96 lines
2.3 KiB
Verilog
96 lines
2.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [3:0] cnt = crc[3:0];
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wire [6:0] decr = crc[14:8];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [3:0] next; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.next (next[3:0]),
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// Inputs
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.cnt (cnt[3:0]),
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.decr (decr[6:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {60'h0, next};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc<10) begin
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sum <= '0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h7cd85c944415d2ef
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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next,
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// Inputs
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cnt, decr
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);
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input [3:0] cnt;
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input signed [6:0] decr;
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output reg [3:0] next;
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always_comb begin
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reg signed [6:0] tmp;
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tmp = 0;
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// verilator lint_off WIDTH
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tmp = ($signed({1'b0, cnt}) - decr);
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// verilator lint_on WIDTH
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if ((tmp > 15)) begin
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next = 15;
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end
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else if ((tmp < 0)) begin
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next = 0;
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end
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else begin
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next = tmp[3:0];
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end
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end
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endmodule
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