44 lines
1.3 KiB
Verilog
44 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//
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// Example module to create problem.
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//
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// generate a 64 bit value with bits
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// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1
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// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1
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// all other bits zero.
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module t_math_imm2 (/*AUTOARG*/
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// Outputs
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LogicImm, LowLogicImm, HighLogicImm,
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// Inputs
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LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot
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);
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input [4:0] LowMaskSel_Top, HighMaskSel_Top;
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input [4:0] LowMaskSel_Bot, HighMaskSel_Bot;
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output [63:0] LogicImm;
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output [63:0] LowLogicImm, HighLogicImm;
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/* verilator lint_off UNSIGNED */
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/* verilator lint_off CMPCONST */
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genvar i;
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generate
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for (i=0;i<64;i=i+1) begin : MaskVal
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if (i >= 32) begin
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assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]);
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assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]);
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end
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else begin
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assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]);
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assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]);
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end
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end
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endgenerate
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assign LogicImm = LowLogicImm & HighLogicImm;
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endmodule
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