76 lines
1.5 KiB
Verilog
76 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [89:0] in;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [89:0] out; // From test of Test.v
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wire [44:0] line0;
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wire [44:0] line1;
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.out (out[89:0]),
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.line0 (line0[44:0]),
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.line1 (line1[44:0]),
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// Inputs
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.clk (clk),
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.in (in[89:0]));
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
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`endif
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cyc <= cyc + 1;
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if (cyc==0) begin
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// Setup
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in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
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end
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else if (cyc==10) begin
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if (in==out) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("*-* Failed!! *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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line0, line1, out,
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// Inputs
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clk, in
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);
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input clk;
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input [89:0] in;
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output reg [44:0] line0;
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output reg [44:0] line1;
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output reg [89:0] out;
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assign {line0,line1} = in;
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always @(posedge clk) begin
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out <= {line0,line1};
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end
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endmodule
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