84 lines
2.2 KiB
Verilog
84 lines
2.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire pick1 = crc[0];
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wire [13:0][1:0] data1 = crc[27+1:1];
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wire [3:0][2:0][1:0] data2 = crc[23+29:29];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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logic [15:0] [1:0] datao; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.datao (datao/*[15:0][1:0]*/),
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// Inputs
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.pick1 (pick1),
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.data1 (data1/*[13:0][1:0]*/),
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.data2 (data2/*[2:0][3:0][1:0]*/));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {32'h0, datao};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h3ff4bf0e6407b281
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test
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(
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input logic pick1,
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input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits
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input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits
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output logic [15:0] [1:0] datao // 16 x 2 = 32 bits
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);
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// verilator lint_off WIDTH
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always_comb datao[13: 0] // 28 bits
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= (pick1)
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? {data1} // 28 bits
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: {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized
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// verilator lint_on WIDTH
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always_comb datao[15:14] = '0;
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endmodule
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