66 lines
1.8 KiB
Verilog
66 lines
1.8 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2004 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=0;
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reg [67:0] r;
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wire and_reduce = &r;
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wire or_reduce = |r;
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wire xor_reduce = ^r;
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wire xnor_reduce = ~^r;
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wire check_equal = r == 68'hffff_ffff_ffff_ffff_f;
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$display("cyc=%0d, r = %x, and_reduce = %x, or=%x xor=%x check_equal = %x",
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cyc, r, and_reduce, or_reduce, xor_reduce, check_equal);
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`endif
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cyc <= cyc + 1;
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if (cyc == 1) begin
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r <= 68'd0;
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end
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else if (cyc == 10) begin
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`checkh(r, 68'h0000_0000_0000_0000_0);
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`checkh(and_reduce, '0);
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`checkh(or_reduce, '0);
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`checkh(xor_reduce, '0);
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`checkh(xnor_reduce, '1);
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r <= 68'hffff_ffff_ffff_ffff_e;
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end
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else if (cyc == 11) begin
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`checkh(r, 68'hffff_ffff_ffff_ffff_e);
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`checkh(and_reduce, '0);
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`checkh(or_reduce, '1);
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`checkh(xor_reduce, '1);
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`checkh(xnor_reduce, '0);
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r <= 68'hffff_ffff_ffff_ffff_f;
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end
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else if (cyc == 12) begin
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`checkh(r, 68'hffff_ffff_ffff_ffff_f);
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`checkh(and_reduce, '1);
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`checkh(or_reduce, '1);
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`checkh(xor_reduce, '0);
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`checkh(xnor_reduce, '1);
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end
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else if (cyc == 90) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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r <= 68'd0;
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end
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end
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endmodule
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