111 lines
3.0 KiB
Verilog
111 lines
3.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2004 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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reg [63:0] rf;
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reg [63:0] rf2;
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reg [63:0] biu;
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reg b;
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always @* begin
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rf[63:32] = biu[63:32] & {32{b}};
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rf[31:0] = {32{b}};
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rf2 = rf;
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rf2[31:0] = ~{32{b}};
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end
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reg [31:0] src1, src0, sr, mask;
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wire [31:0] dualasr
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= ((| src1[31:4])
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? {{16{src0[31]}}, {16{src0[15]}}}
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: ( ( sr & {2{mask[31:16]}})
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| ( {{16{src0[31]}}, {16{src0[15]}}}
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& {2{~mask[31:16]}})));
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wire [31:0] sl_mask
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= (32'hffffffff << src1[4:0]);
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wire [31:0] sr_mask
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= {sl_mask[0], sl_mask[1],
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sl_mask[2], sl_mask[3], sl_mask[4],
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sl_mask[5], sl_mask[6], sl_mask[7],
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sl_mask[8], sl_mask[9],
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sl_mask[10], sl_mask[11],
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sl_mask[12], sl_mask[13], sl_mask[14],
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sl_mask[15], sl_mask[16],
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sl_mask[17], sl_mask[18], sl_mask[19],
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sl_mask[20], sl_mask[21],
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sl_mask[22], sl_mask[23], sl_mask[24],
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sl_mask[25], sl_mask[26],
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sl_mask[27], sl_mask[28], sl_mask[29],
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sl_mask[30], sl_mask[31]};
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wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}};
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wire [1:0] w = {2{b}};
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep);
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`endif
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if (cyc==1) begin
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biu <= 64'h12451282_abadee00;
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b <= 1'b0;
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src1 <= 32'h00000001;
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src0 <= 32'h9a4f1235;
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sr <= 32'h0f19f567;
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mask <= 32'h7af07ab4;
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end
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if (cyc==2) begin
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biu <= 64'h12453382_abad8801;
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b <= 1'b1;
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if (rf != 64'h0) $stop;
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if (rf2 != 64'h00000000ffffffff) $stop;
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src1 <= 32'h0010000f;
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src0 <= 32'h028aa336;
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sr <= 32'h42ad0377;
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mask <= 32'h1ab3b906;
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if (dualasr != 32'h8f1f7060) $stop;
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if (sl_mask != 32'hfffffffe) $stop;
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if (sr_mask != 32'h7fffffff) $stop;
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if (widerep != '0) $stop;
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end
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if (cyc==3) begin
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biu <= 64'h12422382_77ad8802;
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b <= 1'b1;
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if (rf != 64'h12453382ffffffff) $stop;
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if (rf2 != 64'h1245338200000000) $stop;
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src1 <= 32'h0000000f;
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src0 <= 32'h5c158f71;
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sr <= 32'h7076c40a;
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mask <= 32'h33eb3d44;
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if (dualasr != 32'h0000ffff) $stop;
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if (sl_mask != 32'hffff8000) $stop;
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if (sr_mask != 32'h0001ffff) $stop;
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if (widerep != '1) $stop;
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end
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if (cyc==4) begin
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if (rf != 64'h12422382ffffffff) $stop;
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if (rf2 != 64'h1242238200000000) $stop;
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if (dualasr != 32'h3062cc1e) $stop;
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if (sl_mask != 32'hffff8000) $stop;
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if (sr_mask != 32'h0001ffff) $stop;
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$write("*-* All Finished *-*\n");
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if (widerep != '1) $stop;
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$finish;
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end
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end
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end
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endmodule
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