84 lines
2.1 KiB
Verilog
84 lines
2.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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reg [7:0] crc;
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// Build up assignments
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wire [7:0] bitrev;
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assign bitrev[7] = crc[0];
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assign bitrev[6] = crc[1];
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assign bitrev[5] = crc[2];
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assign bitrev[4] = crc[3];
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assign bitrev[0] = crc[7];
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assign bitrev[1] = crc[6];
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assign bitrev[2] = crc[5];
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assign bitrev[3] = crc[4];
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// Build up always assignments
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reg [7:0] bitrevb;
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always @ (/*AS*/crc) begin
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bitrevb[7] = crc[0];
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bitrevb[6] = crc[1];
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bitrevb[5] = crc[2];
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bitrevb[4] = crc[3];
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bitrevb[0] = crc[7];
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bitrevb[1] = crc[6];
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bitrevb[2] = crc[5];
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bitrevb[3] = crc[4];
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end
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// Build up always assignments
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reg [7:0] bitrevr;
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always @ (posedge clk) begin
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bitrevr[7] <= crc[0];
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bitrevr[6] <= crc[1];
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bitrevr[5] <= crc[2];
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bitrevr[4] <= crc[3];
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bitrevr[0] <= crc[7];
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bitrevr[1] <= crc[6];
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bitrevr[2] <= crc[5];
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bitrevr[3] <= crc[4];
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end
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc<=cyc+1;
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//$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev);
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crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
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if (cyc==1) begin
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crc <= 8'hed;
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end
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if (cyc==2 && bitrev!=8'hb7) $stop;
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if (cyc==3 && bitrev!=8'h5b) $stop;
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if (cyc==4 && bitrev!=8'h2d) $stop;
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if (cyc==5 && bitrev!=8'h16) $stop;
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if (cyc==6 && bitrev!=8'h8b) $stop;
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if (cyc==7 && bitrev!=8'hc5) $stop;
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if (cyc==8 && bitrev!=8'he2) $stop;
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if (cyc==9 && bitrev!=8'hf1) $stop;
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if (bitrevb != bitrev) $stop;
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if (cyc==3 && bitrevr!=8'hb7) $stop;
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if (cyc==4 && bitrevr!=8'h5b) $stop;
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if (cyc==5 && bitrevr!=8'h2d) $stop;
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if (cyc==6 && bitrevr!=8'h16) $stop;
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if (cyc==7 && bitrevr!=8'h8b) $stop;
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if (cyc==8 && bitrevr!=8'hc5) $stop;
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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