65 lines
1.4 KiB
Verilog
65 lines
1.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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logic in1 = 1;
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logic [1:0] in2 = 2'b11;
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logic [31:0] out;
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logic [7:0] ones = 8'b11111111;
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logic [9:0] ones10 = 10'b1111111111;
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typedef logic [7:0] data_t;
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typedef logic [9:0] ten_t;
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ten_t out10;
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// verilator lint_off WIDTH
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initial begin
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in1 = 1;
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in2 = 0;
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out = data_t'(in1 << in2);
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if (out != 8'b1) $stop;
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in2 = 1;
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out = data_t'(in1 << in2);
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if (out != 8'b10) $stop;
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in2 = 2;
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out = data_t'(in1 << in2);
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if (out != 8'b100) $stop;
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in2 = 3;
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out = data_t'(in1 << in2);
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if (out != 8'b1000) $stop;
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// Check upper bits get cleared when cast
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in2 = 3;
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out = data_t'(ones << in2);
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if (out != 8'b11111000) $stop;
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in2 = 3;
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out = data_t'(ones10 << in2);
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if (out != 8'b11111000) $stop;
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// bug2597
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out = data_t'(10'h208 >> 2);
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if (out != 8'h82) $stop;
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out = data_t'(10'h208 >> 2);
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if (out != 8'h82) $stop;
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out = data_t'('h208 >> 2);
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if (out != 8'h82) $stop;
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out10 = ten_t'('h404 >> 2);
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if (out10 != 10'h101) $stop;
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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