68 lines
1.5 KiB
Verilog
68 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Peter Debacker.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [10:0] in;
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reg signed[7:0] min;
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reg signed[7:0] max;
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wire signed[7:0] filtered_data;
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reg signed[7:0] delay_minmax[31:0];
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integer k;
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initial begin
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in = 11'b10000001000;
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for(k=0;k<32;k=k+1)
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delay_minmax[k] = 0;
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end
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assign filtered_data = $signed(in[10:3]);
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always @(posedge clk) begin
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in = in + 8;
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`ifdef TEST_VERBOSE
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$write("filtered_data: %d\n", filtered_data);
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`endif
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// delay line shift
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for (k=31;k>0;k=k-1) begin
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delay_minmax[k] = delay_minmax[k-1];
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end
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delay_minmax[0] = filtered_data;
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`ifdef TEST_VERBOSE
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$write("delay_minmax[0] = %d\n", delay_minmax[0]);
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$write("delay_minmax[31] = %d\n", delay_minmax[31]);
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`endif
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// find min and max
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min = 127;
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max = -128;
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`ifdef TEST_VERBOSE
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$write("max init: %d\n", max);
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$write("min init: %d\n", min);
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`endif
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for(k=0;k<32;k=k+1) begin
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if ((delay_minmax[k]) > $signed(max))
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max = delay_minmax[k];
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if ((delay_minmax[k]) < $signed(min))
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min = delay_minmax[k];
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end
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`ifdef TEST_VERBOSE
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$write("max: %d\n", max);
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$write("min: %d\n", min);
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`endif
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if (min == 127) begin
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$stop;
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end
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else if (filtered_data >= -61) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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