105 lines
2.9 KiB
Verilog
105 lines
2.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=0;
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reg [7:0] crc;
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reg [223:0] sum;
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wire [255:0] mglehy = {32{~crc}};
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wire [215:0] drricx = {27{crc}};
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wire [15:0] apqrli = {2{~crc}};
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wire [2:0] szlfpf = crc[2:0];
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wire [15:0] dzosui = {2{crc}};
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wire [31:0] zndrba = {16{crc[1:0]}};
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wire [223:0] bxiouf;
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vliw vliw (
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// Outputs
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.bxiouf (bxiouf),
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// Inputs
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.mglehy (mglehy[255:0]),
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.drricx (drricx[215:0]),
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.apqrli (apqrli[15:0]),
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.szlfpf (szlfpf[2:0]),
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.dzosui (dzosui[15:0]),
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.zndrba (zndrba[31:0]));
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
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if (cyc==0) begin
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// Setup
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crc <= 8'hed;
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sum <= 224'h0;
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end
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else if (cyc<90) begin
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//$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf);
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sum <= {sum[222:0],sum[223]} ^ bxiouf;
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
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if (crc !== 8'b01110000) $stop;
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if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module vliw (
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input[255:0] mglehy,
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input[215:0] drricx,
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input[15:0] apqrli,
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input[2:0] szlfpf,
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input[15:0] dzosui,
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input[31:0] zndrba,
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output wire [223:0] bxiouf
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);
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wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]})
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| ({29{apqrli}} & {mglehy[247:0], drricx});
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wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128])
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| ({21{dzosui}} & zhknfc[335:0]);
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wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
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wire [223:0] rzyeut = viuvoc[335:112];
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assign bxiouf = {rzyeut[7:0],
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rzyeut[15:8],
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rzyeut[23:16],
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rzyeut[31:24],
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rzyeut[39:32],
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rzyeut[47:40],
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rzyeut[55:48],
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rzyeut[63:56],
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rzyeut[71:64],
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rzyeut[79:72],
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rzyeut[87:80],
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rzyeut[95:88],
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rzyeut[103:96],
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rzyeut[111:104],
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rzyeut[119:112],
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rzyeut[127:120],
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rzyeut[135:128],
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rzyeut[143:136],
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rzyeut[151:144],
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rzyeut[159:152],
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rzyeut[167:160],
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rzyeut[175:168],
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rzyeut[183:176],
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rzyeut[191:184],
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rzyeut[199:192],
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rzyeut[207:200],
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rzyeut[215:208],
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rzyeut[223:216]};
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endmodule
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