64 lines
1.2 KiB
Verilog
64 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [7:0] arr [7:0];
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logic [7:0] arri [7:0];
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has_array am1 (.clk(clk), .arri(arr), .arro(arri));
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integer cyc; initial cyc = 0;
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initial begin
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for (int i = 0; i < 8; i++) begin
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arr[i] = 0;
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end
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 5 && arri[1] != 8) begin
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$stop;
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end
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for (int i = 0; i < 7; ++i) begin
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arr[i+1] <= arr[i];
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end
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arr[0] <= arr[0] + 1;
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end
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endmodule : t
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module has_array (
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input clk,
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input logic [7:0] arri [7:0],
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output logic [7:0] arro [7:0]
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);
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integer cyc; initial cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (arri[0] == 10 && cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @(posedge clk) begin
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for (integer i = 0; i < 7; ++i) begin
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arro[i+1] <= arro[i];
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end
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arro[0] = arro[0] + 2;
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end
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endmodule : has_array
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