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67 lines
1.3 KiB
Verilog
67 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005-2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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reg [3:0] value;
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reg [3:0] valuex;
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// verilator lint_off CASEOVERLAP
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// verilator lint_off CASEWITHX
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// verilator lint_off CASEX
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// Note for Verilator Xs must become zeros, or the Xs may match.
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initial begin
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value = 4'b1001;
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valuex = 4'b1xxx;
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case (value)
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4'b1xxx: $stop;
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4'b1???: $stop;
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4'b1001: ;
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default: $stop;
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endcase
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case (valuex)
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4'b1???: $stop;
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4'b1xxx: ;
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4'b1001: ;
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4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
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default: $stop;
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endcase
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//
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casex (value)
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4'b100x: ;
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default: $stop;
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endcase
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casex (value)
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4'b100?: ;
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default: $stop;
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endcase
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casex (valuex)
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4'b100x: ;
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default: $stop;
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endcase
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casex (valuex)
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4'b100?: ;
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default: $stop;
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endcase
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//
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casez (value)
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4'bxxxx: $stop;
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4'b100?: ;
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default: $stop;
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endcase
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casez (valuex)
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4'b1xx?: ;
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4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
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default: $stop;
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endcase
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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