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29 lines
601 B
Verilog
29 lines
601 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// bug475
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module t();
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function real get_real_one;
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input ignored;
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get_real_one = 1.1;
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endfunction
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localparam R_PARAM = get_real_one(1'b0);
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localparam R_PARAM_2 = (R_PARAM > 0);
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generate
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initial begin
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if (R_PARAM != 1.1) $stop;
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if (R_PARAM_2 != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endgenerate
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endmodule
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