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38 lines
891 B
Verilog
38 lines
891 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module foo
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#( parameter real bar = 2.0)
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();
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endmodule
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module t();
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genvar m, r;
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generate
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for (m = 10; m <= 20; m+=10) begin : gen_m
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for (r = 0; r <= 1; r++) begin : gen_r
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localparam real lparam = m + (r + 0.5);
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initial begin
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if (lparam != foo_inst.bar) begin
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$display("%m: lparam != foo_inst.bar (%f, %f)",
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lparam, foo_inst.bar);
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$stop();
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end
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end
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foo #(.bar (lparam)) foo_inst ();
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end
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end
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endgenerate
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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