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94 lines
2.1 KiB
Verilog
94 lines
2.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [6:0] mem1d;
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reg [6:0] mem2d [5:0];
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reg [6:0] mem3d [4:0][5:0];
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integer i,j,k;
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// Four different test cases for out of bounds
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// =
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// <=
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// Continuous assigns
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// Output pin interconnect (also covers cont assigns)
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// Each with both bit selects and array selects
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initial begin
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mem1d[0] = 1'b0;
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i=7;
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mem1d[i] = 1'b1;
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if (mem1d[0] !== 1'b0) $stop;
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//
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for (i=0; i<8; i=i+1) begin
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for (j=0; j<8; j=j+1) begin
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for (k=0; k<8; k=k+1) begin
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mem1d[k] = k[0];
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mem2d[j][k] = j[0]+k[0];
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mem3d[i][j][k] = i[0]+j[0]+k[0];
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end
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end
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end
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for (i=0; i<5; i=i+1) begin
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for (j=0; j<6; j=j+1) begin
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for (k=0; k<7; k=k+1) begin
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if (mem1d[k] !== k[0]) $stop;
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if (mem2d[j][k] !== j[0]+k[0]) $stop;
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if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop;
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end
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end
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end
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end
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integer wi;
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wire [31:0] wd = cyc;
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reg [31:0] reg2d[6:0];
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always @ (posedge clk) reg2d[wi[2:0]] <= wd;
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd);
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`endif
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cyc <= cyc + 1;
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if (cyc<10) begin
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wi <= 0;
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end
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else if (cyc==10) begin
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wi <= 1;
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end
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else if (cyc==11) begin
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if (reg2d[0] !== 10) $stop;
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wi <= 6;
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end
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else if (cyc==12) begin
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if (reg2d[0] !== 10) $stop;
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if (reg2d[1] !== 11) $stop;
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wi <= 7; // Will be ignored
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end
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else if (cyc==13) begin
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if (reg2d[0] !== 10) $stop;
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if (reg2d[1] !== 11) $stop;
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if (reg2d[6] !== 12) $stop;
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end
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else if (cyc==14) begin
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if (reg2d[0] !== 10) $stop;
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if (reg2d[1] !== 11) $stop;
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if (reg2d[6] !== 12) $stop;
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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