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83 lines
1.7 KiB
Verilog
83 lines
1.7 KiB
Verilog
`include "hvsync_generator.v"
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`include "digits10.v"
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module RAM_1KB(clk, addr, din, dout, we);
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input clk; // clock
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input [9:0] addr; // 10-bit address
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input [7:0] din; // 8-bit data input
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output [7:0] dout; // 8-bit data output
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input we; // write enable
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reg [7:0] mem [1024]; // 1024x8 bit memory
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always @(posedge clk) begin
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if (we) // if write enabled
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mem[addr] <= din; // write memory from din
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dout <= mem[addr]; // read memory to dout
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end
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endmodule
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module test_framebuf_top(
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input clk, reset,
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output hsync, vsync,
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output [2:0] rgb
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);
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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wire [9:0] ram_addr;
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wire [7:0] ram_read;
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reg [7:0] ram_write;
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reg ram_writeenable = 0;
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RAM_1KB ram(
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.clk(clk),
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.dout(ram_read),
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.din(ram_write),
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.addr(ram_addr),
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.we(ram_writeenable)
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);
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire [4:0] row = vpos[7:3];
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wire [4:0] col = hpos[7:3];
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wire [3:0] digit = ram_read[3:0];
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wire [2:0] yofs = vpos[2:0];
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wire [2:0] xofs = hpos[2:0];
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wire [4:0] bits;
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assign ram_addr = {row,col};
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digits10_case numbers(
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.digit(digit),
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.yofs(yofs),
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.bits(bits)
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);
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wire r = display_on && 0;
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wire g = display_on && bits[~xofs];
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wire b = display_on && 0;
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assign rgb = {b,g,r};
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always @(posedge clk)
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if (display_on && vpos[2:0] == 7)
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case (hpos[2:0])
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6: begin
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ram_write <= (ram_read + 1);
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ram_writeenable <= 1;
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end
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7: ram_writeenable <= 0;
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endcase
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endmodule
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