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85 lines
1.9 KiB
Verilog
85 lines
1.9 KiB
Verilog
`include "hvsync_generator.v"
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module car_bitmap(
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input [3:0] yofs,
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output [7:0] bits
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);
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reg [7:0] bitarray[16];
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assign bits = bitarray[yofs];
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initial begin/*{w:8,h:16}*/
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bitarray[0] = 8'b0;
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bitarray[1] = 8'b101110;
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bitarray[2] = 8'b11101110;
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bitarray[3] = 8'b11111110;
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bitarray[4] = 8'b11101110;
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bitarray[5] = 8'b1101110;
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bitarray[6] = 8'b110000;
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bitarray[7] = 8'b110000;
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bitarray[8] = 8'b110000;
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bitarray[9] = 8'b1110000;
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bitarray[10] = 8'b1100000;
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bitarray[11] = 8'b11100000;
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bitarray[12] = 8'b11101100;
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bitarray[13] = 8'b11111100;
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bitarray[14] = 8'b11001100;
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bitarray[15] = 8'b1100;
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end
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endmodule
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module sprite_bitmap_top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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reg sprite_active;
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reg [3:0] car_sprite_xofs;
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reg [3:0] car_sprite_yofs;
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wire [7:0] car_sprite_bits;
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reg [8:0] player_x = 128;
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reg [8:0] player_y = 128;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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car_bitmap car(
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.yofs(car_sprite_yofs),
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.bits(car_sprite_bits));
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always @(posedge hsync)
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// start sprite?
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if (vpos == player_y)
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car_sprite_yofs <= 15;
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else if (car_sprite_yofs != 0)
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car_sprite_yofs <= car_sprite_yofs - 1;
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always @(posedge clk)
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if (hpos == player_x)
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car_sprite_xofs <= 15;
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else if (car_sprite_xofs != 0)
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car_sprite_xofs <= car_sprite_xofs - 1;
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// mirror sprite in X direction
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wire [3:0] car_bit = car_sprite_xofs>=8 ?
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15-car_sprite_xofs:
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car_sprite_xofs;
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wire car_gfx = car_sprite_bits[3'(car_bit)];
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wire r = display_on && car_gfx;
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wire g = display_on && car_gfx;
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wire b = display_on && car_gfx;
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assign rgb = {b,g,r};
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endmodule
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