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115 lines
2.2 KiB
Verilog
115 lines
2.2 KiB
Verilog
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`ifndef SCOREBOARD_H
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`define SCOREBOARD_H
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`include "hvsync_generator.v"
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`include "digits10.v"
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/*
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player_stats - Holds two-digit score and one-digit lives counter.
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scoreboard_generator - Outputs video signal with score/lives digits.
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*/
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module player_stats(reset, score0, score1, lives, incscore, declives);
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input reset;
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output reg [3:0] score0;
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output reg [3:0] score1;
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input incscore;
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output reg [3:0] lives;
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input declives;
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always @(posedge incscore or posedge reset)
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begin
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if (reset) begin
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score0 <= 0;
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score1 <= 0;
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end else if (score0 == 9) begin
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score0 <= 0;
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score1 <= score1 + 1;
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end else begin
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score0 <= score0 + 1;
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end
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end
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always @(posedge declives or posedge reset)
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begin
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if (reset)
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lives <= 3;
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else if (lives != 0)
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lives <= lives - 1;
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end
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endmodule
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module scoreboard_generator(score0, score1, lives, vpos, hpos, board_gfx);
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input [3:0] score0;
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input [3:0] score1;
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input [3:0] lives;
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input [9:0] vpos;
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input [9:0] hpos;
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output board_gfx;
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reg [3:0] score_digit;
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reg [4:0] score_bits;
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always @(*)
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begin
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case (hpos[8:6])
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1: score_digit = score1;
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2: score_digit = score0;
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6: score_digit = lives;
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default: score_digit = 15; // no digit
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endcase
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end
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digits10_array digits(
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.digit(score_digit),
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.yofs(vpos[5:3]),
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.bits(score_bits)
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);
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assign board_gfx = score_bits[hpos[5:3] ^ 3'b111];
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endmodule
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module scoreboard_top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [9:0] hpos;
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wire [9:0] vpos;
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wire board_gfx;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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scoreboard_generator scoreboard_gen(
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.score0(0),
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.score1(1),
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.lives(3),
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.vpos(vpos),
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.hpos(hpos),
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.board_gfx(board_gfx)
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);
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wire r = display_on && board_gfx;
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wire g = display_on && board_gfx;
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wire b = display_on && board_gfx;
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assign rgb = {b,g,r};
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endmodule
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`endif
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