diff --git a/src/BusMonCore.vhd b/src/BusMonCore.vhd
index 199c526..f3e3c27 100644
--- a/src/BusMonCore.vhd
+++ b/src/BusMonCore.vhd
@@ -84,14 +84,14 @@ entity BusMonCore is
         avr_RxD          : in    std_logic;
         avr_TxD          : out   std_logic;
 
-        -- GODIL Switches
-        sw1              : in    std_logic;
-        nsw2             : in    std_logic;
+        -- Switches
+        sw_interrupt    : in    std_logic;
+        sw_reset        : in    std_logic;
 
-        -- GODIL LEDs
-        led3             : out   std_logic;
-        led6             : out   std_logic;
-        led8             : out   std_logic;
+        -- LEDs
+        led_bkpt        : out   std_logic;
+        led_trig0       : out   std_logic;
+        led_trig1       : out   std_logic;
 
         -- OHO_DY1 connected to test connector
         tmosi            : out   std_logic;
@@ -213,7 +213,7 @@ begin
         portdin(3)           => '0',
         portdin(4)           => '0',
         portdin(5)           => '0',
-        portdin(6)           => sw1,
+        portdin(6)           => sw_interrupt,
         portdin(7)           => fifo_empty_n,
 
         portdout(0)           => muxsel(0),
@@ -258,16 +258,16 @@ begin
     -- bw_state1(1) is 1 for writes, and 0 for reads
     fifo_din <= cycleCount_inst & "0000" & bw_status1 & Data1 & Addr1 & addr_inst;
 
-    led3 <= not trig(0);       -- red
-    led6 <= not trig(1);       -- red
-    led8 <= not brkpt_active;  -- green
+    led_trig0 <= trig(0);
+    led_trig1 <= trig(1);
+    led_bkpt  <= brkpt_active;
 
-    nrst_avr <= nsw2;
+    nrst_avr <= not sw_reset;
 
     -- OHO DY1 Display for Testing
     dy_data(0) <= hex & "0000" & Addr(3 downto 0);
     dy_data(1) <= hex & "0000" & Addr(7 downto 4);
-    dy_data(2) <= hex & "0000" & "00" & (not nsw2) & sw1;
+    dy_data(2) <= hex & "0000" & "00" & sw_reset & sw_interrupt;
 
     mux <= addr_inst(7 downto 0)            when muxsel = 0 else
            addr_inst(15 downto 8)           when muxsel = 1 else
diff --git a/src/MC6809CpuMon.vhd b/src/MC6809CpuMon.vhd
index 22c07ba..7f0049f 100644
--- a/src/MC6809CpuMon.vhd
+++ b/src/MC6809CpuMon.vhd
@@ -144,10 +144,6 @@ architecture behavioral of MC6809CpuMon is
     signal IRQ_n_masked   : std_logic;
     signal FIRQ_n_masked  : std_logic;
 
-    signal led_trig0_n    : std_logic;
-    signal led_trig1_n    : std_logic;
-    signal led_bkpt_n     : std_logic;
-
 begin
 
     LIC     <= LIC_int;
@@ -158,10 +154,6 @@ begin
     -- The following inputs are not implemented
     -- DMA_n_BREQ_n  (6809 mode)
 
-    led_trig0 <= not led_trig0_n;
-    led_trig1 <= not led_trig1_n;
-    led_bkpt <= not led_bkpt_n;
-
     inst_dcm0 : entity work.DCM0
       generic map (
         ClkMult      => ClkMult,
@@ -198,11 +190,11 @@ begin
         trig         => trig,
         avr_RxD      => avr_RxD,
         avr_TxD      => avr_TxD,
-        sw1          => sw_interrupt,
-        nsw2         => not sw_reset,
-        led3         => led_trig0_n,
-        led6         => led_trig1_n,
-        led8         => led_bkpt_n,
+        sw_interrupt => sw_interrupt,
+        sw_reset     => sw_reset,
+        led_bkpt     => led_bkpt,
+        led_trig0    => led_trig0,
+        led_trig1    => led_trig1,
         tmosi        => tmosi,
         tdin         => tdin,
         tcclk        => tcclk,
diff --git a/src/MOS6502CpuMonCore.vhd b/src/MOS6502CpuMonCore.vhd
index b7880b0..2384442 100644
--- a/src/MOS6502CpuMonCore.vhd
+++ b/src/MOS6502CpuMonCore.vhd
@@ -113,16 +113,8 @@ architecture behavioral of MOS6502CpuMonCore is
     signal NMI_n_masked  : std_logic;
     signal IRQ_n_masked  : std_logic;
 
-    signal led_trig0_n    : std_logic;
-    signal led_trig1_n    : std_logic;
-    signal led_bkpt_n     : std_logic;
-
 begin
 
-    led_trig0 <= not led_trig0_n;
-    led_trig1 <= not led_trig1_n;
-    led_bkpt  <= not led_bkpt_n;
-
     mon : entity work.BusMonCore
     generic map (
         num_comparators   => num_comparators,
@@ -148,11 +140,11 @@ begin
         trig         => trig,
         avr_RxD      => avr_RxD,
         avr_TxD      => avr_TxD,
-        sw1          => sw_interrupt,
-        nsw2         => not sw_reset,
-        led3         => led_trig0_n,
-        led6         => led_trig1_n,
-        led8         => led_bkpt_n,
+        sw_interrupt => sw_interrupt,
+        sw_reset     => sw_reset,
+        led_bkpt     => led_bkpt,
+        led_trig0    => led_trig0,
+        led_trig1    => led_trig1,
         tmosi        => tmosi,
         tdin         => tdin,
         tcclk        => tcclk,
diff --git a/src/Z80CpuMon.vhd b/src/Z80CpuMon.vhd
index dedffc0..95e8b17 100644
--- a/src/Z80CpuMon.vhd
+++ b/src/Z80CpuMon.vhd
@@ -182,17 +182,8 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
 
     signal rfsh_addr      : std_logic_vector(15 downto 0);
 
-    signal led_trig0_n    : std_logic;
-    signal led_trig1_n    : std_logic;
-    signal led_bkpt_n     : std_logic;
-
 begin
 
-    led_trig0 <= not led_trig0_n;
-    led_trig1 <= not led_trig1_n;
-    led_bkpt <= not led_bkpt_n;
-
-
     --------------------------------------------------------
     -- Clocking
     --------------------------------------------------------
@@ -240,11 +231,11 @@ begin
         trig         => trig,
         avr_RxD      => avr_RxD,
         avr_TxD      => avr_TxD_int,
-        sw1          => '0',
-        nsw2         => not sw_reset,
-        led3         => led_trig0_n,
-        led6         => led_trig1_n,
-        led8         => led_bkpt_n,
+        sw_interrupt => '0',
+        sw_reset     => sw_reset,
+        led_bkpt     => led_bkpt,
+        led_trig0    => led_trig0,
+        led_trig1    => led_trig1,
         tmosi        => tmosi,
         tdin         => tdin,
         tcclk        => tcclk,