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Routed four test signals to J5

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Change-Id: Ife39830dc193486c4af66bd49bc5680cab285108
This commit is contained in:
David Banks 2021-11-18 14:59:30 +00:00
parent 3e7bda697c
commit 08116e5f21
5 changed files with 45 additions and 26 deletions
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8
src/MOS6502CpuMon.vhd
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@ -69,7 +69,10 @@ entity MOS6502CpuMon is
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
tcclk : out std_logic;
-- Test connector signals
test : inout std_logic_vector(3 downto 0)
);
end MOS6502CpuMon;
@ -141,7 +144,8 @@ begin
led_trig1 => led_trig1,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
tcclk => tcclk,
test => test
);
sync_gen : process(cpu_clk)

10
src/MOS6502CpuMonALS.vhd
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@ -90,7 +90,10 @@ entity MOS6502CpuMonALS is
-- OHO_DY1 LED display
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
tcclk : out std_logic;
-- Test connector signals
test : inout std_logic_vector(3 downto 0)
);
end MOS6502CpuMonALS;
@ -166,7 +169,10 @@ begin
-- OHO_DY1 LED display
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
tcclk => tcclk,
-- Test signals
test => test
);
-- 6502 Outputs

11
src/MOS6502CpuMonCore.vhd
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@ -67,7 +67,10 @@ entity MOS6502CpuMonCore is
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
tcclk : out std_logic;
-- Test connector signals
test : inout std_logic_vector(3 downto 0)
);
end MOS6502CpuMonCore;
@ -391,4 +394,10 @@ begin
memory_din <= Din;
-- Test outputs
test(0) <= SS_Single; -- GODIL J5 pin 1 (46)
test(1) <= 'Z'; -- GODIL J5 pin 2 (47)
test(2) <= 'Z'; -- GODIL J5 pin 3 (48)
test(3) <= 'Z'; -- GODIL J5 pin 4 (56)
end behavioral;

8
target/lx9_dave/ice6502/board.ucf
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@ -88,7 +88,7 @@ NET "tdin" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "tcclk" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# Test outputs (connect to J5 on FPGA board)
#NET "test1" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test2" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test3" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test4" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test<0>" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test<1>" LOC="P47" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test<2>" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test<3>" LOC="P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

8
target/lx9_dave/ice65c02/board.ucf
View File

@ -88,7 +88,7 @@ NET "tdin" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "tcclk" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# Test outputs (connect to J5 on FPGA board)
#NET "test1" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test2" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test3" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test4" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test<0>" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test<1>" LOC="P47" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test<2>" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "test<3>" LOC="P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;