mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-12-22 16:30:06 +00:00
Implemented cycle counter and data bus monitoring during read/write watches/breakpoints, incremented version to 0.32
Change-Id: I408f57e66800ea58a56896ec4af5d815d1f12c34
This commit is contained in:
David Banks
parent
643c9b2231
commit
14e4adda94
BIN
AtomCpuMon.bit
BIN
AtomCpuMon.bit
Binary file not shown.
@ -67,22 +67,34 @@ unsigned char dopaddr[256] =
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#define MUX_DDR DDRE
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#define MUX_DIN PINE
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// Hardware registers
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#define OFFSET_IAL 0
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#define OFFSET_IAH 1
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#define OFFSET_BW_IAL 2
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#define OFFSET_BW_IAH 3
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#define OFFSET_BW_BAL 4
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#define OFFSET_BW_BAH 5
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#define OFFSET_BW_M 6
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#define OFFSET_DATA 7
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#define OFFSET_REG_A 8
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#define OFFSET_REG_X 9
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#define OFFSET_REG_Y 10
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#define OFFSET_REG_P 11
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#define OFFSET_REG_SPL 12
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#define OFFSET_REG_SPH 13
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#define OFFSET_REG_PCL 14
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#define OFFSET_REG_PCH 15
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#define OFFSET_DATA 2
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#define OFFSET_CNTH 3
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#define OFFSET_CNTL 4
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#define OFFSET_CNTM 5
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// Hardware fifo
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#define OFFSET_BW_IAL 6
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#define OFFSET_BW_IAH 7
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#define OFFSET_BW_BAL 8
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#define OFFSET_BW_BAH 9
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#define OFFSET_BW_BD 10
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#define OFFSET_BW_M 11
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#define OFFSET_BW_CNTL 12
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#define OFFSET_BW_CNTM 13
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#define OFFSET_BW_CNTH 14
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// Processor registers
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#define OFFSET_REG_A 16
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#define OFFSET_REG_X 17
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#define OFFSET_REG_Y 18
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#define OFFSET_REG_P 19
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#define OFFSET_REG_SPL 20
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#define OFFSET_REG_SPH 21
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#define OFFSET_REG_PCL 22
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#define OFFSET_REG_PCH 23
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// Commands
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// 000x Enable/Disable single strpping
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@ -105,7 +117,7 @@ unsigned char dopaddr[256] =
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// Control bits
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#define CMD_MASK 0x1F
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#define CMD_EDGE 0x10
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#define MUXSEL_MASK 0x0F
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#define MUXSEL_MASK 0x1F
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#define MUXSEL_BIT 0
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// Status bits
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@ -113,24 +125,27 @@ unsigned char dopaddr[256] =
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#define BW_ACTIVE_MASK 0x80
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// Breakpoint Modes
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#define BRKPT_INSTR 0
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#define BRKPT_EXEC 0
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#define BRKPT_READ 1
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#define BRKPT_WRITE 2
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#define WATCH_INSTR 3
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#define WATCH_EXEC 3
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#define WATCH_READ 4
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#define WATCH_WRITE 5
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#define UNDEFINED 6
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#define B_MASK ((1<<BRKPT_READ) | (1<<BRKPT_WRITE) | (1<<BRKPT_EXEC))
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#define W_MASK ((1<<WATCH_READ) | (1<<WATCH_WRITE) | (1<<WATCH_EXEC))
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#define B_MEM_MASK ((1<<BRKPT_READ) | (1<<BRKPT_WRITE))
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#define W_MEM_MASK ((1<<BRKPT_WRITE) | (1<<WATCH_WRITE))
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#define BW_MEM_MASK ((1<<BRKPT_READ) | (1<<BRKPT_WRITE) | (1<<WATCH_READ) | (1<<WATCH_WRITE))
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char *modeStrings[7] = {
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"Instruction breakpoint",
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"Read breakpoint",
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"Write breakpoint",
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"Instruction watch",
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"Read watch",
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"Write watch",
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"Ex Breakpoint",
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"Rn Breakpoint",
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"Wr Breakpoint",
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"Ex watch",
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"Rd watch",
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"Wr watch",
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"Undefined"
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};
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@ -157,7 +172,7 @@ char *triggerStrings[NUM_TRIGGERS] = {
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};
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#define VERSION "0.31"
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#define VERSION "0.32"
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#ifdef EMBEDDED_6502
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#define NUM_CMDS 25
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@ -530,20 +545,41 @@ void logTrigger(int trigger) {
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}
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}
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void logCycleCount(int offsetLow, int offsetHigh) {
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unsigned long count = (((unsigned long) hwRead8(offsetHigh)) << 16) | hwRead16(offsetLow);
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unsigned long countSecs = count / 1000000;
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unsigned long countMicros = count % 1000000;
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log0("%02ld.%06ld: ", countSecs, countMicros);
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}
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int logDetails() {
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unsigned int i_addr = hwRead16(OFFSET_BW_IAL);
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unsigned int b_addr = hwRead16(OFFSET_BW_BAL);
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unsigned int b_data = hwRead8(OFFSET_BW_BD);
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unsigned int mode = hwRead8(OFFSET_BW_M);
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unsigned int watch = mode & 8;
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// Convert from 4-bit compressed to 6 bit expanded mode representation
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if (watch) {
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mode = (mode & 7) << 3;
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}
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// Update the serial console
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if (mode & W_MASK) {
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logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
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}
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logMode(mode);
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log0(" hit at %04X", i_addr);
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if (mode & BW_MEM_MASK) {
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log0(" accessing %04X\n", b_addr);
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if (mode & W_MEM_MASK) {
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log0(" writing");
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} else {
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log0(" reading");
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}
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log0(" %04X = %02X\n", b_addr, b_data);
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if (mode & B_MASK) {
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logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
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}
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if (mode & B_MEM_MASK) {
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// It's only safe to do this for brkpts, as it makes memory accesses
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disMem(i_addr);
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@ -563,6 +599,7 @@ void logAddr() {
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lcdAddr(memAddr);
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#endif
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// Update the serial console
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logCycleCount(OFFSET_CNTL, OFFSET_CNTH);
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#ifdef EMBEDDED_6502
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//log0("%04X\n", i_addr);
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disMem(memAddr);
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@ -785,7 +822,7 @@ void doCmdBreak(char *params, unsigned int mode) {
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}
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void doCmdBreakI(char *params) {
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doCmdBreak(params, 1 << BRKPT_INSTR);
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doCmdBreak(params, 1 << BRKPT_EXEC);
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}
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void doCmdBreakR(char *params) {
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@ -797,7 +834,7 @@ void doCmdBreakW(char *params) {
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}
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void doCmdWatchI(char *params) {
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doCmdBreak(params, 1 << WATCH_INSTR);
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doCmdBreak(params, 1 << WATCH_EXEC);
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}
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void doCmdWatchR(char *params) {
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@ -835,7 +872,7 @@ void doCmdBClear(char *params, unsigned int mode) {
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}
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void doCmdBClearI(char *params) {
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doCmdBClear(params, 1 << BRKPT_INSTR);
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doCmdBClear(params, 1 << BRKPT_EXEC);
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}
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void doCmdBClearR(char *params) {
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@ -847,7 +884,7 @@ void doCmdBClearW(char *params) {
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}
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void doCmdWClearI(char *params) {
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doCmdBClear(params, 1 << WATCH_INSTR);
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doCmdBClear(params, 1 << WATCH_EXEC);
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}
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void doCmdWClearR(char *params) {
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@ -44,10 +44,10 @@ ENTITY WatchEvents IS
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PORT (
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clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
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din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
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dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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@ -59,10 +59,10 @@ COMPONENT wrapped_WatchEvents
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PORT (
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clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
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din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
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dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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@ -98,7 +98,7 @@ END COMPONENT;
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c_count_type => 0,
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c_data_count_width => 10,
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c_default_value => "BlankString",
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c_din_width => 36,
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c_din_width => 72,
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c_din_width_axis => 1,
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c_din_width_rach => 32,
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c_din_width_rdch => 64,
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@ -106,7 +106,7 @@ END COMPONENT;
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c_din_width_wdch => 64,
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c_din_width_wrch => 2,
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c_dout_rst_val => "0",
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c_dout_width => 36,
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c_dout_width => 72,
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c_enable_rlocs => 0,
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c_enable_rst_sync => 1,
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c_error_injection_type => 0,
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@ -179,7 +179,7 @@ END COMPONENT;
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c_overflow_low => 0,
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c_preload_latency => 0,
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c_preload_regs => 1,
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c_prim_fifo_type => "512x36",
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c_prim_fifo_type => "512x72",
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c_prog_empty_thresh_assert_val => 4,
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c_prog_empty_thresh_assert_val_axis => 1022,
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c_prog_empty_thresh_assert_val_rach => 1022,
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@ -52,8 +52,8 @@
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<!-- -->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="WatchEvents" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-11T21:55:14" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="644897288B5B4D69FBBB8BE6A3296EA1" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-20T07:31:35" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D9477A1DD499DA00CBCF8BE78B7D99A6" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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@ -1,5 +1,5 @@
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#!/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/xtclsh
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project open AtomBusMon.xise
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project open AtomCpuMon.xise
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process run "Generate Programming File"
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project close
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exit
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@ -1,5 +1,5 @@
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#!/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/xtclsh
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project open AtomBusMon.xise
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project open AtomCpuMon.xise
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project clean
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project close
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exit
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@ -103,6 +103,7 @@ begin
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mon : entity work.BusMonCore port map (
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clock49 => clock49,
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Addr => Addr_int,
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Data => Data,
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Phi2 => busmon_clk,
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RNW => R_W_n_int,
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Sync => Sync_int,
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@ -128,7 +129,7 @@ begin
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WrOut => memory_wr,
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AddrOut => memory_addr,
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DataOut => memory_dout,
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DataIn => memory_din
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DataIn => memory_din
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);
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GenT65Core: if UseT65Core generate
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@ -26,13 +26,14 @@ entity BusMonCore is
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generic (
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num_comparators : integer := 8;
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reg_width : integer := 42;
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fifo_width : integer := 36
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fifo_width : integer := 72
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);
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port (
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clock49 : in std_logic;
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-- 6502 Signals
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Addr : in std_logic_vector(15 downto 0);
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Data : in std_logic_vector(7 downto 0);
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Phi2 : in std_logic;
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RNW : in std_logic;
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Sync : in std_logic;
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@ -40,9 +41,11 @@ entity BusMonCore is
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nRST : inout std_logic;
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-- 6502 Registers
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-- unused in pure bus monitor mode
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Regs : in std_logic_vector(63 downto 0);
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-- 6502 Memory Read/Write
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-- unused in pure bus monitor mode
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RdOut : out std_logic;
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WrOut : out std_logic;
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AddrOut : out std_logic_vector(15 downto 0);
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@ -80,48 +83,56 @@ end BusMonCore;
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architecture behavioral of BusMonCore is
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signal clock_avr : std_logic;
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signal nrst_avr : std_logic;
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signal lcd_rw_int : std_logic;
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signal lcd_db_in : std_logic_vector(7 downto 4);
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signal lcd_db_out : std_logic_vector(7 downto 4);
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signal dy_counter : std_logic_vector(31 downto 0);
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signal dy_data : y2d_type ;
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signal clock_avr : std_logic;
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signal nrst_avr : std_logic;
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signal lcd_rw_int : std_logic;
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signal lcd_db_in : std_logic_vector(7 downto 4);
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signal lcd_db_out : std_logic_vector(7 downto 4);
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signal dy_counter : std_logic_vector(31 downto 0);
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signal dy_data : y2d_type ;
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signal mux : std_logic_vector(7 downto 0);
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signal muxsel : std_logic_vector(3 downto 0);
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signal cmd_edge : std_logic;
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signal cmd_edge1 : std_logic;
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signal cmd_edge2 : std_logic;
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signal cmd : std_logic_vector(3 downto 0);
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signal mux : std_logic_vector(7 downto 0);
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signal muxsel : std_logic_vector(4 downto 0);
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signal cmd_edge : std_logic;
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signal cmd_edge1 : std_logic;
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signal cmd_edge2 : std_logic;
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signal cmd : std_logic_vector(3 downto 0);
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signal addr_sync : std_logic_vector(15 downto 0);
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signal addr_inst : std_logic_vector(15 downto 0);
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signal addr_sync : std_logic_vector(15 downto 0);
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signal addr_inst : std_logic_vector(15 downto 0);
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signal Addr1 : std_logic_vector(15 downto 0);
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signal Data1 : std_logic_vector(7 downto 0);
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signal single : std_logic;
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signal reset : std_logic;
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signal step : std_logic;
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signal cycleCount : std_logic_vector(23 downto 0);
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signal cycleCount_inst : std_logic_vector(23 downto 0);
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signal bw_status : std_logic_vector(fifo_width - 16 - 1 downto 0);
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signal bw_status1 : std_logic_vector(fifo_width - 16 - 1 downto 0);
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signal single : std_logic;
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signal reset : std_logic;
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signal step : std_logic;
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signal bw_status : std_logic_vector(3 downto 0);
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signal bw_status1 : std_logic_vector(3 downto 0);
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signal brkpt_reg : std_logic_vector(num_comparators * reg_width - 1 downto 0);
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signal brkpt_enable : std_logic;
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signal brkpt_active : std_logic;
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signal brkpt_active1 : std_logic;
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signal watch_active : std_logic;
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signal fifo_din : std_logic_vector(fifo_width - 1 downto 0);
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signal fifo_dout : std_logic_vector(fifo_width - 1 downto 0);
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signal fifo_empty : std_logic;
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signal fifo_rd : std_logic;
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signal fifo_wr : std_logic;
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signal fifo_rst : std_logic;
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signal brkpt_reg : std_logic_vector(num_comparators * reg_width - 1 downto 0);
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signal brkpt_enable : std_logic;
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signal brkpt_active : std_logic;
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signal brkpt_active1 : std_logic;
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signal watch_active : std_logic;
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signal fifo_din : std_logic_vector(fifo_width - 1 downto 0);
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signal fifo_dout : std_logic_vector(fifo_width - 1 downto 0);
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signal fifo_empty : std_logic;
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signal fifo_rd : std_logic;
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signal fifo_wr : std_logic;
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signal fifo_rst : std_logic;
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signal memory_rd : std_logic;
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signal memory_wr : std_logic;
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signal addr_dout_reg : std_logic_vector(23 downto 0);
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signal din_reg : std_logic_vector(7 downto 0);
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signal memory_rd : std_logic;
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signal memory_wr : std_logic;
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signal addr_dout_reg : std_logic_vector(23 downto 0);
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signal din_reg : std_logic_vector(7 downto 0);
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signal Rdy_int : std_logic;
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begin
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@ -202,7 +213,7 @@ begin
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portdout(1) => muxsel(1),
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portdout(2) => muxsel(2),
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portdout(3) => muxsel(3),
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portdout(4) => open,
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portdout(4) => muxsel(4),
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portdout(5) => open,
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portdout(6) => open,
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portdout(7) => open,
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@ -230,8 +241,12 @@ begin
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empty => fifo_empty
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);
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|
||||
fifo_din <= bw_status1 & addr_inst;
|
||||
-- The fifo is writen the cycle after the break point
|
||||
-- Addr1 is the address bus delayed by 1 cycle
|
||||
-- DataWr1 is the data being written delayed by 1 cycle
|
||||
-- DataRd is the data being read, that is already one cycle late
|
||||
-- bw_state1(1) is 1 for writes, and 0 for reads
|
||||
fifo_din <= cycleCount_inst & "0000" & bw_status1 & Data1 & Addr1 & addr_inst;
|
||||
|
||||
lcd_rw <= lcd_rw_int;
|
||||
lcd_db <= lcd_db_out when lcd_rw_int = '0' else (others => 'Z');
|
||||
@ -250,20 +265,29 @@ begin
|
||||
|
||||
mux <= addr_inst(7 downto 0) when muxsel = 0 else
|
||||
addr_inst(15 downto 8) when muxsel = 1 else
|
||||
fifo_dout(7 downto 0) when muxsel = 2 else
|
||||
fifo_dout(15 downto 8) when muxsel = 3 else
|
||||
fifo_dout(23 downto 16) when muxsel = 4 else
|
||||
fifo_dout(31 downto 24) when muxsel = 5 else
|
||||
"0000" & fifo_dout(35 downto 32) when muxsel = 6 else
|
||||
din_reg when muxsel = 7 else
|
||||
Regs(7 downto 0) when muxsel = 8 else
|
||||
Regs(15 downto 8) when muxsel = 9 else
|
||||
Regs(23 downto 16) when muxsel = 10 else
|
||||
Regs(31 downto 24) when muxsel = 11 else
|
||||
Regs(39 downto 32) when muxsel = 12 else
|
||||
Regs(47 downto 40) when muxsel = 13 else
|
||||
Regs(55 downto 48) when muxsel = 14 else
|
||||
Regs(63 downto 56) when muxsel = 15 else
|
||||
din_reg when muxsel = 2 else
|
||||
cycleCount(23 downto 16) when muxsel = 3 else
|
||||
cycleCount(7 downto 0) when muxsel = 4 else
|
||||
cycleCount(15 downto 8) when muxsel = 5 else
|
||||
|
||||
fifo_dout(7 downto 0) when muxsel = 6 else
|
||||
fifo_dout(15 downto 8) when muxsel = 7 else
|
||||
fifo_dout(23 downto 16) when muxsel = 8 else
|
||||
fifo_dout(31 downto 24) when muxsel = 9 else
|
||||
fifo_dout(39 downto 32) when muxsel = 10 else
|
||||
fifo_dout(47 downto 40) when muxsel = 11 else
|
||||
fifo_dout(55 downto 48) when muxsel = 12 else
|
||||
fifo_dout(63 downto 56) when muxsel = 13 else
|
||||
fifo_dout(71 downto 64) when muxsel = 14 else
|
||||
|
||||
Regs(7 downto 0) when muxsel = 16 else
|
||||
Regs(15 downto 8) when muxsel = 17 else
|
||||
Regs(23 downto 16) when muxsel = 18 else
|
||||
Regs(31 downto 24) when muxsel = 19 else
|
||||
Regs(39 downto 32) when muxsel = 20 else
|
||||
Regs(47 downto 40) when muxsel = 21 else
|
||||
Regs(55 downto 48) when muxsel = 22 else
|
||||
Regs(63 downto 56) when muxsel = 23 else
|
||||
"10101010";
|
||||
|
||||
-- Combinatorial set of comparators to decode breakpoint/watch addresses
|
||||
@ -279,12 +303,12 @@ begin
|
||||
variable reg_mode_waw : std_logic;
|
||||
variable bactive : std_logic;
|
||||
variable wactive : std_logic;
|
||||
variable status : std_logic_vector(19 downto 0);
|
||||
variable status : std_logic_vector(3 downto 0);
|
||||
variable trigval : std_logic;
|
||||
begin
|
||||
bactive := '0';
|
||||
wactive := '0';
|
||||
status := "00001010101010101010";
|
||||
status := (others => '0');
|
||||
if (brkpt_enable = '1') then
|
||||
for i in 0 to num_comparators - 1 loop
|
||||
reg_addr := brkpt_reg(i * reg_width + 15 downto i * reg_width);
|
||||
@ -302,30 +326,30 @@ begin
|
||||
if (Sync = '1') then
|
||||
if (reg_mode_bi = '1') then
|
||||
bactive := '1';
|
||||
status := "0001" & Addr;
|
||||
status := "0001";
|
||||
end if;
|
||||
if (reg_mode_wi = '1') then
|
||||
wactive := '1';
|
||||
status := "1001" & Addr;
|
||||
status := "1001";
|
||||
end if;
|
||||
else
|
||||
if (RNW = '1') then
|
||||
if (reg_mode_bar = '1') then
|
||||
bactive := '1';
|
||||
status := "0010" & Addr;
|
||||
status := "0010";
|
||||
end if;
|
||||
if (reg_mode_war = '1') then
|
||||
wactive := '1';
|
||||
status := "1010" & Addr;
|
||||
status := "1010";
|
||||
end if;
|
||||
else
|
||||
if (reg_mode_baw = '1') then
|
||||
bactive := '1';
|
||||
status := "0100" & Addr;
|
||||
status := "0100";
|
||||
end if;
|
||||
if (reg_mode_waw = '1') then
|
||||
wactive := '1';
|
||||
status := "1100" & Addr;
|
||||
status := "1100";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
@ -353,6 +377,13 @@ begin
|
||||
begin
|
||||
if rising_edge(Phi2) then
|
||||
|
||||
-- Cycle counter, wraps every 16s at 1MHz
|
||||
if (nRST = '0') then
|
||||
cycleCount <= (others => '0');
|
||||
elsif (Rdy_int = '1') then
|
||||
cycleCount <= cycleCount + 1;
|
||||
end if;
|
||||
|
||||
-- Command processing
|
||||
cmd_edge1 <= cmd_edge;
|
||||
cmd_edge2 <= cmd_edge1;
|
||||
@ -411,9 +442,9 @@ begin
|
||||
end if;
|
||||
|
||||
if ((single = '0') or (cmd_edge2 = '0' and cmd_edge1 = '1' and cmd = "1000")) then
|
||||
Rdy <= (not brkpt_active);
|
||||
Rdy_int <= (not brkpt_active);
|
||||
else
|
||||
Rdy <= (not Sync);
|
||||
Rdy_int <= (not Sync);
|
||||
end if;
|
||||
|
||||
-- 6502 Reset needs to be open collector
|
||||
@ -426,6 +457,7 @@ begin
|
||||
-- Latch instruction address for the whole cycle
|
||||
if (Sync = '1') then
|
||||
addr_inst <= Addr;
|
||||
cycleCount_inst <= cycleCount;
|
||||
end if;
|
||||
|
||||
-- Breakpoints and Watches written to the FIFO
|
||||
@ -433,6 +465,7 @@ begin
|
||||
bw_status1 <= bw_status;
|
||||
if watch_active = '1' or (brkpt_active = '1' and brkpt_active1 = '0') then
|
||||
fifo_wr <= '1';
|
||||
Addr1 <= Addr;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
@ -441,13 +474,16 @@ begin
|
||||
fallingProcess: process (Phi2)
|
||||
begin
|
||||
if falling_edge(Phi2) then
|
||||
-- Latch the data bus for use in watches
|
||||
Data1 <= Data;
|
||||
-- Latch memory read in response to a read command
|
||||
if (memory_rd = '1') then
|
||||
din_reg <= DataIn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
Rdy <= Rdy_int;
|
||||
RdOut <= memory_rd;
|
||||
WrOut <= memory_wr;
|
||||
AddrOut <= addr_dout_reg(23 downto 8);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user