mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2025-02-01 22:31:12 +00:00
Updated AtomBusMon pinout to match 6502, would allow piggy-backing in principle
Change-Id: Ib2c8b2c3fd55f7fbba9b7aecc3d2289ff3114305
This commit is contained in:
David Banks
parent
2ec8488190
commit
3c7fb3429e
@ -19,9 +19,6 @@
|
|||||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||||
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
|
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
|
||||||
</file>
|
</file>
|
||||||
<file xil_pn:name="src/constraints.ucf" xil_pn:type="FILE_UCF">
|
|
||||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
|
||||||
</file>
|
|
||||||
<file xil_pn:name="src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
|
<file xil_pn:name="src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
|
||||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
|
||||||
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
|
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
|
||||||
@ -241,6 +238,9 @@
|
|||||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
|
||||||
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
|
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
|
||||||
</file>
|
</file>
|
||||||
|
<file xil_pn:name="src/AtomBusMon.ucf" xil_pn:type="FILE_UCF">
|
||||||
|
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||||
|
</file>
|
||||||
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
|
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
|
||||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||||
</file>
|
</file>
|
||||||
|
|||||||
@ -9,6 +9,8 @@
|
|||||||
|
|
||||||
#ifdef EMBEDDED_6502
|
#ifdef EMBEDDED_6502
|
||||||
|
|
||||||
|
unsigned int disMem(unsigned int addr);
|
||||||
|
|
||||||
enum
|
enum
|
||||||
{
|
{
|
||||||
IMP, IMPA, MARK2, BRA, IMM, ZP, ZPX, ZPY, INDX, INDY, IND, MARK3, ABS, ABSX, ABSY, IND16, IND1X
|
IMP, IMPA, MARK2, BRA, IMM, ZP, ZPX, ZPY, INDX, INDY, IND, MARK3, ABS, ABSX, ABSY, IND16, IND1X
|
||||||
@ -553,6 +555,77 @@ int lookupBreakpoint(char *params) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void logCycleCount(int offsetLow, int offsetHigh) {
|
||||||
|
unsigned long count = (((unsigned long) hwRead8(offsetHigh)) << 16) | hwRead16(offsetLow);
|
||||||
|
unsigned long countSecs = count / 1000000;
|
||||||
|
unsigned long countMicros = count % 1000000;
|
||||||
|
log0("%02ld.%06ld: ", countSecs, countMicros);
|
||||||
|
}
|
||||||
|
|
||||||
|
void logMode(unsigned int mode) {
|
||||||
|
int i;
|
||||||
|
int first = 1;
|
||||||
|
for (i = 0; i < UNDEFINED; i++) {
|
||||||
|
if (mode & 1) {
|
||||||
|
if (first) {
|
||||||
|
log0("%s", modeStrings[i]);
|
||||||
|
} else {
|
||||||
|
log0(", %c%s", tolower(*modeStrings[i]), modeStrings[i] + 1);
|
||||||
|
}
|
||||||
|
first = 0;
|
||||||
|
}
|
||||||
|
mode >>= 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void logTrigger(int trigger) {
|
||||||
|
if (trigger >= 0 && trigger < NUM_TRIGGERS) {
|
||||||
|
log0("trigger: %s", triggerStrings[trigger]);
|
||||||
|
} else {
|
||||||
|
log0("trigger: ILLEGAL");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int logDetails() {
|
||||||
|
unsigned int i_addr = hwRead16(OFFSET_BW_IAL);
|
||||||
|
unsigned int b_addr = hwRead16(OFFSET_BW_BAL);
|
||||||
|
unsigned int b_data = hwRead8(OFFSET_BW_BD);
|
||||||
|
unsigned int mode = hwRead8(OFFSET_BW_M);
|
||||||
|
unsigned int watch = mode & 8;
|
||||||
|
|
||||||
|
|
||||||
|
// Convert from 4-bit compressed to 6 bit expanded mode representation
|
||||||
|
if (watch) {
|
||||||
|
mode = (mode & 7) << 3;
|
||||||
|
}
|
||||||
|
// Update the serial console
|
||||||
|
if (mode & W_MASK) {
|
||||||
|
logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
|
||||||
|
}
|
||||||
|
logMode(mode);
|
||||||
|
log0(" hit at %04X", i_addr);
|
||||||
|
if (mode & BW_MEM_MASK) {
|
||||||
|
if (mode & W_MEM_MASK) {
|
||||||
|
log0(" writing");
|
||||||
|
} else {
|
||||||
|
log0(" reading");
|
||||||
|
}
|
||||||
|
log0(" %04X = %02X\n", b_addr, b_data);
|
||||||
|
if (mode & B_MASK) {
|
||||||
|
logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
|
||||||
|
}
|
||||||
|
#ifdef EMBEDDED_6502
|
||||||
|
if (mode & B_MEM_MASK) {
|
||||||
|
// It's only safe to do this for brkpts, as it makes memory accesses
|
||||||
|
disMem(i_addr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
} else {
|
||||||
|
log0("\n");
|
||||||
|
}
|
||||||
|
return watch;
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef EMBEDDED_6502
|
#ifdef EMBEDDED_6502
|
||||||
void loadData(unsigned int data) {
|
void loadData(unsigned int data) {
|
||||||
int i;
|
int i;
|
||||||
@ -671,77 +744,8 @@ unsigned int disassemble(unsigned int addr)
|
|||||||
unsigned int disMem(unsigned int addr) {
|
unsigned int disMem(unsigned int addr) {
|
||||||
loadAddr(addr);
|
loadAddr(addr);
|
||||||
return disassemble(addr);
|
return disassemble(addr);
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void logMode(unsigned int mode) {
|
|
||||||
int i;
|
|
||||||
int first = 1;
|
|
||||||
for (i = 0; i < UNDEFINED; i++) {
|
|
||||||
if (mode & 1) {
|
|
||||||
if (first) {
|
|
||||||
log0("%s", modeStrings[i]);
|
|
||||||
} else {
|
|
||||||
log0(", %c%s", tolower(*modeStrings[i]), modeStrings[i] + 1);
|
|
||||||
}
|
|
||||||
first = 0;
|
|
||||||
}
|
|
||||||
mode >>= 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void logTrigger(int trigger) {
|
|
||||||
if (trigger >= 0 && trigger < NUM_TRIGGERS) {
|
|
||||||
log0("trigger: %s", triggerStrings[trigger]);
|
|
||||||
} else {
|
|
||||||
log0("trigger: ILLEGAL");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void logCycleCount(int offsetLow, int offsetHigh) {
|
|
||||||
unsigned long count = (((unsigned long) hwRead8(offsetHigh)) << 16) | hwRead16(offsetLow);
|
|
||||||
unsigned long countSecs = count / 1000000;
|
|
||||||
unsigned long countMicros = count % 1000000;
|
|
||||||
log0("%02ld.%06ld: ", countSecs, countMicros);
|
|
||||||
}
|
|
||||||
|
|
||||||
int logDetails() {
|
|
||||||
unsigned int i_addr = hwRead16(OFFSET_BW_IAL);
|
|
||||||
unsigned int b_addr = hwRead16(OFFSET_BW_BAL);
|
|
||||||
unsigned int b_data = hwRead8(OFFSET_BW_BD);
|
|
||||||
unsigned int mode = hwRead8(OFFSET_BW_M);
|
|
||||||
unsigned int watch = mode & 8;
|
|
||||||
|
|
||||||
|
|
||||||
// Convert from 4-bit compressed to 6 bit expanded mode representation
|
|
||||||
if (watch) {
|
|
||||||
mode = (mode & 7) << 3;
|
|
||||||
}
|
|
||||||
// Update the serial console
|
|
||||||
if (mode & W_MASK) {
|
|
||||||
logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
|
|
||||||
}
|
|
||||||
logMode(mode);
|
|
||||||
log0(" hit at %04X", i_addr);
|
|
||||||
if (mode & BW_MEM_MASK) {
|
|
||||||
if (mode & W_MEM_MASK) {
|
|
||||||
log0(" writing");
|
|
||||||
} else {
|
|
||||||
log0(" reading");
|
|
||||||
}
|
|
||||||
log0(" %04X = %02X\n", b_addr, b_data);
|
|
||||||
if (mode & B_MASK) {
|
|
||||||
logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
|
|
||||||
}
|
|
||||||
if (mode & B_MEM_MASK) {
|
|
||||||
// It's only safe to do this for brkpts, as it makes memory accesses
|
|
||||||
disMem(i_addr);
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
log0("\n");
|
|
||||||
}
|
|
||||||
return watch;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void logAddr() {
|
void logAddr() {
|
||||||
|
|||||||
@ -23,7 +23,7 @@ F_CPU=15855484
|
|||||||
CC=avr-gcc
|
CC=avr-gcc
|
||||||
OBJCOPY=avr-objcopy
|
OBJCOPY=avr-objcopy
|
||||||
|
|
||||||
CFLAGS=-DLCD=1 -DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
|
CFLAGS=-DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
|
||||||
|
|
||||||
OBJECTS=AtomBusMon.o hd44780.o status.o
|
OBJECTS=AtomBusMon.o hd44780.o status.o
|
||||||
|
|
||||||
|
|||||||
76
src/AtomBusMon.ucf
Normal file
76
src/AtomBusMon.ucf
Normal file
@ -0,0 +1,76 @@
|
|||||||
|
|
||||||
|
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
||||||
|
|
||||||
|
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
|
||||||
|
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
|
||||||
|
#NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
|
||||||
|
#NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 4
|
||||||
|
#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
|
||||||
|
#NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 6
|
||||||
|
NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
|
||||||
|
#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
|
||||||
|
NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
|
||||||
|
NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
|
||||||
|
NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
|
||||||
|
NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
|
||||||
|
NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
|
||||||
|
NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
|
||||||
|
NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
|
||||||
|
NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
|
||||||
|
NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
|
||||||
|
NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
|
||||||
|
NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
|
||||||
|
NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
|
||||||
|
|
||||||
|
#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
|
||||||
|
NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
|
||||||
|
NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
|
||||||
|
NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
|
||||||
|
NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
|
||||||
|
#NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
|
||||||
|
#NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
|
||||||
|
#NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
|
||||||
|
#NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
|
||||||
|
#NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
|
||||||
|
#NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
|
||||||
|
#NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
|
||||||
|
#NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
|
||||||
|
NET "RNW" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
|
||||||
|
#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
|
||||||
|
#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
|
||||||
|
#NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 | PERIOD = 500.0 ; # 6502 pin 37
|
||||||
|
#NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
|
||||||
|
NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
|
||||||
|
NET "nRST" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
|
||||||
|
|
||||||
|
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
|
||||||
|
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
|
||||||
|
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
|
||||||
|
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
|
||||||
|
NET "nsw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
|
||||||
|
|
||||||
|
# I/O's for test connector
|
||||||
|
#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||||
|
#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||||
|
NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||||
|
NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||||
|
NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||||
|
#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||||
|
#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||||
|
|
||||||
|
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
|
||||||
|
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
|
||||||
|
|
||||||
|
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
|
||||||
|
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
|
||||||
|
|
||||||
|
# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
|
||||||
|
# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
|
||||||
|
# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
|
||||||
|
# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
|
||||||
|
# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
|
||||||
|
# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
|
||||||
|
# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -36,10 +36,10 @@ entity AtomBusMon is
|
|||||||
trig : in std_logic_vector(1 downto 0);
|
trig : in std_logic_vector(1 downto 0);
|
||||||
|
|
||||||
-- HD44780 LCD
|
-- HD44780 LCD
|
||||||
lcd_rs : out std_logic;
|
--lcd_rs : out std_logic;
|
||||||
lcd_rw : out std_logic;
|
--lcd_rw : out std_logic;
|
||||||
lcd_e : out std_logic;
|
--lcd_e : out std_logic;
|
||||||
lcd_db : inout std_logic_vector(7 downto 4);
|
--lcd_db : inout std_logic_vector(7 downto 4);
|
||||||
|
|
||||||
-- AVR Serial Port
|
-- AVR Serial Port
|
||||||
avr_RxD : in std_logic;
|
avr_RxD : in std_logic;
|
||||||
@ -68,16 +68,23 @@ begin
|
|||||||
mon : entity work.BusMonCore port map (
|
mon : entity work.BusMonCore port map (
|
||||||
clock49 => clock49,
|
clock49 => clock49,
|
||||||
Addr => Addr,
|
Addr => Addr,
|
||||||
|
Data => (others => '0'),
|
||||||
Phi2 => Phi2,
|
Phi2 => Phi2,
|
||||||
RNW => RNW,
|
RNW => RNW,
|
||||||
Sync => Sync,
|
Sync => Sync,
|
||||||
Rdy => Rdy,
|
Rdy => Rdy,
|
||||||
nRST => nRST,
|
nRST => nRST,
|
||||||
|
Regs => (others => '0'),
|
||||||
|
RdOut => open,
|
||||||
|
WrOut => open,
|
||||||
|
AddrOut => open,
|
||||||
|
DataOut => open,
|
||||||
|
DataIn => (others => '0'),
|
||||||
trig => trig,
|
trig => trig,
|
||||||
lcd_rs => lcd_rs,
|
lcd_rs => open,
|
||||||
lcd_rw => lcd_rw,
|
lcd_rw => open,
|
||||||
lcd_e => lcd_e,
|
lcd_e => open,
|
||||||
lcd_db => lcd_db,
|
lcd_db => open,
|
||||||
avr_RxD => avr_RxD,
|
avr_RxD => avr_RxD,
|
||||||
avr_TxD => avr_TxD,
|
avr_TxD => avr_TxD,
|
||||||
sw1 => sw1,
|
sw1 => sw1,
|
||||||
@ -87,8 +94,7 @@ begin
|
|||||||
led8 => led8,
|
led8 => led8,
|
||||||
tmosi => tmosi,
|
tmosi => tmosi,
|
||||||
tdin => tdin,
|
tdin => tdin,
|
||||||
tcclk => tcclk,
|
tcclk => tcclk
|
||||||
Regs => (others => '0')
|
|
||||||
);
|
);
|
||||||
|
|
||||||
end behavioral;
|
end behavioral;
|
||||||
|
|||||||
@ -1,75 +0,0 @@
|
|||||||
|
|
||||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
|
||||||
|
|
||||||
NET "lcd_rs" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6847 pin 2
|
|
||||||
NET "lcd_rw" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6847 pin 3
|
|
||||||
NET "lcd_e" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6847 pin 4
|
|
||||||
NET "lcd_db<4>" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6847 pin 5
|
|
||||||
NET "lcd_db<5>" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6847 pin 6
|
|
||||||
NET "lcd_db<6>" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6847 pin 7
|
|
||||||
NET "lcd_db<7>" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6847 pin 8
|
|
||||||
NET "avr_RxD" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6847 pin 9
|
|
||||||
NET "avr_TxD" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6847 pin 10
|
|
||||||
|
|
||||||
NET "trig<0>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6847 pin 18
|
|
||||||
NET "trig<1>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6847 pin 19
|
|
||||||
NET "nRST" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6847 pin 20
|
|
||||||
NET "Addr<0>" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6847 pin 21
|
|
||||||
NET "Addr<1>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6847 pin 22
|
|
||||||
NET "Addr<2>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6847 pin 23
|
|
||||||
NET "Addr<3>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6847 pin 24
|
|
||||||
NET "Addr<4>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6847 pin 25
|
|
||||||
NET "Addr<5>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6847 pin 26
|
|
||||||
NET "Addr<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6847 pin 27
|
|
||||||
NET "Addr<7>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6847 pin 28
|
|
||||||
NET "Addr<8>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6847 pin 29
|
|
||||||
NET "Addr<9>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6847 pin 30
|
|
||||||
NET "Addr<10>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6847 pin 31
|
|
||||||
NET "Addr<11>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6847 pin 32
|
|
||||||
NET "Addr<12>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6847 pin 33
|
|
||||||
NET "Addr<13>" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6847 pin 34
|
|
||||||
NET "Addr<14>" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6847 pin 35
|
|
||||||
NET "Addr<15>" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6847 pin 36
|
|
||||||
|
|
||||||
NET "Phi2" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6847 pin 37
|
|
||||||
NET "RNW" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6847 pin 38
|
|
||||||
NET "Sync" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6847 pin 39
|
|
||||||
NET "Rdy" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6847 pin 40
|
|
||||||
|
|
||||||
|
|
||||||
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
|
|
||||||
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
|
|
||||||
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
|
|
||||||
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
|
|
||||||
NET "nsw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
|
|
||||||
|
|
||||||
|
|
||||||
# I/O's for test connector
|
|
||||||
#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
|
||||||
#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
|
||||||
NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
|
||||||
NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
|
||||||
NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
|
||||||
#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
|
||||||
#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
# NET "" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6847 pin 11
|
|
||||||
# NET "" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6847 pin 12
|
|
||||||
# NET "" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6847 pin 13
|
|
||||||
# NET "" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6847 pin 14
|
|
||||||
# NET "" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6847 pin 15
|
|
||||||
# NET "" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6847 pin 16
|
|
||||||
|
|
||||||
|
|
||||||
# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
|
|
||||||
# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
|
|
||||||
# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
|
|
||||||
# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
|
|
||||||
# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
|
|
||||||
# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
|
|
||||||
# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Loading…
x
Reference in New Issue
Block a user