mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-09-11 20:54:53 +00:00
Replace special command with x interrupt control commands
Change-Id: I991171d6923cdc928dd9dbb9823c43aee71661be
This commit is contained in:
David Banks
parent
1244eaf607
commit
3e7bda697c
@ -16,14 +16,33 @@
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#define VERSION "0.996"
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// The X commands allows the various interrupt inputs to be overridded
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// They are named after the data sheet pin name
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#if defined(CPU_Z80)
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#define NAME "ICE-Z80"
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#define XCMD0 "xbusrq"
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#define XCMD1 "xint"
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#define XCMD2 "xnmi"
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#define XCMD3 "xres"
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#elif defined(CPU_6502)
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#define NAME "ICE-6502"
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#define XCMD0 "xirq"
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#define XCMD1 "xnmi"
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#define XCMD2 "xres"
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#define XCMD3 "xso "
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#elif defined(CPU_65C02)
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#define NAME "ICE-65C02"
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#define XCMD0 "xirq"
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#define XCMD1 "xnmi"
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#define XCMD2 "xres"
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#define XCMD3 "xso "
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#elif defined(CPU_6809)
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#define NAME "ICE-6809"
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#define XCMD0 "xfiq"
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#define XCMD1 "xirq"
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#define XCMD2 "xnmi"
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#define XCMD3 "xres"
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#else
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#error "Unsupported CPU type"
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#endif
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@ -70,7 +89,6 @@ char *cmdStrings[] = {
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"load",
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"save",
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"srec",
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"special",
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"reset",
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"trace",
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"blist",
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@ -89,7 +107,11 @@ char *cmdStrings[] = {
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"clear",
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"trigger",
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"timermode",
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"timeout"
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"timeout",
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XCMD0,
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XCMD1,
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XCMD2,
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XCMD3
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};
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// Must be kept in step with cmdStrings (just above)
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@ -125,7 +147,6 @@ void (*cmdFuncs[])(char *params) = {
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doCmdLoad,
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doCmdSave,
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doCmdSRec,
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doCmdSpecial,
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doCmdReset,
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doCmdTrace,
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doCmdList,
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@ -144,7 +165,11 @@ void (*cmdFuncs[])(char *params) = {
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doCmdClear,
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doCmdTrigger,
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doCmdTimerMode,
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doCmdTimeout
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doCmdTimeout,
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doCmdXCmd0,
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doCmdXCmd1,
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doCmdXCmd2,
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doCmdXCmd3
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};
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#if defined(EXTENDED_HELP)
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@ -167,6 +192,7 @@ static const char ARGS14[] PROGMEM = "[ <value> ]";
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static const char ARGS15[] PROGMEM = "[ <command> ]";
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static const char ARGS16[] PROGMEM = "<op1> [ <op2> [ <op3> ] ]";
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static const char ARGS17[] PROGMEM = "[ <source> [ <prescale> [ <reset address> ] ] ]";
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static const char ARGS18[] PROGMEM = "e|c|d|f";
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static const char * const argsStrings[] PROGMEM = {
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ARGS00,
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@ -187,6 +213,7 @@ static const char * const argsStrings[] PROGMEM = {
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ARGS15,
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ARGS16,
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ARGS17,
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ARGS18
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};
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// Must be kept in step with cmdStrings (just above)
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@ -197,7 +224,7 @@ static const uint8_t helpMeta[] PROGMEM = {
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17, 15, // help
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9, 8, // continue
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24, 1, // next
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32, 6, // step
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31, 6, // step
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27, 7, // regs
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12, 10, // dis
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16, 7, // flush
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@ -207,7 +234,7 @@ static const uint8_t helpMeta[] PROGMEM = {
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8, 13, // compare
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22, 1, // mem
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26, 2, // rd
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43, 3, // wr
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42, 3, // wr
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#if defined(CPU_Z80)
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20, 1, // io
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19, 2, // in
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@ -218,30 +245,33 @@ static const uint8_t helpMeta[] PROGMEM = {
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15, 16, // exec
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23, 14, // mode
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#endif
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33, 12, // test
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32, 12, // test
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21, 0, // load
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29, 9, // save
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31, 7, // srec
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30, 14, // special
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30, 7, // srec
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28, 7, // reset
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36, 6, // trace
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35, 6, // trace
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1, 7, // blist
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6, 4, // breakx
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42, 4, // watchx
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41, 4, // watchx
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4, 4, // breakr
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40, 4, // watchr
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39, 4, // watchr
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5, 4, // breakw
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41, 4, // watchw
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40, 4, // watchw
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#if defined(CPU_Z80)
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2, 4, // breaki
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38, 4, // watchi
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37, 4, // watchi
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3, 4, // breako
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39, 4, // watcho
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38, 4, // watcho
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#endif
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7, 0, // clear
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37, 5, // trigger
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35, 17, // timermode
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34, 14, // timeout
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36, 5, // trigger
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34, 17, // timermode
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33, 14, // timeout
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43, 18, // xcmd0
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44, 18, // xcmd1
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45, 18, // xcmd2
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46, 18, // xcmd3
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0, 0
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};
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@ -286,8 +316,8 @@ static const uint8_t helpMeta[] PROGMEM = {
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// 011xx1 Unused
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// 011x1x Unused
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// 0111xx Unused
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// 100xxx Special
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// 1010xx Timer Mode
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// 10xxxx Int Ctrl
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// 1100xx Timer Mode
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// 00 - count cpu cycles where clken = 1 and CountCycle = 1
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// 01 - count cpu cycles where clken = 1 (ignoring CountCycle)
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// 10 - free running timer, using busmon_clk as the source
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@ -310,8 +340,8 @@ static const uint8_t helpMeta[] PROGMEM = {
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#define CMD_WR_IO 0x16
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#define CMD_WR_IO_INC 0x17
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#define CMD_EXEC_GO 0x18
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#define CMD_SPECIAL 0x20
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#define CMD_TIMER_MODE 0x28
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#define CMD_INT_CTRL 0x20
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#define CMD_TIMER_MODE 0x30
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/********************************************************
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* AVR Status Register Definitions
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@ -609,6 +639,24 @@ static const char * triggerStrings[NUM_TRIGGERS] = {
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#define TRIGGER_UNDEFINED 31
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/********************************************************
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* Interrupt controls
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********************************************************/
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static const uint8_t cmd_map[] = { 1, 3, 0, 2 };
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static const char INTCTRL0[] PROGMEM = "Enabled";
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static const char INTCTRL1[] PROGMEM = "Conditional";
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static const char INTCTRL2[] PROGMEM = "Forced";
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static const char INTCTRL3[] PROGMEM = "Disabled";
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static const char *int_ctrl_strings[] = {
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INTCTRL0,
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INTCTRL1,
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INTCTRL2,
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INTCTRL3
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};
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/********************************************************
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* Other global variables
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********************************************************/
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@ -637,15 +685,16 @@ uint8_t cmd_id = 0xff;
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#define MASK_CLOCK_ERROR 1
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#define MASK_TIMEOUT_ERROR 2
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// Current special setting
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uint8_t special = 0x00;
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// Current timer mode setting
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uint8_t timer_mode = 0x00;
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uint8_t timer_prescale = 0x01;
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addr_t timer_resetaddr = 0xffff;
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unsigned long timer_offset = 0;
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// Current interrupts controls
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uint8_t int_ctrl = 0;
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/********************************************************
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* User Command Processor
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********************************************************/
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@ -2032,31 +2081,50 @@ void doCmdSRec(char *params) {
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}
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}
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void logSpecial(char *function, uint8_t value) {
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logs(function);
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if (value) {
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logstr(" inhibited\n");
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} else {
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logstr(" enabled\n");
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}
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void set_int_ctrl(uint8_t offset, char *params) {
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// (C) 01 Conditional
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// (D) 11 Disabled
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// (E) 00 Enabled
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// (F) 10 Forced
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while (*params == ' ') {
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params++;
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}
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if (!*params) {
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uint8_t tmp = int_ctrl;
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for (int i = 0; i < 4; i++) {
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logs(cmdStrings[NUM_CMDS - 4 + i]);
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logstr(" = ");
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logpgmstr(int_ctrl_strings[tmp & 3]);
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logc('\n');
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tmp >>= 2;
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}
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} else {
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*params &= 0xdf;
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if (*params >= 'C' && *params <= 'F') {
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uint8_t val = cmd_map[*params - 'C'];
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hwCmd(CMD_INT_CTRL, (offset << 1) | val);
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int_ctrl &= (0x03 << offset) ^ 0xFF;
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int_ctrl |= (val << offset);
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} else {
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logstr("Illegal option\n");
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}
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}
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}
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void doCmdSpecial(char *params) {
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uint8_t tmp = 0xff;
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parsehex2(params, &tmp);
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#if defined(CPU_6809)
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if (tmp <= 7) {
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#else
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if (tmp <= 3) {
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#endif
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special = tmp;
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hwCmd(CMD_SPECIAL, special);
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}
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#if defined(CPU_6809)
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logSpecial("FIRQ", special & 4);
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#endif
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logSpecial("NMI", special & 2);
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logSpecial("IRQ", special & 1);
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void doCmdXCmd0(char *params) {
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set_int_ctrl(0, params);
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}
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void doCmdXCmd1(char *params) {
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set_int_ctrl(2, params);
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}
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void doCmdXCmd2(char *params) {
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set_int_ctrl(4, params);
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}
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void doCmdXCmd3(char *params) {
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set_int_ctrl(6, params);
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}
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void doCmdTimerMode(char *params) {
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@ -76,7 +76,6 @@ void doCmdStep(char *params);
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void doCmdTest(char *params);
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void doCmdSave(char *params);
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void doCmdSRec(char *params);
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void doCmdSpecial(char *params);
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void doCmdTimerMode(char *params);
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void doCmdTimeout(char *params);
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void doCmdTrace(char *params);
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@ -88,5 +87,9 @@ void doCmdWatchWrIO(char *params);
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void doCmdWatchWrMem(char *params);
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void doCmdWriteIO(char *params);
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void doCmdWriteMem(char *params);
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void doCmdXCmd0(char *params);
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void doCmdXCmd1(char *params);
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void doCmdXCmd2(char *params);
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void doCmdXCmd3(char *params);
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#endif
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@ -71,8 +71,8 @@ entity BusMonCore is
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DataIn : in std_logic_vector(7 downto 0);
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Done : in std_logic;
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-- Special outputs (function is CPU specific)
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Special : out std_logic_vector(2 downto 0);
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-- External Interrupt Control
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int_ctrl : out std_logic_vector(7 downto 0) := x"00";
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-- Single Step interface
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SS_Single : out std_logic;
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@ -459,8 +459,8 @@ begin
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-- 0111xx Unused
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-- 011x1x Unused
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-- 011xx1 Unused
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-- 100xxx Special
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-- 1010xx Timer Mode
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-- 10xxxx Int Ctrl
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-- 1100xx Timer Mode
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-- 00 - count cpu cycles where clken = 1 and CountCycle = 1
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-- 01 - count cpu cycles where clken = 1 (ignoring CountCycle)
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-- 10 - free running timer, using busmon_clk as the source
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@ -551,11 +551,11 @@ begin
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exec <= '1';
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end if;
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if (cmd(5 downto 3) = "100") then
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Special <= cmd(2 downto 0);
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if (cmd(5 downto 4) = "10") then
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int_ctrl(to_integer(unsigned(cmd(3 downto 2))) * 2 + 1 downto to_integer(unsigned(cmd(3 downto 2))) * 2) <= cmd(1 downto 0);
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end if;
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if (cmd(5 downto 2) = "1010") then
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if (cmd(5 downto 2) = "1100") then
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timer_mode <= cmd(1 downto 0);
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end if;
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@ -124,7 +124,7 @@ architecture behavioral of MC6809CpuMon is
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signal SS_Single : std_logic;
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signal SS_Step : std_logic;
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signal CountCycle : std_logic;
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signal special : std_logic_vector(2 downto 0);
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signal int_ctrl : std_logic_vector(7 downto 0);
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signal LIC_int : std_logic;
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@ -140,9 +140,10 @@ architecture behavioral of MC6809CpuMon is
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signal data_wr : std_logic;
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signal nRSTout : std_logic;
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signal NMI_n_masked : std_logic;
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signal IRQ_n_masked : std_logic;
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signal FIRQ_n_masked : std_logic;
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signal IRQ_n_masked : std_logic;
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signal NMI_n_masked : std_logic;
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signal RES_n_masked : std_logic;
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begin
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@ -184,7 +185,7 @@ begin
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WrIO_n => '1',
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Sync => Sync_int,
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Rdy => open,
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nRSTin => RES_n,
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nRSTin => RES_n_masked,
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nRSTout => cpu_reset_n,
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CountCycle => CountCycle,
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trig => trig,
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@ -207,14 +208,28 @@ begin
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DataOut => memory_dout,
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DataIn => memory_din,
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Done => memory_done,
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Special => special,
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int_ctrl => int_ctrl,
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SS_Step => SS_Step,
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SS_Single => SS_Single
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);
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FIRQ_n_masked <= FIRQ_n or special(2);
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NMI_n_masked <= NMI_n or special(1);
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IRQ_n_masked <= IRQ_n or special(0);
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-- The two int control bits work as follows
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-- 00 -> IRQ_n (enabled)
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-- 01 -> IRQ_n or SS_Single (enabled when free-running)
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-- 10 -> 0 (forced)
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-- 11 -> 1 (disabled)
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FIRQ_n_masked <= int_ctrl(0) when int_ctrl(1) = '1' else
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FIRQ_n or (int_ctrl(0) and SS_single);
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IRQ_n_masked <= int_ctrl(2) when int_ctrl(3) = '1' else
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IRQ_n or (int_ctrl(2) and SS_single);
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NMI_n_masked <= int_ctrl(4) when int_ctrl(5) = '1' else
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NMI_n or (int_ctrl(4) and SS_single);
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RES_n_masked <= int_ctrl(6) when int_ctrl(7) = '1' else
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RES_n or (int_ctrl(6) and SS_single);
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-- The CPU is slightly pipelined and the register update of the last
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-- instruction overlaps with the opcode fetch of the next instruction.
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@ -100,7 +100,7 @@ architecture behavioral of MOS6502CpuMonCore is
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signal SS_Step : std_logic;
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signal SS_Step_held : std_logic;
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signal CountCycle : std_logic;
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signal special : std_logic_vector(2 downto 0);
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signal int_ctrl : std_logic_vector(7 downto 0);
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signal memory_rd : std_logic;
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signal memory_rd1 : std_logic;
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@ -111,8 +111,11 @@ architecture behavioral of MOS6502CpuMonCore is
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signal memory_din : std_logic_vector(7 downto 0);
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signal memory_done : std_logic;
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signal NMI_n_masked : std_logic;
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signal IRQ_n_masked : std_logic;
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signal NMI_n_masked : std_logic;
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signal Res_n_masked : std_logic;
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signal SO_n_masked : std_logic;
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signal exec : std_logic;
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signal exec_held : std_logic;
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@ -139,7 +142,7 @@ begin
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WrIO_n => '1',
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Sync => Sync_mon,
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Rdy => open,
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nRSTin => Res_n,
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nRSTin => Res_n_masked,
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nRSTout => cpu_reset_n,
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CountCycle => CountCycle,
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trig => trig,
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@ -163,7 +166,7 @@ begin
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DataOut => memory_dout,
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DataIn => memory_din,
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Done => Done_mon,
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Special => special,
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int_ctrl => int_ctrl,
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SS_Step => SS_Step,
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SS_Single => SS_Single
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);
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@ -173,8 +176,24 @@ begin
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Done_mon <= Rdy and memory_done;
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Data <= Din when R_W_n_int = '1' else Dout_int;
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NMI_n_masked <= NMI_n or special(1);
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IRQ_n_masked <= IRQ_n or special(0);
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-- The two int control bits work as follows
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-- 00 -> IRQ_n (enabled)
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-- 01 -> IRQ_n or SS_Single (enabled when free-running)
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-- 10 -> 0 (forced)
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-- 11 -> 1 (disabled)
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IRQ_n_masked <= int_ctrl(0) when int_ctrl(1) = '1' else
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IRQ_n or (int_ctrl(0) and SS_single);
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NMI_n_masked <= int_ctrl(2) when int_ctrl(3) = '1' else
|
||||
NMI_n or (int_ctrl(2) and SS_single);
|
||||
|
||||
Res_n_masked <= int_ctrl(4) when int_ctrl(5) = '1' else
|
||||
Res_n or (int_ctrl(4) and SS_single);
|
||||
|
||||
SO_n_masked <= int_ctrl(6) when int_ctrl(7) = '1' else
|
||||
SO_n or (int_ctrl(6) and SS_single);
|
||||
|
||||
-- The CPU is slightly pipelined and the register update of the last
|
||||
-- instruction overlaps with the opcode fetch of the next instruction.
|
||||
@ -209,7 +228,7 @@ begin
|
||||
inst_t65: entity work.T65 port map (
|
||||
mode => "00",
|
||||
Abort_n => '1',
|
||||
SO_n => SO_n,
|
||||
SO_n => SO_n_masked,
|
||||
Res_n => cpu_reset_n,
|
||||
Enable => cpu_clken_ss,
|
||||
Clk => cpu_clk,
|
||||
|
||||
@ -116,7 +116,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
|
||||
signal SS_Step : std_logic;
|
||||
signal SS_Step_held : std_logic;
|
||||
signal CountCycle : std_logic;
|
||||
signal special : std_logic_vector(2 downto 0);
|
||||
signal int_ctrl : std_logic_vector(7 downto 0);
|
||||
signal skipNextOpcode : std_logic;
|
||||
|
||||
signal Regs : std_logic_vector(255 downto 0);
|
||||
@ -150,6 +150,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
|
||||
signal BUSRQ_n_sync : std_logic;
|
||||
signal INT_n_sync : std_logic;
|
||||
signal NMI_n_sync : std_logic;
|
||||
signal RESET_n_sync : std_logic;
|
||||
|
||||
signal Read_n : std_logic;
|
||||
signal Read_n0 : std_logic;
|
||||
@ -218,7 +219,7 @@ begin
|
||||
WrIO_n => WriteIO_n,
|
||||
Sync => Sync,
|
||||
Rdy => open,
|
||||
nRSTin => RESET_n,
|
||||
nRSTin => RESET_n_sync,
|
||||
nRSTout => cpu_reset_n,
|
||||
CountCycle => CountCycle,
|
||||
trig => trig,
|
||||
@ -242,7 +243,7 @@ begin
|
||||
DataOut => memory_dout,
|
||||
DataIn => memory_din,
|
||||
Done => memory_done,
|
||||
Special => special,
|
||||
int_ctrl => int_ctrl,
|
||||
SS_Single => SS_Single,
|
||||
SS_Step => SS_Step
|
||||
);
|
||||
@ -283,9 +284,31 @@ begin
|
||||
int_gen : process(CLK_n)
|
||||
begin
|
||||
if rising_edge(CLK_n) then
|
||||
BUSRQ_n_sync <= BUSRQ_n;
|
||||
NMI_n_sync <= NMI_n or special(1);
|
||||
INT_n_sync <= INT_n or special(0);
|
||||
|
||||
if int_ctrl(1) = '1' then
|
||||
BUSRQ_n_sync <= int_ctrl(0);
|
||||
else
|
||||
BUSRQ_n_sync <= BUSRQ_n or (int_ctrl(0) and SS_single);
|
||||
end if;
|
||||
|
||||
if int_ctrl(3) = '1' then
|
||||
INT_n_sync <= int_ctrl(2);
|
||||
else
|
||||
INT_n_sync <= INT_n or (int_ctrl(2) and SS_single);
|
||||
end if;
|
||||
|
||||
if int_ctrl(5) = '1' then
|
||||
NMI_n_sync <= int_ctrl(4);
|
||||
else
|
||||
NMI_n_sync <= NMI_n or (int_ctrl(4) and SS_single);
|
||||
end if;
|
||||
|
||||
if int_ctrl(7) = '1' then
|
||||
RESET_n_sync <= int_ctrl(6);
|
||||
else
|
||||
RESET_n_sync <= RESET_n or (int_ctrl(6) and SS_single);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
@ -401,7 +424,7 @@ begin
|
||||
BUSAK_n <= BUSAK_n_int when state = idle else mon_busak_n;
|
||||
|
||||
-- Force the address and databus to tristate when reset is asserted
|
||||
tristate_ad_n <= '0' when RESET_n = '0' else
|
||||
tristate_ad_n <= '0' when RESET_n_sync = '0' else
|
||||
BUSAK_n_int when state = idle else
|
||||
mon_busak_n1;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user