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Single-stepping functionality complete

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Change-Id: Ic21b05ae8ecb828d32e55fe36be501800cfb3407
This commit is contained in:
David Banks 2015-06-07 11:19:33 +01:00
parent 2ab3ac7bc1
commit 43df61cd06
82 changed files with 17976 additions and 0 deletions
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iseconfig/
working/
nohup.out
AtomBusMon_guide.ncd
AtomBusMon_summary.html
src/AtomBusMon_bd.bmm
*~
#*

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="src/AtomBusMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="src/constraints.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="src/AVR8/Core/avr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="src/AVR8/Core/alu_avr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="src/AVR8/Core/bit_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="src/AVR8/Core/io_adr_dec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="src/AVR8/Core/io_reg_file.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="src/AVR8/Core/pm_fetch_dec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="src/AVR8/Core/reg_file.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/ArbiterAndMux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemRdMux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="src/AVR8/Memory/prog_mem_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XDM4Kx8.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XMemCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerDFF.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerLatch.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="src/AVR8/resync/rsnc_comp_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_mod_comp_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_mod.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="src/AVR8/uC/RAMDataReg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/avr_adr_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/AVRuCPackage.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/std_library.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/SynthCtrlPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="src/AVR8/Core/AVR_Core_CompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XPM8Kx16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="134"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="src/AtomBusMon.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="src/oho_dy1/OhoPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
</files>
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s250e" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomBusMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/AtomBusMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomBusMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="non-default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AtomBusMon" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomBusMon_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomBusMon_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomBusMon_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomBusMon_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomBusMon" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AtomBusMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-05-24T15:45:55" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6944A56AEEC704FF66BE3C0F54DA91A8" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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firmware/AtomBusMon.c Normal file
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#include <stdio.h>
#include <string.h>
#include <avr/pgmspace.h>
#include "hd44780.h"
#include "status.h"
#define CTRL_PORT PORTB
#define CTRL_DDR DDRB
#define SINGLE_MASK 0x02
#define STEP_MASK 0x01
#define CTRL_MASK (SINGLE_MASK | STEP_MASK)
#define AL_PORT PORTD
#define AL_DIN PIND
#define AL_MASK 0x00
#define AL_DDR DDRD
#define AH_PORT PORTE
#define AH_DIN PINE
#define AH_MASK 0x00
#define AH_DDR DDRE
#define VERSION "0.10"
#define NUMCMDS 10
#define MAXBKPTS 4
int numbkpts = 0;
int single;
long trace;
long instructions = 1;
unsigned int breakpoints[MAXBKPTS] = {
0,
0,
0,
0
};
char *cmdStrings[NUMCMDS] = {
"help",
"reset",
"break",
"continue",
"address",
"step",
"trace",
"blist",
"bset",
"bclear"
};
#define Delay_us(__us) \
if((unsigned long) (F_CPU/1000000.0 * __us) != F_CPU/1000000.0 * __us)\
__builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000000.0 * __us)+1);\
else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000000.0 * __us))
#define Delay_ms(__ms) \
if((unsigned long) (F_CPU/1000.0 * __ms) != F_CPU/1000.0 * __ms)\
__builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000.0 * __ms)+1);\
else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000.0 * __ms))
char message[32];
char command[32];
void readCmd(char *cmd) {
char c;
int i = 0;
log0(">> ");
while (1) {
c = Serial_RxByte0();
if (c == 8) {
// Handle backspace/delete
if (i > 0) {
i--;
Serial_TxByte0(c);
Serial_TxByte0(32);
Serial_TxByte0(c);
}
} else if (c == 13) {
// Handle return
if (i == 0) {
while (cmd[i]) {
Serial_TxByte0(cmd[i++]);
}
} else {
cmd[i] = 0;
}
Serial_TxByte0(10);
Serial_TxByte0(13);
return;
} else {
// Handle any other character
Serial_TxByte0(c);
cmd[i] = c;
i++;
}
}
}
void setSingle(int i) {
single = i;
if (single) {
CTRL_PORT |= SINGLE_MASK;
log0("Single stepping enabled\n");
} else {
CTRL_PORT &= ~SINGLE_MASK;
log0("Single stepping disabled\n");
}
}
void setTrace(long i) {
trace = i;
if (trace) {
log0("Tracing every %ld instructions\n", trace);
} else {
log0("Tracing disabled\n");
}
}
/*******************************************
* Commands
*******************************************/
void notImplemented() {
log0("Not implemented\n");
}
void doCmdHelp(char *params) {
int i;
log0("Atom Bus Monitor version %s\n", VERSION);
log0("Commands:\n");
for (i = 0; i < NUMCMDS; i++) {
log0(" %s\n", cmdStrings[i]);
}
}
void doCmdAddr() {
unsigned int addr = AH_DIN << 8 | AL_DIN;
sprintf(message, "%04X", addr);
lcd_goto(6);
lcd_puts(message);
log0("%s\n", message);
}
void doCmdStep(char *params) {
long i;
long j;
if (!single) {
log0("Use the break command to stop the 6502\n");
return;
}
sscanf(params, "%ld", &instructions);
if (instructions <= 0) {
log0("Number of instuctions must be positive\n");
return;
}
log0("Stepping %ld instructions\n", instructions);
j = trace;
for (i = 1; i <= instructions; i++) {
// Step the 6502
CTRL_PORT &= ~STEP_MASK;
Delay_us(1);
CTRL_PORT |= STEP_MASK;
Delay_us(1);
if (i == instructions || (trace && (--j == 0))) {
doCmdAddr();
j = trace;
}
}
}
void doCmdReset(char *params) {
notImplemented();
}
void doCmdBreak(char *params) {
setSingle(true);
doCmdAddr();
}
void doCmdContinue(char *params) {
setSingle(false);
}
void doCmdTrace(char *params) {
long i;
sscanf(params, "%ld", &i);
setTrace(i);
}
void doCmdBList(char *params) {
int i;
if (numbkpts) {
for (i = 0; i < numbkpts; i++) {
log0("%d: %04X\n", i, breakpoints[i]);
}
} else {
log0("No breakpoints set\n");
}
}
void doCmdBSet(char *params) {
int i;
unsigned int addr;
sscanf(params, "%x", &addr);
if (numbkpts == MAXBKPTS) {
log0("All breakpoints are already set\n");
doCmdBList(NULL);
return;
}
numbkpts++;
for (i = numbkpts - 2; i >= -1; i--) {
if (i == -1 || breakpoints[i] < addr) {
log0("Setting breakpoint at %04X\n", addr);
breakpoints[i + 1] = addr;
doCmdBList(NULL);
return;
} else if (breakpoints[i] == addr) {
log0("Breakpoint already set at %04X\n", addr);
doCmdBList(NULL);
return;
} else {
breakpoints[i + 1] = breakpoints[i];
}
}
}
void doCmdBClear(char *params) {
int i;
int n;
sscanf(params, "%d", &n);
if (n >= numbkpts) {
log0("Breakpoint %d not set\n", n);
} else {
log0("Removing breakpoint at %04X\n", breakpoints[n]);
for (i = n; i < numbkpts; i++) {
breakpoints[i] = breakpoints[i + 1];
}
numbkpts--;
}
doCmdBList(NULL);
}
void initialize() {
CTRL_DDR = CTRL_MASK;
AL_DDR = AL_MASK;
AH_DDR = AH_MASK;
CTRL_PORT &= ~STEP_MASK;
Serial_Init(57600,57600);
lcd_init();
lcd_puts("Addr: xxxx");
log0("Atom Bus Monitor\n");
setSingle(false);
setTrace(0);
}
void (*cmdFuncs[NUMCMDS])(char *params) = {
doCmdHelp,
doCmdReset,
doCmdBreak,
doCmdContinue,
doCmdAddr,
doCmdStep,
doCmdTrace,
doCmdBList,
doCmdBSet,
doCmdBClear
};
void dispatchCmd(char *cmd) {
int i;
char *cmdString;
int minLen;
int cmdStringLen;
int cmdLen = 0;
while (cmd[cmdLen] >= 'a' && cmd[cmdLen] <= 'z') {
cmdLen++;
}
for (i = 0; i < NUMCMDS; i++) {
cmdString = cmdStrings[i];
cmdStringLen = strlen(cmdString);
minLen = cmdLen < cmdStringLen ? cmdLen : cmdStringLen;
if (strncmp(cmdString, cmd, minLen) == 0) {
(*cmdFuncs[i])(command + cmdLen);
return;
}
}
log0("Unknown command %s\n", cmd);
}
int main(void) {
initialize();
while (1) {
readCmd(command);
dispatchCmd(command);
}
return 0;
}

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firmware/Makefile Normal file
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# Paths that will need changing
ATOMFPGA=$(HOME)/atom/AtomBusMon
PAPILIO_LOADER=/opt/GadgetFactory/papilio-loader/programmer
XILINX=/opt/Xilinx/14.7
# Shouldn't need to make changes below this point
BIT_FILE=$(ATOMFPGA)/working/AtomBusMon.bit
BMM_FILE=$(ATOMFPGA)/src/AtomBusMon_bd.bmm
# Papilio dev environment
PROG=${PAPILIO_LOADER}/linux32/papilio-prog
BSCAN=${PAPILIO_LOADER}/bscan_spi_xc3s500e.bit
SREC_CAT=srec_cat
GAWK=gawk
DATA2MEM=${XILINX}/ISE_DS/ISE/bin/lin/data2mem
# AVR dev environment
MCU=atmega103
F_CPU=15855484
CC=avr-gcc
OBJCOPY=avr-objcopy
CFLAGS=-DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
OBJECTS=AtomBusMon.o hd44780.o status.o
load: avr.bit
# sudo $(PROG) -v -f avr.bit
# sudo $(PROG) -v -b $(BSCAN) -f avr.bit -sa -r
avr.bit: avr_progmem.mem
$(DATA2MEM) -bm $(BMM_FILE) -bd avr_progmem.mem -bt $(BIT_FILE) -o b avr.bit
avr_progmem.mem: avr_progmem.hex
$(SREC_CAT) $< -Intel -Byte_Swap 2 -Data_Only -o tmp.mem -vmem 8
$(GAWK) ' BEGIN{FS=" ";} { $$1= ""; print}' tmp.mem > $@
rm tmp.mem
avr_progmem.hex : avr_progmem.out
$(OBJCOPY) -R .eeprom -O ihex avr_progmem.out avr_progmem.hex
avr_progmem.out : $(OBJECTS)
$(CC) $(CFLAGS) -o avr_progmem.out -Wl,-Map,avr_progmem.map $^
%.o : %.c
$(CC) $(CFLAGS) -Os -c $<
%.o : %.S
$(CC) $(CFLAGS) -Os -c $<
.phony: clean
clean:
rm -f avr.bit avr_progmem.mem avr_progmem.hex avr_progmem.out avr_progmem.map *.o

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/*****************************************************************************
Title : HD44780 Library
Author : SA Development
Version: 1.11
*****************************************************************************/
#include "avr/pgmspace.h"
#include "hd44780.h"
#include "avr/sfr_defs.h"
#if (USE_ADELAY_LIBRARY==1)
#include "adelay.h"
#else
#define Delay_ns(__ns) \
if((unsigned long) (F_CPU/1000000000.0 * __ns) != F_CPU/1000000000.0 * __ns)\
__builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000000000.0 * __ns)+1);\
else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000000000.0 * __ns))
#define Delay_us(__us) \
if((unsigned long) (F_CPU/1000000.0 * __us) != F_CPU/1000000.0 * __us)\
__builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000000.0 * __us)+1);\
else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000000.0 * __us))
#define Delay_ms(__ms) \
if((unsigned long) (F_CPU/1000.0 * __ms) != F_CPU/1000.0 * __ms)\
__builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000.0 * __ms)+1);\
else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000.0 * __ms))
#define Delay_s(__s) \
if((unsigned long) (F_CPU/1.0 * __s) != F_CPU/1.0 * __s)\
__builtin_avr_delay_cycles((unsigned long) ( F_CPU/1.0 * __s)+1);\
else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1.0 * __s))
#endif
#if !defined(LCD_BITS) || (LCD_BITS!=4 && LCD_BITS!=8)
#error LCD_BITS is not defined or not valid.
#endif
#if !defined(WAIT_MODE) || (WAIT_MODE!=0 && WAIT_MODE!=1)
#error WAIT_MODE is not defined or not valid.
#endif
#if !defined(RW_LINE_IMPLEMENTED) || (RW_LINE_IMPLEMENTED!=0 && RW_LINE_IMPLEMENTED!=1)
#error RW_LINE_IMPLEMENTED is not defined or not valid.
#endif
#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED!=1)
#error WAIT_MODE=1 requires RW_LINE_IMPLEMENTED=1.
#endif
#if !defined(LCD_DISPLAYS) || (LCD_DISPLAYS<1) || (LCD_DISPLAYS>4)
#error LCD_DISPLAYS is not defined or not valid.
#endif
// Constants/Macros
#define PIN(x) (*(&x - 2)) // Address of Data Direction Register of Port X
#define DDR(x) (*(&x - 1)) // Address of Input Register of Port X
//PORT defines
#define lcd_rs_port_low() LCD_RS_PORT&=~_BV(LCD_RS_PIN)
#if RW_LINE_IMPLEMENTED==1
#define lcd_rw_port_low() LCD_RW_PORT&=~_BV(LCD_RW_PIN)
#endif
#define lcd_db0_port_low() LCD_DB0_PORT&=~_BV(LCD_DB0_PIN)
#define lcd_db1_port_low() LCD_DB1_PORT&=~_BV(LCD_DB1_PIN)
#define lcd_db2_port_low() LCD_DB2_PORT&=~_BV(LCD_DB2_PIN)
#define lcd_db3_port_low() LCD_DB3_PORT&=~_BV(LCD_DB3_PIN)
#define lcd_db4_port_low() LCD_DB4_PORT&=~_BV(LCD_DB4_PIN)
#define lcd_db5_port_low() LCD_DB5_PORT&=~_BV(LCD_DB5_PIN)
#define lcd_db6_port_low() LCD_DB6_PORT&=~_BV(LCD_DB6_PIN)
#define lcd_db7_port_low() LCD_DB7_PORT&=~_BV(LCD_DB7_PIN)
#define lcd_rs_port_high() LCD_RS_PORT|=_BV(LCD_RS_PIN)
#if RW_LINE_IMPLEMENTED==1
#define lcd_rw_port_high() LCD_RW_PORT|=_BV(LCD_RW_PIN)
#endif
#define lcd_db0_port_high() LCD_DB0_PORT|=_BV(LCD_DB0_PIN)
#define lcd_db1_port_high() LCD_DB1_PORT|=_BV(LCD_DB1_PIN)
#define lcd_db2_port_high() LCD_DB2_PORT|=_BV(LCD_DB2_PIN)
#define lcd_db3_port_high() LCD_DB3_PORT|=_BV(LCD_DB3_PIN)
#define lcd_db4_port_high() LCD_DB4_PORT|=_BV(LCD_DB4_PIN)
#define lcd_db5_port_high() LCD_DB5_PORT|=_BV(LCD_DB5_PIN)
#define lcd_db6_port_high() LCD_DB6_PORT|=_BV(LCD_DB6_PIN)
#define lcd_db7_port_high() LCD_DB7_PORT|=_BV(LCD_DB7_PIN)
#define lcd_rs_port_set(value) if (value) lcd_rs_port_high(); else lcd_rs_port_low();
#if RW_LINE_IMPLEMENTED==1
#define lcd_rw_port_set(value) if (value) lcd_rw_port_high(); else lcd_rw_port_low();
#endif
#define lcd_db0_port_set(value) if (value) lcd_db0_port_high(); else lcd_db0_port_low();
#define lcd_db1_port_set(value) if (value) lcd_db1_port_high(); else lcd_db1_port_low();
#define lcd_db2_port_set(value) if (value) lcd_db2_port_high(); else lcd_db2_port_low();
#define lcd_db3_port_set(value) if (value) lcd_db3_port_high(); else lcd_db3_port_low();
#define lcd_db4_port_set(value) if (value) lcd_db4_port_high(); else lcd_db4_port_low();
#define lcd_db5_port_set(value) if (value) lcd_db5_port_high(); else lcd_db5_port_low();
#define lcd_db6_port_set(value) if (value) lcd_db6_port_high(); else lcd_db6_port_low();
#define lcd_db7_port_set(value) if (value) lcd_db7_port_high(); else lcd_db7_port_low();
//PIN defines
#define lcd_db0_pin_get() (((PIN(LCD_DB0_PORT) & _BV(LCD_DB0_PIN))==0)?0:1)
#define lcd_db1_pin_get() (((PIN(LCD_DB1_PORT) & _BV(LCD_DB1_PIN))==0)?0:1)
#define lcd_db2_pin_get() (((PIN(LCD_DB2_PORT) & _BV(LCD_DB2_PIN))==0)?0:1)
#define lcd_db3_pin_get() (((PIN(LCD_DB3_PORT) & _BV(LCD_DB3_PIN))==0)?0:1)
#define lcd_db4_pin_get() (((PIN(LCD_DB4_PORT) & _BV(LCD_DB4_PIN))==0)?0:1)
#define lcd_db5_pin_get() (((PIN(LCD_DB5_PORT) & _BV(LCD_DB5_PIN))==0)?0:1)
#define lcd_db6_pin_get() (((PIN(LCD_DB6_PORT) & _BV(LCD_DB6_PIN))==0)?0:1)
#define lcd_db7_pin_get() (((PIN(LCD_DB7_PORT) & _BV(LCD_DB7_PIN))==0)?0:1)
//DDR defines
#define lcd_rs_ddr_low() DDR(LCD_RS_PORT)&=~_BV(LCD_RS_PIN)
#if RW_LINE_IMPLEMENTED==1
#define lcd_rw_ddr_low() DDR(LCD_RW_PORT)&=~_BV(LCD_RW_PIN)
#endif
#define lcd_db0_ddr_low() DDR(LCD_DB0_PORT)&=~_BV(LCD_DB0_PIN)
#define lcd_db1_ddr_low() DDR(LCD_DB1_PORT)&=~_BV(LCD_DB1_PIN)
#define lcd_db2_ddr_low() DDR(LCD_DB2_PORT)&=~_BV(LCD_DB2_PIN)
#define lcd_db3_ddr_low() DDR(LCD_DB3_PORT)&=~_BV(LCD_DB3_PIN)
#define lcd_db4_ddr_low() DDR(LCD_DB4_PORT)&=~_BV(LCD_DB4_PIN)
#define lcd_db5_ddr_low() DDR(LCD_DB5_PORT)&=~_BV(LCD_DB5_PIN)
#define lcd_db6_ddr_low() DDR(LCD_DB6_PORT)&=~_BV(LCD_DB6_PIN)
#define lcd_db7_ddr_low() DDR(LCD_DB7_PORT)&=~_BV(LCD_DB7_PIN)
#define lcd_rs_ddr_high() DDR(LCD_RS_PORT)|=_BV(LCD_RS_PIN)
#if RW_LINE_IMPLEMENTED==1
#define lcd_rw_ddr_high() DDR(LCD_RW_PORT)|=_BV(LCD_RW_PIN)
#endif
#define lcd_db0_ddr_high() DDR(LCD_DB0_PORT)|=_BV(LCD_DB0_PIN)
#define lcd_db1_ddr_high() DDR(LCD_DB1_PORT)|=_BV(LCD_DB1_PIN)
#define lcd_db2_ddr_high() DDR(LCD_DB2_PORT)|=_BV(LCD_DB2_PIN)
#define lcd_db3_ddr_high() DDR(LCD_DB3_PORT)|=_BV(LCD_DB3_PIN)
#define lcd_db4_ddr_high() DDR(LCD_DB4_PORT)|=_BV(LCD_DB4_PIN)
#define lcd_db5_ddr_high() DDR(LCD_DB5_PORT)|=_BV(LCD_DB5_PIN)
#define lcd_db6_ddr_high() DDR(LCD_DB6_PORT)|=_BV(LCD_DB6_PIN)
#define lcd_db7_ddr_high() DDR(LCD_DB7_PORT)|=_BV(LCD_DB7_PIN)
#define lcd_rs_ddr_set(value) if (value) lcd_rs_ddr_high(); else lcd_rs_ddr_low();
#if RW_LINE_IMPLEMENTED==1
#define lcd_rw_ddr_set(value) if (value) lcd_rw_ddr_high(); else lcd_rw_ddr_low();
#endif
#define lcd_db0_ddr_set(value) if (value) lcd_db0_ddr_high(); else lcd_db0_ddr_low();
#define lcd_db1_ddr_set(value) if (value) lcd_db1_ddr_high(); else lcd_db1_ddr_low();
#define lcd_db2_ddr_set(value) if (value) lcd_db2_ddr_high(); else lcd_db2_ddr_low();
#define lcd_db3_ddr_set(value) if (value) lcd_db3_ddr_high(); else lcd_db3_ddr_low();
#define lcd_db4_ddr_set(value) if (value) lcd_db4_ddr_high(); else lcd_db4_ddr_low();
#define lcd_db5_ddr_set(value) if (value) lcd_db5_ddr_high(); else lcd_db5_ddr_low();
#define lcd_db6_ddr_set(value) if (value) lcd_db6_ddr_high(); else lcd_db6_ddr_low();
#define lcd_db7_ddr_set(value) if (value) lcd_db7_ddr_high(); else lcd_db7_ddr_low();
#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
static unsigned char PrevCmdInvolvedAddressCounter=0;
#endif
#if (LCD_DISPLAYS>1)
static unsigned char ActiveDisplay=1;
#endif
static inline void lcd_e_port_low()
{
#if (LCD_DISPLAYS>1)
switch (ActiveDisplay)
{
case 2 : LCD_E2_PORT&=~_BV(LCD_E2_PIN);
break;
#if (LCD_DISPLAYS>=3)
case 3 : LCD_E3_PORT&=~_BV(LCD_E3_PIN);
break;
#endif
#if (LCD_DISPLAYS==4)
case 4 : LCD_E4_PORT&=~_BV(LCD_E4_PIN);
break;
#endif
default :
#endif
LCD_E_PORT&=~_BV(LCD_E_PIN);
#if (LCD_DISPLAYS>1)
}
#endif
}
static inline void lcd_e_port_high()
{
#if (LCD_DISPLAYS>1)
switch (ActiveDisplay)
{
case 2 : LCD_E2_PORT|=_BV(LCD_E2_PIN);
break;
#if (LCD_DISPLAYS>=3)
case 3 : LCD_E3_PORT|=_BV(LCD_E3_PIN);
break;
#endif
#if (LCD_DISPLAYS==4)
case 4 : LCD_E4_PORT|=_BV(LCD_E4_PIN);
break;
#endif
default :
#endif
LCD_E_PORT|=_BV(LCD_E_PIN);
#if (LCD_DISPLAYS>1)
}
#endif
}
static inline void lcd_e_ddr_low()
{
#if (LCD_DISPLAYS>1)
switch (ActiveDisplay)
{
case 2 : DDR(LCD_E2_PORT)&=~_BV(LCD_E2_PIN);
break;
#if (LCD_DISPLAYS>=3)
case 3 : DDR(LCD_E3_PORT)&=~_BV(LCD_E3_PIN);
break;
#endif
#if (LCD_DISPLAYS==4)
case 4 : DDR(LCD_E4_PORT)&=~_BV(LCD_E4_PIN);
break;
#endif
default :
#endif
DDR(LCD_E_PORT)&=~_BV(LCD_E_PIN);
#if (LCD_DISPLAYS>1)
}
#endif
}
static inline void lcd_e_ddr_high()
{
#if (LCD_DISPLAYS>1)
switch (ActiveDisplay)
{
case 2 : DDR(LCD_E2_PORT)|=_BV(LCD_E2_PIN);
break;
#if (LCD_DISPLAYS>=3)
case 3 : DDR(LCD_E3_PORT)|=_BV(LCD_E3_PIN);
break;
#endif
#if (LCD_DISPLAYS==4)
case 4 : DDR(LCD_E4_PORT)|=_BV(LCD_E4_PIN);
break;
#endif
default :
#endif
DDR(LCD_E_PORT)|=_BV(LCD_E_PIN);
#if (LCD_DISPLAYS>1)
}
#endif
}
/*************************************************************************
loops while lcd is busy, returns address counter
*************************************************************************/
#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
static uint8_t lcd_read(uint8_t rs);
static void lcd_waitbusy(void)
{
register uint8_t c;
unsigned int ul1=0;
while ( ((c=lcd_read(0)) & (1<<LCD_BUSY)) && ul1<((F_CPU/16384>=16)?F_CPU/16384:16)) // Wait Until Busy Flag is Cleared
ul1++;
}
#endif
/*************************************************************************
Low-level function to read byte from LCD controller
Input: rs 1: read data
0: read busy flag / address counter
Returns: byte read from LCD controller
*************************************************************************/
#if RW_LINE_IMPLEMENTED==1
static uint8_t lcd_read(uint8_t rs)
{
uint8_t data;
#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
if (rs)
lcd_waitbusy();
if (PrevCmdInvolvedAddressCounter)
{
Delay_us(5);
PrevCmdInvolvedAddressCounter=0;
}
#endif
if (rs)
{
lcd_rs_port_high(); // RS=1: Read Data
#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
PrevCmdInvolvedAddressCounter=1;
#endif
}
else lcd_rs_port_low(); // RS=0: Read Busy Flag
lcd_rw_port_high(); // RW=1: Read Mode
#if LCD_BITS==4
lcd_db7_ddr_low(); // Configure Data Pins as Input
lcd_db6_ddr_low();
lcd_db5_ddr_low();
lcd_db4_ddr_low();
lcd_e_port_high(); // Read High Nibble First
Delay_ns(500);
data=lcd_db4_pin_get() << 4 | lcd_db5_pin_get() << 5 |
lcd_db6_pin_get() << 6 | lcd_db7_pin_get() << 7;
lcd_e_port_low();
Delay_ns(500);
lcd_e_port_high(); // Read Low Nibble
Delay_ns(500);
data|=lcd_db4_pin_get() << 0 | lcd_db5_pin_get() << 1 |
lcd_db6_pin_get() << 2 | lcd_db7_pin_get() << 3;
lcd_e_port_low();
lcd_db7_ddr_high(); // Configure Data Pins as Output
lcd_db6_ddr_high();
lcd_db5_ddr_high();
lcd_db4_ddr_high();
lcd_db7_port_high(); // Pins High (Inactive)
lcd_db6_port_high();
lcd_db5_port_high();
lcd_db4_port_high();
#else //using 8-Bit-Mode
lcd_db7_ddr_low(); // Configure Data Pins as Input
lcd_db6_ddr_low();
lcd_db5_ddr_low();
lcd_db4_ddr_low();
lcd_db3_ddr_low();
lcd_db2_ddr_low();
lcd_db1_ddr_low();
lcd_db0_ddr_low();
lcd_e_port_high();
Delay_ns(500);
data=lcd_db7_pin_get() << 7 | lcd_db6_pin_get() << 6 |
lcd_db5_pin_get() << 5 | lcd_db4_pin_get() << 4 |
lcd_db3_pin_get() << 3 | lcd_db2_pin_get() << 2 |
lcd_db1_pin_get() << 1 | lcd_db0_pin_get();
lcd_e_port_low();
lcd_db7_ddr_high(); // Configure Data Pins as Output
lcd_db6_ddr_high();
lcd_db5_ddr_high();
lcd_db4_ddr_high();
lcd_db3_ddr_high();
lcd_db2_ddr_high();
lcd_db1_ddr_high();
lcd_db0_ddr_high();
lcd_db7_port_high(); // Pins High (Inactive)
lcd_db6_port_high();
lcd_db5_port_high();
lcd_db4_port_high();
lcd_db3_port_high();
lcd_db2_port_high();
lcd_db1_port_high();
lcd_db0_port_high();
#endif
lcd_rw_port_low();
#if (WAIT_MODE==0 || RW_LINE_IMPLEMENTED==0)
if (rs)
Delay_us(40);
else Delay_us(1);
#endif
return data;
}
uint8_t lcd_getc()
{
return lcd_read(1);
}
#endif
/*************************************************************************
Low-level function to write byte to LCD controller
Input: data byte to write to LCD
rs 1: write data
0: write instruction
Returns: none
*************************************************************************/
static void lcd_write(uint8_t data,uint8_t rs)
{
#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
lcd_waitbusy();
if (PrevCmdInvolvedAddressCounter)
{
Delay_us(5);
PrevCmdInvolvedAddressCounter=0;
}
#endif
if (rs)
{
lcd_rs_port_high(); // RS=1: Write Character
#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
PrevCmdInvolvedAddressCounter=1;
#endif
}
else
{
lcd_rs_port_low(); // RS=0: Write Command
#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
PrevCmdInvolvedAddressCounter=0;
#endif
}
#if LCD_BITS==4
lcd_db7_port_set(data&_BV(7)); //Output High Nibble
lcd_db6_port_set(data&_BV(6));
lcd_db5_port_set(data&_BV(5));
lcd_db4_port_set(data&_BV(4));
Delay_ns(100);
lcd_e_port_high();
Delay_ns(500);
lcd_e_port_low();
lcd_db7_port_set(data&_BV(3)); //Output High Nibble
lcd_db6_port_set(data&_BV(2));
lcd_db5_port_set(data&_BV(1));
lcd_db4_port_set(data&_BV(0));
Delay_ns(100);
lcd_e_port_high();
Delay_ns(500);
lcd_e_port_low();
lcd_db7_port_high(); // All Data Pins High (Inactive)
lcd_db6_port_high();
lcd_db5_port_high();
lcd_db4_port_high();
#else //using 8-Bit_Mode
lcd_db7_port_set(data&_BV(7)); //Output High Nibble
lcd_db6_port_set(data&_BV(6));
lcd_db5_port_set(data&_BV(5));
lcd_db4_port_set(data&_BV(4));
lcd_db3_port_set(data&_BV(3)); //Output High Nibble
lcd_db2_port_set(data&_BV(2));
lcd_db1_port_set(data&_BV(1));
lcd_db0_port_set(data&_BV(0));
Delay_ns(100);
lcd_e_port_high();
Delay_ns(500);
lcd_e_port_low();
lcd_db7_port_high(); // All Data Pins High (Inactive)
lcd_db6_port_high();
lcd_db5_port_high();
lcd_db4_port_high();
lcd_db3_port_high();
lcd_db2_port_high();
lcd_db1_port_high();
lcd_db0_port_high();
#endif
#if (WAIT_MODE==0 || RW_LINE_IMPLEMENTED==0)
if (!rs && data<=((1<<LCD_CLR) | (1<<LCD_HOME))) // Is command clrscr or home?
Delay_us(1640);
else Delay_us(40);
#endif
}
/*************************************************************************
Send LCD controller instruction command
Input: instruction to send to LCD controller, see HD44780 data sheet
Returns: none
*************************************************************************/
void lcd_command(uint8_t cmd)
{
lcd_write(cmd,0);
}
/*************************************************************************
Set cursor to specified position
Input: pos position
Returns: none
*************************************************************************/
void lcd_goto(uint8_t pos)
{
lcd_command((1<<LCD_DDRAM)+pos);
}
/*************************************************************************
Clear screen
Input: none
Returns: none
*************************************************************************/
void lcd_clrscr()
{
lcd_command(1<<LCD_CLR);
}
/*************************************************************************
Return home
Input: none
Returns: none
*************************************************************************/
void lcd_home()
{
lcd_command(1<<LCD_HOME);
}
/*************************************************************************
Display character
Input: character to be displayed
Returns: none
*************************************************************************/
void lcd_putc(char c)
{
lcd_write(c,1);
}
/*************************************************************************
Display string
Input: string to be displayed
Returns: none
*************************************************************************/
void lcd_puts(const char *s)
{
register char c;
while ((c=*s++))
lcd_putc(c);
}
/*************************************************************************
Display string from flash
Input: string to be displayed
Returns: none
*************************************************************************/
void lcd_puts_P(const char *progmem_s)
{
register char c;
while ((c=pgm_read_byte(progmem_s++)))
lcd_putc(c);
}
/*************************************************************************
Initialize display
Input: none
Returns: none
*************************************************************************/
void lcd_init()
{
//Set All Pins as Output
lcd_e_ddr_high();
lcd_rs_ddr_high();
#if RW_LINE_IMPLEMENTED==1
lcd_rw_ddr_high();
#endif
lcd_db7_ddr_high();
lcd_db6_ddr_high();
lcd_db5_ddr_high();
lcd_db4_ddr_high();
#if LCD_BITS==8
lcd_db3_ddr_high();
lcd_db2_ddr_high();
lcd_db1_ddr_high();
lcd_db0_ddr_high();
#endif
//Set All Control Lines Low
lcd_e_port_low();
lcd_rs_port_low();
#if RW_LINE_IMPLEMENTED==1
lcd_rw_port_low();
#endif
//Set All Data Lines High
lcd_db7_port_high();
lcd_db6_port_high();
lcd_db5_port_high();
lcd_db4_port_high();
#if LCD_BITS==8
lcd_db3_port_high();
lcd_db2_port_high();
lcd_db1_port_high();
lcd_db0_port_high();
#endif
//Startup Delay
Delay_ms(DELAY_RESET);
//Initialize Display
lcd_db7_port_low();
lcd_db6_port_low();
Delay_ns(100);
lcd_e_port_high();
Delay_ns(500);
lcd_e_port_low();
Delay_us(4100);
lcd_e_port_high();
Delay_ns(500);
lcd_e_port_low();
Delay_us(100);
lcd_e_port_high();
Delay_ns(500);
lcd_e_port_low();
Delay_us(40);
//Init differs between 4-bit and 8-bit from here
#if (LCD_BITS==4)
lcd_db4_port_low();
Delay_ns(100);
lcd_e_port_high();
Delay_ns(500);
lcd_e_port_low();
Delay_us(40);
lcd_db4_port_low();
Delay_ns(100);
lcd_e_port_high();
Delay_ns(500);
lcd_e_port_low();
Delay_ns(500);
#if (LCD_DISPLAYS==1)
if (LCD_DISPLAY_LINES>1)
lcd_db7_port_high();
#else
unsigned char c;
switch (ActiveDisplay)
{
case 1 : c=LCD_DISPLAY_LINES; break;
case 2 : c=LCD_DISPLAY2_LINES; break;
#if (LCD_DISPLAYS>=3)
case 3 : c=LCD_DISPLAY3_LINES; break;
#endif
#if (LCD_DISPLAYS==4)
case 4 : c=LCD_DISPLAY4_LINES; break;
#endif
}
if (c>1)
lcd_db7_port_high();
#endif
Delay_ns(100);
lcd_e_port_high();
Delay_ns(500);
lcd_e_port_low();
Delay_us(40);
#else
#if (LCD_DISPLAYS==1)
if (LCD_DISPLAY_LINES<2)
lcd_db3_port_low();
#else
unsigned char c;
switch (ActiveDisplay)
{
case 1 : c=LCD_DISPLAY_LINES; break;
case 2 : c=LCD_DISPLAY2_LINES; break;
#if (LCD_DISPLAYS>=3)
case 3 : c=LCD_DISPLAY3_LINES; break;
#endif
#if (LCD_DISPLAYS==4)
case 4 : c=LCD_DISPLAY4_LINES; break;
#endif
}
if (c<2)
lcd_db3_port_low();
#endif
lcd_db2_port_low();
Delay_ns(100);
lcd_e_port_high();
Delay_ns(500);
lcd_e_port_low();
Delay_us(40);
#endif
//Display Off
lcd_command(_BV(LCD_DISPLAYMODE));
//Display Clear
lcd_clrscr();
//Entry Mode Set
lcd_command(_BV(LCD_ENTRY_MODE) | _BV(LCD_ENTRY_INC));
//Display On
lcd_command(_BV(LCD_DISPLAYMODE) | _BV(LCD_DISPLAYMODE_ON));
}
#if (LCD_DISPLAYS>1)
void lcd_use_display(int ADisplay)
{
if (ADisplay>=1 && ADisplay<=LCD_DISPLAYS)
ActiveDisplay=ADisplay;
}
#endif

61
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/*****************************************************************************
Title : HD44780 Library
Author : SA Development
Version: 1.11
*****************************************************************************/
#ifndef HD44780_H
#define HD44780_H
#include "hd44780_settings.h"
#include "inttypes.h"
//LCD Constants for HD44780
#define LCD_CLR 0 // DB0: clear display
#define LCD_HOME 1 // DB1: return to home position
#define LCD_ENTRY_MODE 2 // DB2: set entry mode
#define LCD_ENTRY_INC 1 // DB1: 1=increment, 0=decrement
#define LCD_ENTRY_SHIFT 0 // DB0: 1=display shift on
#define LCD_DISPLAYMODE 3 // DB3: turn lcd/cursor on
#define LCD_DISPLAYMODE_ON 2 // DB2: turn display on
#define LCD_DISPLAYMODE_CURSOR 1 // DB1: turn cursor on
#define LCD_DISPLAYMODE_BLINK 0 // DB0: blinking cursor
#define LCD_MOVE 4 // DB4: move cursor/display
#define LCD_MOVE_DISP 3 // DB3: move display (0-> cursor)
#define LCD_MOVE_RIGHT 2 // DB2: move right (0-> left)
#define LCD_FUNCTION 5 // DB5: function set
#define LCD_FUNCTION_8BIT 4 // DB4: set 8BIT mode (0->4BIT mode)
#define LCD_FUNCTION_2LINES 3 // DB3: two lines (0->one line)
#define LCD_FUNCTION_10DOTS 2 // DB2: 5x10 font (0->5x7 font)
#define LCD_CGRAM 6 // DB6: set CG RAM address
#define LCD_DDRAM 7 // DB7: set DD RAM address
#define LCD_BUSY 7 // DB7: LCD is busy
void lcd_init();
void lcd_command(uint8_t cmd);
void lcd_clrscr();
void lcd_home();
void lcd_goto(uint8_t pos);
#if RW_LINE_IMPLEMENTED==1
uint8_t lcd_getc();
#endif
void lcd_putc(char c);
void lcd_puts(const char *s);
void lcd_puts_P(const char *progmem_s);
#if (LCD_DISPLAYS>1)
void lcd_use_display(int ADisplay);
#endif
#endif

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Title : HD44780 Library
Author : SA Development
Version: 1.11
Parts of this code have been created or modified by Peter Fleury, Martin Thomas, and Andreas Heinzen as well. I went through it line by line and modified or improved it as necessary. This library has been cut down to only what was necessary to communicate with the LCD and does not include scrolling or wrapping features. See the libraries for the mentioned authors to get those features if you need them.
INSTALLATION:
-------------
Three files are provided:
hd44780.c - Main code file, you must add this to your project under "Source Files".
hd44780.h - Main include file, you must include this in any files you wish to use the library.
hd44780_settings_example.h - This is an example of the hd44780_settings.h file that the library requires (and will try to include). The settings that are intended to be customized for each project are located in this file.
The advantage to this is that the main C/H files are unmodified and can be updated to a new version without losing custom per project settings. Another advantage is that since they are unmodified, you can put them in a shared or library directory and use them in multiple separate projects. Then you only have one place to update them instead of multiple project directories.
Two ways you can implement this:
Non-shared method:
1. Copy these files into your project directory.
2. Rename "hd44780_settings_example.h" to "hd44780_settings.h".
3. Set the values appropriate to your project in "hd44780_settings.h".
4. Add the hd44780.c to your project.
5. Put "#include "hd44780.h" in any of your C files that need to use the functions.
Shared method:
1. Create a shared directory.
2. Copy these files into this directory.
To use it with a project:
1. Copy "hd44780_settings_example.h" to your project directory as "hd44780_settings.h". NOTE THE "_example" was dropped from the filename.
2. Set the values appropriate to your project in "hd44780_settings.h".
3. Add the hd44780.c to your project.
4. Put "#include "..\shared\hd44780.h" in any of your C files that need to use the functions. You may have to modify this to point to your shared directory.
5. Project -> Configuration Options -> Include Directories -> New -> Add your project directory. It should put a ".\" in the list. This step is necessary because when the library tries to include "hd44780_settings.h", it will look in your project directory and grab the one customized for that particular project. This is why it is important NOT to have a hd44780_settings.h in your shared directory and why I have this file named hd44780_settings_example.h instead. You can leave the example file in the shared directory as a file to copy and rename when starting a new project.
This library will work with my Advanced Delay Library as well by changing the USE_ADELAY_LIBRARY value from 0 to 1. By default it will use the __builtin_avr_delay_cycles function. My only gripe about this built in function is that if you are debugging at the assembly level it does not match C code lines to the assembly lines properly. Other than this it is exceptional. My Advanced Delay Library accomplishes the same thing while also adding additional delay functions that can expect a variable instead of a constant to be supplied and they don't suffer the C to assembly alignment bug that the built in ones do.
HOW TO USE:
-----------
Supports LCD communications on as few as 6 pins or as many as 11 pins depending on configuration.
The first choice you must make is whether you want to use 4 bit or 8 bit mode. Honestly this isn't a hard choice as I've tested both on my scope to see how the performance differed and both were very close to the same under all clock speeds I tested (16khz to 16mhz). I don't see the point in wasting 4 uC pins for 8 bit mode as it seems to have no advantage. Use the LCD_BITS parameter to set this:
LCD_BITS=4 // 4 for 4 Bit I/O Mode
LCD_BITS=8 // 8 for 8 Bit I/O Mode
The next choice is whether to implement a RW signal or not. If you don't need to read anything back from the LCD, then you can skip implementing it and simply connect the RW signal to ground. This is nice because it doesn't take up a uC pin this way. If however, you need to read something back from the LCD, you will need to implement RW. Use the RW_LINE_IMPLEMENTED parameter to set this:
RW_LINE_IMPLEMENTED=0 //0 for no RW line (RW on LCD tied to ground)
RW_LINE_IMPLEMENTED=1 //1 for RW line present
The last big decision is which WAIT_MODE to use. You can select between Delay Mode or Check Busy Mode. Delay Mode will delay after each LCD command to make sure that there is time for the LCD to execute the command before the next one can be issued. Check Busy Mode will read the check busy flag from the LCD to see if the LCD is still busy or ready for the next command. Check Busy Mode requires the RW line to be implemented, however you can implement an RW line (RW_LINE_IMPLEMENTED=1) and use Delay Mode (WAIT_MODE=0). You might think that the Check Busy Mode technique would be faster, but it is actually slower when running a clock below 10Mhz. This is because the extra code is takes to check it takes up more time that the Delay Mode would have. At 10Mhz or above, Check Busy Mode will be faster. At 16Mhz, it was 20% faster than Delay Mode, but at 8Mhz Delay Mode was 10% faster. Use the WAIT_MODE parameter to set this:
WAIT_MODE=0 // 0=Use Delay Method (Faster if running <10Mhz)
WAIT_MODE=1 // 1=Use Check Busy Flag (Faster if running >10Mhz) ***Requires RW Line***
This version implements multiple LCD display support for up to 4 devices. All devices will share their data/RS/RW(if implemented) pins. Each device will have its own E(enable) pin. You can use the command lcd_use_display(x) to choose which display commands will execute on. You will need to lcd_init() each one individually. This not only allows you to run 4 independent LCD display, but some displays like the 40 character x 4 line display are actually implemented with 2 lcd controllers. They will have an E and E2 pin so you will need this multiple display functionallity to use a display like this.
To init the display, clear the screen, and output "Hello World...":
lcd_init();
lcd_clrscr();
lcd_puts("Hello World...");
To put a character:
lcd_putc('A');
To turn off the display:
lcd_command(_BV(LCD_DISPLAYMODE));
To turn on the display:
lcd_command(_BV(LCD_DISPLAYMODE) | _BV(LCD_DISPLAYMODE_ON));
To turn on the display AND display an underline cursor:
lcd_command(_BV(LCD_DISPLAYMODE) | _BV(LCD_DISPLAYMODE_ON) | _BV(LCD_DISPLAYMODE_CURSOR));
To turn on the display AND display a blinking cursor:
lcd_command(_BV(LCD_DISPLAYMODE) | _BV(LCD_DISPLAYMODE_ON) | _BV(LCD_DISPLAYMODE_BLINK));
To move the cursor to the left:
lcd_command(_BV(LCD_MOVE));
To move the cursor to the right:
lcd_command(_BV(LCD_MOVE) | _BV(LCD_MOVE_RIGHT));
To move the cursor to a specific location:
lcd_goto(0x40); //0x40 is often the beginning of the second line
//each LCD display will have its memory mapped
//differently
To create a custom character:
lcd_command(_BV(LCD_CGRAM)+0*8); //The 0 on this line may be 0-7
lcd_putc(0b00000); //5x8 bitmap of character, in this example a backslash
lcd_putc(0b10000);
lcd_putc(0b01000);
lcd_putc(0b00100);
lcd_putc(0b00010);
lcd_putc(0b00001);
lcd_putc(0b00000);
lcd_putc(0b00000);
lcd_goto(0); //DO NOT FORGET to issue a GOTO command to go back to writing to the LCD
//ddram OR you will spend hours like me thinking the LCD is locked up
//when it working just fine and you are outputting to cgram instead of
//ddram!
To display this custom character:
lcd_putc(0); //Displays custom character 0
To shift the display so that the characters on screen are pushed to the left:
lcd_command(_BV(LCD_MOVE) | _BV(LCD_MOVE_DISP));
To shift the display so that the characters on screen are pushed to the left:
lcd_command(_BV(LCD_MOVE) | _BV(LCD_MOVE_DISP) | _BV(LCD_MOVE_RIGHT));
VERSION HISTORY:
----------------
1.00 - Initial version.
1.02 - Delay_ns, Delay_us, and Delay_ms added via a new included file "delay.h". All of these functions support values from 1-65535 so you can delay 65.535 seconds using Delay_ms, or Delay_ns(1) to delay 1ns. Realize that a delay of 1ns would only be possible if you were running at 1ghz, but asking for 1ns delay will get you a single clock delay. At 8mhz this is 125ns. The delays will get you "at least" what you ask for with as little more as possible. The reason the delay functions were added is because the LCD library I based this on "assumed" that 2 clocks were enough for a 500ns wait. This is TRUE if you are running at less than 2mhz, but not true if you are running faster. I modified these functions to use the new Delay_ns function above so it will ALWAYS wait 500ns on the enable line now.
1.03 - No longer includes my delay functions, but instead uses the internal builtin_avr_delay_cycles instead. You can still use it with my Advanced Delay Library, check the C file for info. This version also adds a clrscr in the init function. I was experiencing issues where a reset would corrupt part of the screen so this was necessary to make sure it starts clear.
1.05 - Reorganized all code to follow the standard C and H file techniques.
1.10 - Multiple LCD display support (Up to 4) added.
Bugs in the read command and 8 bit modes fixed and tested.
You are now able to put any pins on any pin and port. The data pins are no longer required to be on 0-3 or 0-7. This gives you full freedom to put these pins anywhere.
All pin changes are now done through SBI CBI instructions meaning there will be zero problems with interrupts of other things occuring on pins of the same port as the LCD pins.
Checkbusy used to end up in an infinite loop if the LCD didn't response with "not busy". I have put a 3ms maximum time on it (or 16 attempts minimum). Since all LCD commands should run with 1.64ms, this should be more than enough and will allow the processor to continue on instead of being permanently stuck. The delay however at 3ms everytime a call is made to the LCD will probably slow things down too much anyway, but I figured having this limit was better than nothing.
1.11 - A big issue in the LCD init code has been corrected which will now allow 4-bit mode to work properly below 2mhz. I've tested both 4-bit and 8-bit modes from 16khz to 16mhz with no issues.
Many commands have been marked as static if you don't need to access them, the only change is that lcd_read(x) is no longer available. You must use lcd_getc() instead.
RW_LINE_IMPLEMENTED has been added which allows you to indicate whether you are implementing the RW line or not. This used to be part of the WAIT_MODE, but having this option now allows you to implement the RW line so you can read from the LCD, but still use WAIT_MODE=0 for delays instead of using the check busy flag.
Check Busy has had an additional 6us delay added to it when the previous command involved a read or write that changes the address pointer. This is due to the check busy flag going low before this pointer is updated and is to ensure the LCD is ready for another command.

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#ifndef HD44780_SETTINGS_H
#define HD44780_SETTINGS_H
// This is done in the makefile
// #define F_CPU 15855484 // Set Clock Frequency
#define USE_ADELAY_LIBRARY 0 // Set to 1 to use my ADELAY library, 0 to use internal delay functions
#define LCD_BITS 4 // 4 for 4 Bit I/O Mode, 8 for 8 Bit I/O Mode
#define RW_LINE_IMPLEMENTED 1 // 0 for no RW line (RW on LCD tied to ground), 1 for RW line present
#define WAIT_MODE 1 // 0=Use Delay Method (Faster if running <10Mhz)
// 1=Use Check Busy Flag (Faster if running >10Mhz) ***Requires RW Line***
#define DELAY_RESET 15 // in mS
#if (LCD_BITS==8) // If using 8 bit mode, you must configure DB0-DB7
#define LCD_DB0_PORT PORTA
#define LCD_DB0_PIN 0
#define LCD_DB1_PORT PORTA
#define LCD_DB1_PIN 1
#define LCD_DB2_PORT PORTA
#define LCD_DB2_PIN 2
#define LCD_DB3_PORT PORTA
#define LCD_DB3_PIN 3
#endif
#define LCD_DB4_PORT PORTA // If using 4 bit omde, yo umust configure DB4-DB7
#define LCD_DB4_PIN 4
#define LCD_DB5_PORT PORTA
#define LCD_DB5_PIN 5
#define LCD_DB6_PORT PORTA
#define LCD_DB6_PIN 6
#define LCD_DB7_PORT PORTA
#define LCD_DB7_PIN 7
#define LCD_RS_PORT PORTA // Port for RS line
#define LCD_RS_PIN 0 // Pin for RS line
#define LCD_RW_PORT PORTA // Port for RW line (ONLY used if RW_LINE_IMPLEMENTED=1)
#define LCD_RW_PIN 1 // Pin for RW line (ONLY used if RW_LINE_IMPLEMENTED=1)
#define LCD_DISPLAYS 1 // Up to 4 LCD displays can be used at one time
// All pins are shared between displays except for the E
// pin which each display will have its own
// Display 1 Settings - if you only have 1 display, YOU MUST SET THESE
#define LCD_DISPLAY_LINES 1 // Number of Lines, Only Used for Set I/O Mode Command
#define LCD_E_PORT PORTA // Port for E line
#define LCD_E_PIN 2 // Pin for E line
#endif

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/*
Status.c
Functions for logging program status to the serial port, to
be used for debugging pruposes etc.
2008-03-21, P.Harvey-Smith.
*/
#include <avr/interrupt.h>
#include <stdio.h>
#include <ctype.h>
#include "terminalcodes.h"
#include "status.h"
#ifdef SERIAL_STATUS
static int StdioSerial_TxByte0(char DataByte, FILE *Stream);
static int StdioSerial_TxByte1(char DataByte, FILE *Stream);
FILE ser0stream = FDEV_SETUP_STREAM(StdioSerial_TxByte0,NULL,_FDEV_SETUP_WRITE);
FILE ser1stream = FDEV_SETUP_STREAM(StdioSerial_TxByte1,NULL,_FDEV_SETUP_WRITE);
void StdioSerial_TxByte(char DataByte, uint8_t Port)
{
#ifdef COOKED_SERIAL
if((DataByte=='\r') || (DataByte=='\n'))
{
if(Port==1)
{
Serial_TxByte1('\r');
Serial_TxByte1('\n');
}
else
{
Serial_TxByte0('\r');
Serial_TxByte0('\n');
}
}
else
#endif
if(Port==1)
Serial_TxByte1(DataByte);
else
Serial_TxByte0(DataByte);
}
int StdioSerial_TxByte0(char DataByte, FILE *Stream)
{
StdioSerial_TxByte(DataByte,0);
return 0;
}
int StdioSerial_TxByte1(char DataByte, FILE *Stream)
{
StdioSerial_TxByte(DataByte,1);
return 0;
}
void cls(uint8_t Port)
{
if(Port==1)
{
log1(ESC_ERASE_DISPLAY);
log1(ESC_CURSOR_POS(0,0));
}
else
{
log0(ESC_ERASE_DISPLAY);
log0(ESC_CURSOR_POS(0,0));
}
}
void USART_Init0(const uint32_t BaudRate)
{
#ifdef UCSR0A
UCSR0A = 0;
UCSR0B = ((1 << RXEN0) | (1 << TXEN0));
UCSR0C = ((1 << UCSZ01) | (1 << UCSZ00));
UBRR0 = SERIAL_UBBRVAL(BaudRate);
#else
UCR = ((1 << RXEN) | (1 << TXEN));
UBRR = SERIAL_UBBRVAL(BaudRate);
#endif
}
void USART_Init1(const uint32_t BaudRate)
{
#ifdef UCSR1A
UCSR1A = 0;
UCSR1B = ((1 << RXEN1) | (1 << TXEN1));
UCSR1C = ((1 << UCSZ11) | (1 << UCSZ10));
UBRR1 = SERIAL_UBBRVAL(BaudRate);
#endif
}
/** Transmits a given byte through the USART.
*
* \param DataByte Byte to transmit through the USART
*/
void Serial_TxByte0(const char DataByte)
{
#ifdef UCSR0A
while ( !( UCSR0A & (1<<UDRE0)) ) ;
UDR0=DataByte;
#else
while ( !( USR & (1<<UDRE)) ) ;
UDR=DataByte;
#endif
}
void Serial_TxByte1(const char DataByte)
{
#ifdef UCSR1A
while ( !( UCSR1A & (1<<UDRE1)) ) ;
UDR1=DataByte;
#endif
}
/** Receives a byte from the USART.
*
* \return Byte received from the USART
*/
char Serial_RxByte0(void)
{
#ifdef UCSR0A
while (!(USR & (1 << RXC0))) ;
return UDR0;
#else
while (!(USR & (1<<RXC))) ;
return UDR;
#endif
}
char Serial_RxByte1(void)
{
#ifdef UCSR1A
while (!(UCSR1A & (1 << RXC1))) ;
return UDR1;
#else
return 0;
#endif
}
uint8_t Serial_ByteRecieved0(void)
{
#ifdef UCSR0A
return (UCSR0A & (1 << RXC0));
#else
return (USR & (1<<RXC));
#endif
}
uint8_t Serial_ByteRecieved1(void)
{
#ifdef UCSR1A
return (UCSR1A & (1 << RXC1));
#else
return 0;
#endif
}
void Serial_Init(const uint32_t BaudRate0,
const uint32_t BaudRate1)
{
if (BaudRate0<=0)
USART_Init0(DefaultBaudRate);
else
USART_Init0(BaudRate0);
if (BaudRate1<=0)
USART_Init1(DefaultBaudRate);
else
USART_Init1(BaudRate1);
cls(0);
cls(1);
log0("stdio initialised\n");
log0("compiled at %s on %s\n",__TIME__,__DATE__);
log0("SerialPort0\n");
log1("SerialPort1\n");
}
#ifdef USE_HEXDUMP
void HexDump(const uint8_t *Buff,
uint16_t Length,
uint8_t Port)
{
char LineBuff[80];
char *LineBuffPos;
uint16_t LineOffset;
uint16_t CharOffset;
const uint8_t *BuffPtr;
BuffPtr=Buff;
for(LineOffset=0;LineOffset<Length;LineOffset+=16, BuffPtr+=16)
{
LineBuffPos=LineBuff;
LineBuffPos+=sprintf(LineBuffPos,"%4.4X ",LineOffset);
for(CharOffset=0;CharOffset<16;CharOffset++)
{
if((LineOffset+CharOffset)<Length)
LineBuffPos+=sprintf(LineBuffPos,"%2.2X ",BuffPtr[CharOffset]);
else
LineBuffPos+=sprintf(LineBuffPos," ");
}
for(CharOffset=0;CharOffset<16;CharOffset++)
{
if((LineOffset+CharOffset)<Length)
{
if(isprint(BuffPtr[CharOffset]))
LineBuffPos+=sprintf(LineBuffPos,"%c",BuffPtr[CharOffset]);
else
LineBuffPos+=sprintf(LineBuffPos," ");
}
else
LineBuffPos+=sprintf(LineBuffPos,".");
}
switch (Port)
{
case 0 : log0("%s\n",LineBuff); break;
case 1 : log1("%s\n",LineBuff); break;
}
}
}
void HexDumpHead(const uint8_t *Buff,
uint16_t Length,
uint8_t Port)
{
FILE *File;
File=&ser0stream;
switch (Port)
{
case 0 : File=&ser0stream; break;
case 1 : File=&ser1stream; break;
}
fprintf_P(File,PSTR("%d\n"),Buff);
fprintf_P(File,PSTR("Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ASCII\n"));
fprintf_P(File,PSTR("----------------------------------------------------------\n"));
HexDump(Buff,Length,Port);
};
#else
void HexDump(const uint8_t *Buff,
uint16_t Length,
uint8_t Port) {};
void HexDumpHead(const uint8_t *Buff,
uint16_t Length,
uint8_t Port) {};
#endif
#else
void USART_Init0(const uint32_t BaudRate) {};
void Serial_TxByte0(const char DataByte) {};
char Serial_RxByte0(void) {};
uint8_t Serial_ByteRecieved0(void) {};
void USART_Init1(const uint32_t BaudRate) {};
void Serial_TxByte1(const char DataByte) {};
char Serial_RxByte1(void) {};
uint8_t Serial_ByteRecieved1(void) {};
void Serial_Init(const uint32_t BaudRate0,
const uint32_t BaudRate1) {};
void cls(uint8_t Port) {};
void HexDump(const uint8_t *Buff,
uint16_t Length,
uint8_t Port) {};
void HexDumpHead(const uint8_t *Buff,
uint16_t Length,
uint8_t Port) {};
#endif

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/*
Status.h
Functions for logging program status to the serial port, to
be used for debugging pruposes etc.
2008-03-21, P.Harvey-Smith.
Some functions and macros borrowed from Dean Camera's LURFA
USB libraries.
*/
#include <avr/io.h>
#include <avr/pgmspace.h>
#include <stdbool.h>
#include <stdio.h>
#ifndef __STATUS_DEFINES__
#define __STATUS_DEFINES__
#ifdef SERIAL_STATUS
#define log0(format,...) fprintf_P(&ser0stream,PSTR(format),##__VA_ARGS__)
#define log1(format,...) fprintf_P(&ser1stream,PSTR(format),##__VA_ARGS__)
#else
#define log0(format,...)
#define log1(format,...)
#endif
//
// For stdio
//
extern FILE ser0stream;
extern FILE ser1stream;
/* Default baud rate if 0 passed to Serial_Init */
#define DefaultBaudRate 9600
/** Indicates whether a character has been received through the USART - boolean false if no character
* has been received, or non-zero if a character is waiting to be read from the reception buffer.
*/
#define Serial_IsCharReceived() ((UCSR1A & (1 << RXC1)) ? true : false)
/** Macro for calculating the baud value from a given baud rate when the U2X (double speed) bit is
* not set.
*/
#define SERIAL_UBBRVAL(baud) (((F_CPU / 16) / baud) - 1)
/** Macro for calculating the baud value from a given baud rate when the U2X (double speed) bit is
* set.
*/
#define SERIAL_2X_UBBRVAL(baud) (((F_CPU / 8) / baud) - 1)
#define SerEOL0() { Serial_TxByte0('\r'); Serial_TxByte0('\n'); }
#ifdef NOUSART1
#undef UCSR1A
#endif
void USART_Init0(const uint32_t BaudRate);
void Serial_TxByte0(const char DataByte);
char Serial_RxByte0(void);
uint8_t Serial_ByteRecieved0(void);
void USART_Init1(const uint32_t BaudRate);
void Serial_TxByte1(const char DataByte);
char Serial_RxByte1(void);
uint8_t Serial_ByteRecieved1(void);
void Serial_Init(const uint32_t BaudRate0,
const uint32_t BaudRate1);
void cls(uint8_t Port);
void HexDump(const uint8_t *Buff,
uint16_t Length,
uint8_t Port);
void HexDumpHead(const uint8_t *Buff,
uint16_t Length,
uint8_t Port);
#endif

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/*
LUFA Library
Copyright (C) Dean Camera, 2008.
dean [at] fourwalledcubicle [dot] com
www.fourwalledcubicle.com
*/
/*
Copyright 2008 Dean Camera (dean [at] fourwalledcubicle [dot] com)
Permission to use, copy, modify, and distribute this software
and its documentation for any purpose and without fee is hereby
granted, provided that the above copyright notice appear in all
copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of the author not be used in
advertising or publicity pertaining to distribution of the
software without specific, written prior permission.
The author disclaim all warranties with regard to this
software, including all implied warranties of merchantability
and fitness. In no event shall the author be liable for any
special, indirect or consequential damages or any damages
whatsoever resulting from loss of use, data or profits, whether
in an action of contract, negligence or other tortious action,
arising out of or in connection with the use or performance of
this software.
*/
/** \file
*
* ANSI terminal compatible escape sequences. These escape sequences are designed to be concatenated with existing
* strings to modify their display on a compatible terminal application.
*
* \note If desired, the macro DISABLE_TERMINAL_CODES can be defined in the project makefile and passed to the GCC
* compiler via the -D switch to disable the terminal codes without modifying the source, for use with non
* compatible terminals (any terminal code then equate to empty strings).
*
* Example Usage:
* \code
* printf("Some String, " ESC_BOLD_ON " Some bold string");
* \endcode
*/
#ifndef __TERMINALCODES_H__
#define __TERMINALCODES_H__
/* Public Interface - May be used in end-application: */
/* Macros: */
#if !defined(DISABLE_TERMINAL_CODES)
/** Creates an ANSII escape sequence with the payload specified by "c". */
#define ANSI_ESCAPE_SEQUENCE(c) "\33[" c
#else
#define ANSI_ESCAPE_SEQUENCE(c)
#endif
/** Resets any escape sequence modifiers back to their defaults. */
#define ESC_RESET ANSI_ESCAPE_SEQUENCE("0m")
/** Turns on bold so that any following text is printed to the terminal in bold. */
#define ESC_BOLD_ON ANSI_ESCAPE_SEQUENCE("1m")
/** Turns on italics so that any following text is printed to the terminal in italics. */
#define ESC_ITALICS_ON ANSI_ESCAPE_SEQUENCE("3m")
/** Turns on underline so that any following text is printed to the terminal underlined. */
#define ESC_UNDERLINE_ON ANSI_ESCAPE_SEQUENCE("4m")
/** Turns on inverse so that any following text is printed to the terminal in inverted colours. */
#define ESC_INVERSE_ON ANSI_ESCAPE_SEQUENCE("7m")
/** Turns on strikethrough so that any following text is printed to the terminal with a line through the
* center.
*/
#define ESC_STRIKETHROUGH_ON ANSI_ESCAPE_SEQUENCE("9m")
/** Turns off bold so that any following text is printed to the terminal in non bold. */
#define ESC_BOLD_OFF ANSI_ESCAPE_SEQUENCE("22m")
/** Turns off italics so that any following text is printed to the terminal in non italics. */
#define ESC_ITALICS_OFF ANSI_ESCAPE_SEQUENCE("23m")
/** Turns off underline so that any following text is printed to the terminal non underlined. */
#define ESC_UNDERLINE_OFF ANSI_ESCAPE_SEQUENCE("24m")
/** Turns off inverse so that any following text is printed to the terminal in non inverted colours. */
#define ESC_INVERSE_OFF ANSI_ESCAPE_SEQUENCE("27m")
/** Turns off strikethrough so that any following text is printed to the terminal without a line through
* the center.
*/
#define ESC_STRIKETHROUGH_OFF ANSI_ESCAPE_SEQUENCE("29m")
/** Sets the foreground (text) colour to black. */
#define ESC_FG_BLACK ANSI_ESCAPE_SEQUENCE("30m")
/** Sets the foreground (text) colour to red. */
#define ESC_FG_RED ANSI_ESCAPE_SEQUENCE("31m")
/** Sets the foreground (text) colour to green. */
#define ESC_FG_GREEN ANSI_ESCAPE_SEQUENCE("32m")
/** Sets the foreground (text) colour to yellow. */
#define ESC_FG_YELLOW ANSI_ESCAPE_SEQUENCE("33m")
/** Sets the foreground (text) colour to blue. */
#define ESC_FG_BLUE ANSI_ESCAPE_SEQUENCE("34m")
/** Sets the foreground (text) colour to magenta. */
#define ESC_FG_MAGENTA ANSI_ESCAPE_SEQUENCE("35m")
/** Sets the foreground (text) colour to cyan. */
#define ESC_FG_CYAN ANSI_ESCAPE_SEQUENCE("36m")
/** Sets the foreground (text) colour to white. */
#define ESC_FG_WHITE ANSI_ESCAPE_SEQUENCE("37m")
/** Sets the foreground (text) colour to the terminal's default. */
#define ESC_FG_DEFAULT ANSI_ESCAPE_SEQUENCE("39m")
/** Sets the text background colour to black. */
#define ESC_BG_BLACK ANSI_ESCAPE_SEQUENCE("40m")
/** Sets the text background colour to red. */
#define ESC_BG_RED ANSI_ESCAPE_SEQUENCE("41m")
/** Sets the text background colour to green. */
#define ESC_BG_GREEN ANSI_ESCAPE_SEQUENCE("42m")
/** Sets the text background colour to yellow. */
#define ESC_BG_YELLOW ANSI_ESCAPE_SEQUENCE("43m")
/** Sets the text background colour to blue. */
#define ESC_BG_BLUE ANSI_ESCAPE_SEQUENCE("44m")
/** Sets the text background colour to magenta. */
#define ESC_BG_MAGENTA ANSI_ESCAPE_SEQUENCE("45m")
/** Sets the text background colour to cyan. */
#define ESC_BG_CYAN ANSI_ESCAPE_SEQUENCE("46m")
/** Sets the text background colour to white. */
#define ESC_BG_WHITE ANSI_ESCAPE_SEQUENCE("47m")
/** Sets the text background colour to the terminal's default. */
#define ESC_BG_DEFAULT ANSI_ESCAPE_SEQUENCE("49m")
/** Sets the cursor position to the given line and column. */
#define ESC_CURSOR_POS(L, C) ANSI_ESCAPE_SEQUENCE(#L ";" #C "H")
/** Moves the cursor up the given number of lines. */
#define ESC_CURSOR_UP(L) ANSI_ESCAPE_SEQUENCE(#L "A")
/** Moves the cursor down the given number of lines. */
#define ESC_CURSOR_DOWN(L) ANSI_ESCAPE_SEQUENCE(#L "B")
/** Moves the cursor to the right the given number of columns. */
#define ESC_CURSOR_FORWARD(C) ANSI_ESCAPE_SEQUENCE(#C "C")
/** Moves the cursor to the left the given number of columns. */
#define ESC_CURSOR_BACKWARD(C) ANSI_ESCAPE_SEQUENCE(#C "D")
/** Saves the current cursor position so that it may be restored with ESC_CURSOR_POS_RESTORE. */
#define ESC_CURSOR_POS_SAVE ANSI_ESCAPE_SEQUENCE("s")
/** Restores the cursor position to the last position saved with ESC_CURSOR_POS_SAVE. */
#define ESC_CURSOR_POS_RESTORE ANSI_ESCAPE_SEQUENCE("u")
/** Erases the entire display, returning the cursor to the top left. */
#define ESC_ERASE_DISPLAY ANSI_ESCAPE_SEQUENCE("2J")
/** Erases the current line, returning the cursor to the far left. */
#define ESC_ERASE_LINE ANSI_ESCAPE_SEQUENCE("K")
#endif

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#!/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/xtclsh
project open AtomBusMon.xise
process run "Generate Programming File"
project close
exit

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#!/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/xtclsh
project open AtomBusMon.xise
project clean
project close
exit

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-- *****************************************************************************************
-- AVR constants and type declarations
-- Version 1.0A(Special version for the JTAG OCD)
-- Modified 05.05.2004
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use WORK.SynthCtrlPack.all;
package AVRuCPackage is
-- Old package
type ext_mux_din_type is array(0 to CExtMuxInSize-1) of std_logic_vector(7 downto 0);
subtype ext_mux_en_type is std_logic_vector(0 to CExtMuxInSize-1);
-- End of old package
constant IOAdrWidth : positive := 16;
type AVRIOAdr_Type is array(0 to 63) of std_logic_vector(IOAdrWidth-1 downto 0);
constant CAVRIOAdr : AVRIOAdr_Type :=("0000000000000000","0000000000000001","0000000000000010","0000000000000011",
"0000000000000100","0000000000000101","0000000000000110","0000000000000111",
"0000000000001000","0000000000001001","0000000000001010","0000000000001011",
"0000000000001100","0000000000001101","0000000000001110","0000000000001111",
"0000000000010000","0000000000010001","0000000000010010","0000000000010011",
"0000000000010100","0000000000010101","0000000000010110","0000000000010111",
"0000000000011000","0000000000011001","0000000000011010","0000000000011011",
"0000000000011100","0000000000011101","0000000000011110","0000000000011111",
"0000000000100000","0000000000100001","0000000000100010","0000000000100011",
"0000000000100100","0000000000100101","0000000000100110","0000000000100111",
"0000000000101000","0000000000101001","0000000000101010","0000000000101011",
"0000000000101100","0000000000101101","0000000000101110","0000000000101111",
"0000000000110000","0000000000110001","0000000000110010","0000000000110011",
"0000000000110100","0000000000110101","0000000000110110","0000000000110111",
"0000000000111000","0000000000111001","0000000000111010","0000000000111011",
"0000000000111100","0000000000111101","0000000000111110","0000000000111111"); -- I/O port addresses
-- I/O register file
constant RAMPZ_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3B#);
constant SPL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3D#);
constant SPH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3E#);
constant SREG_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3F#);
-- End of I/O register file
-- UART
constant UDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0C#);
constant UBRR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#09#);
constant USR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0B#);
constant UCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0A#);
-- End of UART
-- Timer/Counter
constant TCCR0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#33#);
constant TCCR1A_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2F#);
constant TCCR1B_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2E#);
constant TCCR2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#25#);
constant ASSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#30#);
constant TIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#37#);
constant TIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#36#);
constant TCNT0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#32#);
constant TCNT2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#24#);
constant OCR0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#31#);
constant OCR2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#23#);
constant TCNT1H_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2D#);
constant TCNT1L_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2C#);
constant OCR1AH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2B#);
constant OCR1AL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2A#);
constant OCR1BH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#29#);
constant OCR1BL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#28#);
constant ICR1AH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#27#);
constant ICR1AL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#26#);
-- End of Timer/Counter
-- Service module
constant MCUCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#35#);
constant EIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#39#);
constant EIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#38#);
constant EICR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3A#);
constant MCUSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#34#);
constant XDIV_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3C#);
-- End of service module
-- EEPROM
constant EEARH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1F#);
constant EEARL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1E#);
constant EEDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1D#);
constant EECR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1C#);
-- End of EEPROM
-- SPI
constant SPDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0F#);
constant SPSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0E#);
constant SPCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0D#);
-- End of SPI
-- PORTA addresses
constant PORTA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1B#);
constant DDRA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1A#);
constant PINA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#19#);
-- PORTB addresses
constant PORTB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#18#);
constant DDRB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#17#);
constant PINB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#16#);
-- PORTC addresses
constant PORTC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#15#);
constant DDRC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#14#);
constant PINC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#13#);
-- PORTD addresses
constant PORTD_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#12#);
constant DDRD_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#11#);
constant PIND_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#10#);
-- PORTE addresses
constant PORTE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#03#);
constant DDRE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#02#);
constant PINE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#01#);
-- PORTF addresses
constant PORTF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#07#);
constant DDRF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#08#);
constant PINF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#00#);
-- ******************** Parallel port address table **************************************
constant CMaxNumOfPPort : positive := 6;
type PPortAdrTbl_Type is record Port_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
DDR_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
Pin_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
end record;
type PPortAdrTblArray_Type is array (0 to CMaxNumOfPPort-1) of PPortAdrTbl_Type;
constant PPortAdrArray : PPortAdrTblArray_Type := ((PORTA_Address,DDRA_Address,PINA_Address), -- PORTA
(PORTB_Address,DDRB_Address,PINB_Address), -- PORTB
(PORTC_Address,DDRC_Address,PINC_Address), -- PORTC
(PORTD_Address,DDRD_Address,PIND_Address), -- PORTD
(PORTE_Address,DDRE_Address,PINE_Address), -- PORTE
(PORTF_Address,DDRF_Address,PINF_Address)); -- PORTF
-- ***************************************************************************************
-- Analog to digital converter
constant ADCL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#04#);
constant ADCH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#05#);
constant ADCSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#06#);
constant ADMUX_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#07#);
-- Analog comparator
constant ACSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#08#);
-- Watchdog
constant WDTCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#21#);
-- JTAG OCDR (ATmega128)
constant OCDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#22#);
-- JTAG OCDR (ATmega16)
--constant OCDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#31#);
-- ***************************************************************************************
-- Function declaration
function LOG2(Number : positive) return natural;
end AVRuCPackage;
package body AVRuCPackage is
-- Functions
function LOG2(Number : positive) return natural is
variable Temp : positive;
begin
Temp := 1;
if Number=1 then
return 0;
else
for i in 1 to integer'high loop
Temp := 2*Temp;
if Temp>=Number then
return i;
end if;
end loop;
end if;
end LOG2;
-- End of functions
end AVRuCPackage;

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-- *****************************************************************************************
-- AVR synthesis control package
-- Version 1.32 (Special version for the JTAG OCD)
-- Modified 14.07.2005
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package SynthCtrlPack is
-- Please note: Do not change these settings, this is not quite ready yet. Jack Gassett
-- Control the size of Program and Data memory.
constant CDATAMEMSIZE : integer := 11; --2^(x+1)=Data SRAM Memory Size (10=2048) (Default 11=4096) (12=8192)
constant CPROGMEMSIZE : integer := 12; --(2^(x+1))*2)=Program Memory Size (10=4096) (11=8192) (Default 12=16384)
-- Calculate at Wolfram Alpha (http://www.wolframalpha.com/input/?i=%282^%28x%2B1%29%29*2%29%2Cx%3D12)
-- Reset generator
constant CSecondClockUsed : boolean := FALSE;
constant CImplClockSw : boolean := FALSE;
-- Only for ASICs
constant CSynchLatchUsed : boolean := FALSE;
-- Register file
constant CResetRegFile : boolean := TRUE;
-- External multiplexer size
constant CExtMuxInSize : positive := 16;
end SynthCtrlPack;

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-- *****************************************************************************************
-- AVR constants
-- Version 2.1
-- Modified 08.01.2007
-- Designed by Ruslan Lepetenok
-- EIND register address is added
-- type ext_mux_din_type and subtype ext_mux_en_type were removed
-- LOG2 function was removed
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package avr_adr_pack is
constant PINF_address : integer := 16#00#; -- Input Pins Port F
constant PINE_address : integer := 16#01#; -- Input Pins Port E
constant DDRE_address : integer := 16#02#; -- Data Direction Regis Port E
constant PORTE_address : integer := 16#03#; -- Data Register Port E
constant ADCL_address : integer := 16#04#; -- ADC Data register(Low)
constant ADCH_address : integer := 16#05#; -- ADC Data register(High)
constant ADCSRA_address : integer := 16#06#; -- ADC Control and Status Register
constant ADMUX_address : integer := 16#07#; -- ADC Multiplexer Selection Register
constant ACSR_address : integer := 16#08#; -- Analog Comparator Control and Status Register
constant UBRR0L_address : integer := 16#09#; -- USART0 Baud Rate Register Low
constant UCSR0B_address : integer := 16#0A#; -- USART0 Control and Status Register B
constant UCSR0A_address : integer := 16#0B#; -- USART0 Control and Status Register A
constant UDR0_address : integer := 16#0C#; -- USART0 I/O Data Register
constant SPCR_address : integer := 16#0D#; -- SPI Control Register
constant SPSR_address : integer := 16#0E#; -- SPI Status Register
constant SPDR_address : integer := 16#0F#; -- SPI I/O Data Register
constant PIND_address : integer := 16#10#; -- Input Pins Port D
constant DDRD_address : integer := 16#11#; -- Data Direction Regis Port D
constant PORTD_address : integer := 16#12#; -- Data Register Port D
constant PINC_address : integer := 16#13#; -- Input Pins Port C
constant DDRC_address : integer := 16#14#; -- Data Direction Regis Port C
constant PORTC_address : integer := 16#15#; -- Data Register Port C
constant PINB_address : integer := 16#16#; -- Input Pins Port B
constant DDRB_address : integer := 16#17#; -- Data Direction Regis Port B
constant PORTB_address : integer := 16#18#; -- Data Register Port B
constant PINA_address : integer := 16#19#; -- Input Pins Port A
constant DDRA_address : integer := 16#1A#; -- Data Direction Regis Port A
constant PORTA_address : integer := 16#1B#; -- Data Register Port A
constant EECR_address : integer := 16#1C#; -- EEPROM Control Register
constant EEDR_address : integer := 16#1D#; -- EEPROM Data Register
constant EEARL_address : integer := 16#1E#; -- EEPROM Address Register(Low)
constant EEARH_address : integer := 16#1F#; -- EEPROM Address Register(High)
constant SFIOR_address : integer := 16#20#; -- Special Function I/O Register
constant WDTCR_address : integer := 16#21#; -- Watchdog Timer Control Register
constant OCDR_address : integer := 16#22#; -- On-Chip Debug Register
constant OCR2_address : integer := 16#23#; -- Timer/Counter 2 Output Compare Register
constant TCNT2_address : integer := 16#24#; -- Timer/Counter 2
constant TCCR2_address : integer := 16#25#; -- Timer/Counter 2 Control Register
constant ICR1L_address : integer := 16#26#; -- Timer/Counter 1 Input Capture Register(Low)
constant ICR1H_address : integer := 16#27#; -- Timer/Counter 1 Input Capture Register(High)
constant OCR1BL_address : integer := 16#28#; -- Timer/Counter 1 Output Compare Register B(Low)
constant OCR1BH_address : integer := 16#29#; -- Timer/Counter 1 Output Compare Register B(High)
constant OCR1AL_address : integer := 16#2A#; -- Timer/Counter 1 Output Compare Register A(Low)
constant OCR1AH_address : integer := 16#2B#; -- Timer/Counter 1 Output Compare Register A(High)
constant TCNT1L_address : integer := 16#2C#; -- Timer/Counter 1 Register(Low)
constant TCNT1H_address : integer := 16#2D#; -- Timer/Counter 1 Register(High)
constant TCCR1B_address : integer := 16#2E#; -- Timer/Counter 1 Control Register B
constant TCCR1A_address : integer := 16#2F#; -- Timer/Counter 1 Control Register A
constant ASSR_address : integer := 16#30#; -- Asynchronous mode Status Register
constant OCR0_address : integer := 16#31#; -- Timer/Counter 0 Output Compare Register
constant TCNT0_address : integer := 16#32#; -- Timer/Counter 0
constant TCCR0_address : integer := 16#33#; -- Timer/Counter 0 Control Register
constant MCUCSR_address : integer := 16#34#; -- MCU general Control and Status Register
constant MCUCR_address : integer := 16#35#; -- MCU general Control Register
constant TIFR_address : integer := 16#36#; -- Timer/Counter Interrupt Flag Register
constant TIMSK_address : integer := 16#37#; -- Timer/Counter Interrupt Mask Register
constant EIFR_address : integer := 16#38#; -- External Interrupt Flag Register
constant EIMSK_address : integer := 16#39#; -- External Interrupt Mask Register
constant EICRB_address : integer := 16#3A#; -- External Interrupt Control Register B
constant RAMPZ_address : integer := 16#3B#; -- RAM Page Z Select Register
constant XDIV_address : integer := 16#3C#; -- XTAL Divide Control Register
constant SPL_address : integer := 16#3D#; -- Stack Pointer(Low)
constant SPH_address : integer := 16#3E#; -- Stack Pointer(High)
constant SREG_address : integer := 16#3F#; -- Status Register
-- Extended I/O space
constant DDRF_address : integer := 16#61#; -- Data Direction Regis Port F
constant PORTF_address : integer := 16#62#; -- Data Register Port F
constant PING_address : integer := 16#63#; -- Input Pins Port G
constant DDRG_address : integer := 16#64#; -- Data Direction Regis Port G
constant PORTG_address : integer := 16#65#; -- Data Register Port G
constant SPMCSR_address : integer := 16#68#; -- Store Program Memory Control and Status Register
constant EICRA_address : integer := 16#6A#; -- External Interrupt Control Register A
constant XMCRB_address : integer := 16#6C#; -- External Memory Control Register B
constant XMCRA_address : integer := 16#6D#; -- External Memory Control Register A
constant OSCCAL_address : integer := 16#6F#; -- Oscillator Calibration Register
constant TWBR_address : integer := 16#70#; -- TWI Bit Rate Register
constant TWSR_address : integer := 16#71#; -- TWI Status Register
constant TWAR_address : integer := 16#72#; -- TWI Address Register
constant TWDR_address : integer := 16#73#; -- TWI Data Register
constant TWCR_address : integer := 16#74#; -- TWI Control Register
constant OCR1CL_address : integer := 16#78#; -- Timer/Counter 1 Output Compare Register C(Low)
constant OCR1CH_address : integer := 16#79#; -- Timer/Counter 1 Output Compare Register C(High)
constant TCCR1C_address : integer := 16#7A#; -- Timer/Counter 1 Control Register C
constant ETIFR_address : integer := 16#7C#; -- Extended Timer/Counter Interrupt Flag Register
constant ETIMSK_address : integer := 16#7D#; -- Extended Timer/Counter Interrupt Mask Register
constant ICR3L_address : integer := 16#80#; -- Timer/Counter 3 Input Capture Register(Low)
constant ICR3H_address : integer := 16#81#; -- Timer/Counter 3 Input Capture Register(High)
constant OCR3CL_address : integer := 16#82#; -- Timer/Counter 3 Output Compare Register C(Low)
constant OCR3CH_address : integer := 16#83#; -- Timer/Counter 3 Output Compare Register C(High)
constant OCR3BL_address : integer := 16#84#; -- Timer/Counter 3 Output Compare Register B(Low)
constant OCR3BH_address : integer := 16#85#; -- Timer/Counter 3 Output Compare Register B(High)
constant OCR3AL_address : integer := 16#86#; -- Timer/Counter 3 Output Compare Register A(Low)
constant OCR3AH_address : integer := 16#87#; -- Timer/Counter 3 Output Compare Register A(High)
constant TCNT3L_address : integer := 16#88#; -- Timer/Counter 3 Register Low
constant TCNT3H_address : integer := 16#89#; -- Timer/Counter 3 Register Low
constant TCCR3B_address : integer := 16#8A#; -- Timer/Counter 3 Control Register B
constant TCCR3A_address : integer := 16#8B#; -- Timer/Counter 3 Control Register A
constant TCCR3C_address : integer := 16#8C#; -- Timer/Counter 3 Control Register C
constant UBRR0H_address : integer := 16#90#; -- USART0 Baud Rate Register High
constant UCSR0C_address : integer := 16#95#; -- USART0 Control and Status Register C
constant UBRR1H_address : integer := 16#98#; -- USART1 Baud Rate Register High
constant UBRR1L_address : integer := 16#99#; -- USART1 Baud Rate Register Low
constant UCSR1B_address : integer := 16#9A#; -- USART1 Control and Status Register B
constant UCSR1A_address : integer := 16#9B#; -- USART1 Control and Status Register A
constant UDR1_address : integer := 16#9C#; -- USART1 I/O Data Register
constant UCSR1C_address : integer := 16#9D#; -- USART1 Control and Status Register C
-- Cores with 22 bit PC(I/O)
constant EIND_Address : integer := 16#3C#; -- !!!TBD!!! Occupated by XDIV in Mega128
end avr_adr_pack;

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--**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package spi_mod_comp_pack is
component spi_mod is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- SPI i/f
misoi : in std_logic;
mosii : in std_logic;
scki : in std_logic; -- Resynch
ss_b : in std_logic; -- Resynch
misoo : out std_logic;
mosio : out std_logic;
scko : out std_logic;
spe : out std_logic;
spimaster : out std_logic;
-- IRQ
spiirq : out std_logic;
spiack : in std_logic;
-- Slave Programming Mode
por : in std_logic;
spiextload : in std_logic;
spidwrite : out std_logic;
spiload : out std_logic
);
end component;
end spi_mod_comp_pack;

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-- *****************************************************************************************
-- Standard libraries
-- Version 0.2
-- Modified 02.12.2006
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package std_library is
type log2array_type is array(0 to 1024) of integer;
constant fn_log2 : log2array_type := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
constant fn_log2x : log2array_type := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
-- *********************************************************************************
function fn_det_x(d : std_logic_vector) return boolean;
function fn_det_x(d : std_logic) return boolean;
function fn_xor_vect(vect : std_logic_vector) return std_logic;
function fn_or_vect(vect : std_logic_vector) return std_logic;
function fn_and_vect(vect : std_logic_vector) return std_logic;
function fn_to_integer(vect : std_logic_vector) return integer;
function fn_to_integer(d : std_logic) return integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic(b : boolean) return std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic;
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
end std_library;
package body std_library is
function fn_det_x(d : std_logic_vector) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_det_x(d : std_logic) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_xor_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp xor vect(i);
end loop;
return(temp);
end fn_xor_vect;
function fn_or_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp or vect(i);
end loop;
return(temp);
end fn_or_vect;
function fn_and_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '1';
for i in vect'range loop
temp := temp and vect(i);
end loop;
return(temp);
end fn_and_vect;
function fn_to_integer(vect : std_logic_vector) return integer is
begin
if (not fn_det_x(vect)) then
return(to_integer(unsigned(vect)));
else
return(0);
end if;
end fn_to_integer;
function fn_to_integer(d : std_logic) return integer is
begin
if (not fn_det_x(d)) then
if (d = '1') then
return(1);
else
return(0);
end if;
else
return(0);
end if;
end fn_to_integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_unsigned(int, width));
return(temp);
end fn_to_std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_signed(int, width));
return(temp);
end fn_to_std_logic_vector_signed;
function fn_to_std_logic(b : boolean) return std_logic is
begin
if (b) then
return('1');
else
return('0');
end if;
end fn_to_std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector((2**vect'length)-1 downto 0);
variable i : integer range result'range;
begin
result := (others => '0');
i := 0;
if (not fn_det_x(vect)) then
i := to_integer(unsigned(vect));
end if;
result(i) := '1';
return(result);
end fn_dcd;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic is
variable result : std_logic_vector(vect'length-1 downto 0);
variable i : integer range result'range;
begin
result := vect;
i := 0;
if (not fn_det_x(sel)) then
i := to_integer(unsigned(sel));
end if;
return(result(i));
end fn_mux;
-- >>>>
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
if (not (fn_det_x(vect_a) or fn_det_x(vect_b))) then
return(std_logic_vector(unsigned(vect_a) + unsigned(vect_b)));
-- pragma translate_off
else
tmp_a := (others =>'X');
tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
-- pragma translate_on
end if;
end "+";
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
if (not fn_det_x(vect)) then
return(std_logic_vector(unsigned(vect) + int));
-- pragma translate_off
else
temp := (others =>'X');
return(temp);
-- pragma translate_on
end if;
end "+";
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
if (not (fn_det_x(vect) or fn_det_x(d))) then
return(std_logic_vector(unsigned(vect) + unsigned(tmp_b)));
-- pragma translate_off
else
tmp_b := (others =>'X');
return(tmp_b);
-- pragma translate_on
end if;
end "+";
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
if (not (fn_det_x(vect_a) or fn_det_x(vect_b))) then
return(std_logic_vector(unsigned(vect_a) - unsigned(vect_b)));
-- pragma translate_off
else
tmp_a := (others =>'X'); tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
-- pragma translate_on
end if;
end "-";
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
if (not fn_det_x(vect)) then
return(std_logic_vector(unsigned(vect) - int));
-- pragma translate_off
else
temp := (others =>'X');
return(temp);
-- pragma translate_on
end if;
end "-";
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
if (not fn_det_x(vect)) then
return(std_logic_vector(int - unsigned(vect)));
-- pragma translate_off
else
temp := (others =>'X');
return(temp);
-- pragma translate_on
end if;
end "-";
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
if (not (fn_det_x(vect) or fn_det_x(d))) then
return(std_logic_vector(unsigned(vect) - unsigned(tmp_b)));
-- pragma translate_off
else tmp_a := (others =>'X');
return(tmp_a);
-- pragma translate_on
end if;
end "-";
end std_library;

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--************************************************************************************************
-- Component declarations for AVR core
-- Version 1.52? (Special version for fhe JTAG OCD)
-- Designed by Ruslan Lepetenok
-- Modified 31.06.2006
-- PM clock enable was added
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package AVR_Core_CompPack is
component pm_fetch_dec is port(
-- Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
-- JTAG OCD support
valid_instr : out std_logic;
insert_nop : in std_logic;
block_irq : in std_logic;
change_flow : out std_logic;
-- Program memory
pc : out std_logic_vector (15 downto 0);
inst : in std_logic_vector (15 downto 0);
-- I/O control
adr : out std_logic_vector (15 downto 0);
iore : out std_logic;
iowe : out std_logic;
-- Data memory control
ramadr : out std_logic_vector (15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic;
-- Data paths
dbusin : in std_logic_vector (7 downto 0);
dbusout : out std_logic_vector (7 downto 0);
-- Interrupt
irqlines : in std_logic_vector (22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
--Sleep
sleepi : out std_logic;
irqok : out std_logic;
--Watchdog
wdri : out std_logic;
-- ALU interface(Data inputs)
alu_data_r_in : out std_logic_vector(7 downto 0);
-- ALU interface(Instruction inputs)
idc_add_out : out std_logic;
idc_adc_out : out std_logic;
idc_adiw_out : out std_logic;
idc_sub_out : out std_logic;
idc_subi_out : out std_logic;
idc_sbc_out : out std_logic;
idc_sbci_out : out std_logic;
idc_sbiw_out : out std_logic;
adiw_st_out : out std_logic;
sbiw_st_out : out std_logic;
idc_and_out : out std_logic;
idc_andi_out : out std_logic;
idc_or_out : out std_logic;
idc_ori_out : out std_logic;
idc_eor_out : out std_logic;
idc_com_out : out std_logic;
idc_neg_out : out std_logic;
idc_inc_out : out std_logic;
idc_dec_out : out std_logic;
idc_cp_out : out std_logic;
idc_cpc_out : out std_logic;
idc_cpi_out : out std_logic;
idc_cpse_out : out std_logic;
idc_lsr_out : out std_logic;
idc_ror_out : out std_logic;
idc_asr_out : out std_logic;
idc_swap_out : out std_logic;
-- ALU interface(Data output)
alu_data_out : in std_logic_vector(7 downto 0);
-- ALU interface(Flag outputs)
alu_c_flag_out : in std_logic;
alu_z_flag_out : in std_logic;
alu_n_flag_out : in std_logic;
alu_v_flag_out : in std_logic;
alu_s_flag_out : in std_logic;
alu_h_flag_out : in std_logic;
-- General purpose register file interface
reg_rd_in : out std_logic_vector (7 downto 0);
reg_rd_out : in std_logic_vector (7 downto 0);
reg_rd_adr : out std_logic_vector (4 downto 0);
reg_rr_out : in std_logic_vector (7 downto 0);
reg_rr_adr : out std_logic_vector (4 downto 0);
reg_rd_wr : out std_logic;
post_inc : out std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
pre_dec : out std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
reg_h_wr : out std_logic;
reg_h_out : in std_logic_vector (15 downto 0);
reg_h_adr : out std_logic_vector (2 downto 0); -- x,y,z
reg_z_out : in std_logic_vector (15 downto 0); -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
-- I/O register file interface
sreg_fl_in : out std_logic_vector(7 downto 0);
globint : in std_logic; -- SREG I flag
sreg_fl_wr_en : out std_logic_vector(7 downto 0); --FLAGS WRITE ENABLE SIGNALS
spl_out : in std_logic_vector(7 downto 0);
sph_out : in std_logic_vector(7 downto 0);
sp_ndown_up : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
sp_en : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
rampz_out : in std_logic_vector(7 downto 0);
-- Bit processor interface
bit_num_r_io : out std_logic_vector(2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
bitpr_io_out : in std_logic_vector(7 downto 0); -- SBI/CBI OUT
branch : out std_logic_vector(2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
bit_pr_sreg_out : in std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY)
bld_op_out : in std_logic_vector(7 downto 0); -- BLD OUT (T FLAG)
bit_test_op_out : in std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC
sbi_st_out : out std_logic;
cbi_st_out : out std_logic;
idc_bst_out : out std_logic;
idc_bset_out : out std_logic;
idc_bclr_out : out std_logic;
idc_sbic_out : out std_logic;
idc_sbis_out : out std_logic;
idc_sbrs_out : out std_logic;
idc_sbrc_out : out std_logic;
idc_brbs_out : out std_logic;
idc_brbc_out : out std_logic;
idc_reti_out : out std_logic);
end component;
component alu_avr is port(
alu_data_r_in : in std_logic_vector(7 downto 0);
alu_data_d_in : in std_logic_vector(7 downto 0);
alu_c_flag_in : in std_logic;
alu_z_flag_in : in std_logic;
-- OPERATION SIGNALS INPUTS
idc_add :in std_logic;
idc_adc :in std_logic;
idc_adiw :in std_logic;
idc_sub :in std_logic;
idc_subi :in std_logic;
idc_sbc :in std_logic;
idc_sbci :in std_logic;
idc_sbiw :in std_logic;
adiw_st : in std_logic;
sbiw_st : in std_logic;
idc_and :in std_logic;
idc_andi :in std_logic;
idc_or :in std_logic;
idc_ori :in std_logic;
idc_eor :in std_logic;
idc_com :in std_logic;
idc_neg :in std_logic;
idc_inc :in std_logic;
idc_dec :in std_logic;
idc_cp :in std_logic;
idc_cpc :in std_logic;
idc_cpi :in std_logic;
idc_cpse :in std_logic;
idc_lsr :in std_logic;
idc_ror :in std_logic;
idc_asr :in std_logic;
idc_swap :in std_logic;
-- DATA OUTPUT
alu_data_out : out std_logic_vector(7 downto 0);
-- FLAGS OUTPUT
alu_c_flag_out : out std_logic;
alu_z_flag_out : out std_logic;
alu_n_flag_out : out std_logic;
alu_v_flag_out : out std_logic;
alu_s_flag_out : out std_logic;
alu_h_flag_out : out std_logic
);
end component;
component reg_file is port (
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
reg_rd_in : in std_logic_vector (7 downto 0);
reg_rd_out : out std_logic_vector (7 downto 0);
reg_rd_adr : in std_logic_vector (4 downto 0);
reg_rr_out : out std_logic_vector (7 downto 0);
reg_rr_adr : in std_logic_vector (4 downto 0);
reg_rd_wr : in std_logic;
post_inc : in std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
pre_dec : in std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
reg_h_wr : in std_logic;
reg_h_out : out std_logic_vector (15 downto 0);
reg_h_adr : in std_logic_vector (2 downto 0); -- x,y,z
reg_z_out : out std_logic_vector (15 downto 0) -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
);
end component;
component io_reg_file is port (
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
adr : in std_logic_vector(15 downto 0);
iowe : in std_logic;
dbusout : in std_logic_vector(7 downto 0);
sreg_fl_in : in std_logic_vector(7 downto 0);
sreg_out : out std_logic_vector(7 downto 0);
sreg_fl_wr_en : in std_logic_vector (7 downto 0); --FLAGS WRITE ENABLE SIGNALS
spl_out : out std_logic_vector(7 downto 0);
sph_out : out std_logic_vector(7 downto 0);
sp_ndown_up : in std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
sp_en : in std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
rampz_out : out std_logic_vector(7 downto 0));
end component;
component bit_processor is port(
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
bit_num_r_io : in std_logic_vector(2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
dbusin : in std_logic_vector(7 downto 0); -- SBI/CBI/SBIS/SBIC IN
bitpr_io_out : out std_logic_vector(7 downto 0); -- SBI/CBI OUT
sreg_out : in std_logic_vector(7 downto 0); -- BRBS/BRBC/BLD IN
branch : in std_logic_vector(2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
bit_pr_sreg_out : out std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY)
bld_op_out : out std_logic_vector(7 downto 0); -- BLD OUT (T FLAG)
reg_rd_out : in std_logic_vector(7 downto 0); -- BST/SBRS/SBRC IN
bit_test_op_out : out std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC/BRBC/BRBS
-- Instructions and states
sbi_st : in std_logic;
cbi_st : in std_logic;
idc_bst : in std_logic;
idc_bset : in std_logic;
idc_bclr : in std_logic;
idc_sbic : in std_logic;
idc_sbis : in std_logic;
idc_sbrs : in std_logic;
idc_sbrc : in std_logic;
idc_brbs : in std_logic;
idc_brbc : in std_logic;
idc_reti : in std_logic
);
end component;
component io_adr_dec is port (
adr : in std_logic_vector(15 downto 0);
iore : in std_logic;
dbusin_ext : in std_logic_vector(7 downto 0);
dbusin_int : out std_logic_vector(7 downto 0);
spl_out : in std_logic_vector(7 downto 0);
sph_out : in std_logic_vector(7 downto 0);
sreg_out : in std_logic_vector(7 downto 0);
rampz_out : in std_logic_vector(7 downto 0));
end component;
end AVR_Core_CompPack;

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--************************************************************************************************
-- ALU(internal module) for AVR core
-- Version 1.2
-- Designed by Ruslan Lepetenok
-- Modified 02.08.2003
-- (CPC/SBC/SBCI Z-flag bug found)
-- H-flag with NEG instruction found
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity alu_avr is port(
alu_data_r_in : in std_logic_vector(7 downto 0);
alu_data_d_in : in std_logic_vector(7 downto 0);
alu_c_flag_in : in std_logic;
alu_z_flag_in : in std_logic;
-- OPERATION SIGNALS INPUTS
idc_add :in std_logic;
idc_adc :in std_logic;
idc_adiw :in std_logic;
idc_sub :in std_logic;
idc_subi :in std_logic;
idc_sbc :in std_logic;
idc_sbci :in std_logic;
idc_sbiw :in std_logic;
adiw_st : in std_logic;
sbiw_st : in std_logic;
idc_and :in std_logic;
idc_andi :in std_logic;
idc_or :in std_logic;
idc_ori :in std_logic;
idc_eor :in std_logic;
idc_com :in std_logic;
idc_neg :in std_logic;
idc_inc :in std_logic;
idc_dec :in std_logic;
idc_cp :in std_logic;
idc_cpc :in std_logic;
idc_cpi :in std_logic;
idc_cpse :in std_logic;
idc_lsr :in std_logic;
idc_ror :in std_logic;
idc_asr :in std_logic;
idc_swap :in std_logic;
-- DATA OUTPUT
alu_data_out : out std_logic_vector(7 downto 0);
-- FLAGS OUTPUT
alu_c_flag_out : out std_logic;
alu_z_flag_out : out std_logic;
alu_n_flag_out : out std_logic;
alu_v_flag_out : out std_logic;
alu_s_flag_out : out std_logic;
alu_h_flag_out : out std_logic
);
end alu_avr;
architecture rtl of alu_avr is
-- ####################################################
-- INTERNAL SIGNALS
-- ####################################################
signal alu_data_out_int : std_logic_vector (7 downto 0);
-- ALU FLAGS (INTERNAL)
signal alu_z_flag_out_int : std_logic;
signal alu_c_flag_in_int : std_logic; -- INTERNAL CARRY FLAG
signal alu_n_flag_out_int : std_logic;
signal alu_v_flag_out_int : std_logic;
signal alu_c_flag_out_int : std_logic;
-- ADDER SIGNALS --
signal adder_nadd_sub : std_logic; -- 0 -> ADD ,1 -> SUB
signal adder_v_flag_out : std_logic;
signal adder_carry : std_logic_vector(8 downto 0);
signal adder_d_in : std_logic_vector(8 downto 0);
signal adder_r_in : std_logic_vector(8 downto 0);
signal adder_out : std_logic_vector(8 downto 0);
-- NEG OPERATOR SIGNALS
signal neg_op_in : std_logic_vector(7 downto 0);
signal neg_op_carry : std_logic_vector(8 downto 0);
signal neg_op_out : std_logic_vector(8 downto 0);
-- INC, DEC OPERATOR SIGNALS
signal incdec_op_in : std_logic_vector (7 downto 0);
signal incdec_op_carry : std_logic_vector(7 downto 0);
signal incdec_op_out : std_logic_vector(7 downto 0);
signal com_op_out : std_logic_vector(7 downto 0);
signal and_op_out : std_logic_vector(7 downto 0);
signal or_op_out : std_logic_vector(7 downto 0);
signal eor_op_out : std_logic_vector(7 downto 0);
-- SHIFT SIGNALS
signal right_shift_out : std_logic_vector(7 downto 0);
-- SWAP SIGNALS
signal swap_out : std_logic_vector(7 downto 0);
begin
-- ########################################################################
-- ############### ALU
-- ########################################################################
adder_nadd_sub <=(idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or
idc_cp or idc_cpc or idc_cpi or idc_cpse ); -- '0' -> '+'; '1' -> '-'
-- SREG C FLAG (ALU INPUT)
alu_c_flag_in_int <= alu_c_flag_in and
(idc_adc or adiw_st or idc_sbc or idc_sbci or sbiw_st or
idc_cpc or
idc_ror);
-- SREG Z FLAG ()
-- alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st)) or
-- ((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st));
alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st or idc_cpc or idc_sbc or idc_sbci)) or
((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st))or
(alu_z_flag_in and alu_z_flag_out_int and(idc_cpc or idc_sbc or idc_sbci)); -- Previous value (for CPC/SBC/SBCI instructions)
-- SREG N FLAG
alu_n_flag_out <= alu_n_flag_out_int;
-- SREG V FLAG
alu_v_flag_out <= alu_v_flag_out_int;
alu_c_flag_out <= alu_c_flag_out_int;
alu_data_out <= alu_data_out_int;
-- #########################################################################################
adder_d_in <= '0'&alu_data_d_in;
adder_r_in <= '0'&alu_data_r_in;
--########################## ADDEER ###################################
adder_out(0) <= adder_d_in(0) xor adder_r_in(0) xor alu_c_flag_in_int;
adder_carry(0) <= ((adder_d_in(0) xor adder_nadd_sub) and adder_r_in(0)) or
(((adder_d_in(0) xor adder_nadd_sub) or adder_r_in(0)) and alu_c_flag_in_int);
summator:for i in 1 to 8 generate
adder_out(i) <= adder_d_in(i) xor adder_r_in(i) xor adder_carry(i-1);
adder_carry(i) <= ((adder_d_in(i) xor adder_nadd_sub) and adder_r_in(i)) or
(((adder_d_in(i) xor adder_nadd_sub) or adder_r_in(i)) and adder_carry(i-1));
end generate;
-- FLAGS FOR ADDER INSTRUCTIONS:
-- CARRY FLAG (C) -> adder_out(8)
-- HALF CARRY FLAG (H) -> adder_carry(3)
-- TOW'S COMPLEMENT OVERFLOW (V) ->
adder_v_flag_out <= (((adder_d_in(7) and adder_r_in(7) and not adder_out(7)) or
(not adder_d_in(7) and not adder_r_in(7) and adder_out(7))) and not adder_nadd_sub) or -- ADD
(((adder_d_in(7) and not adder_r_in(7) and not adder_out(7)) or
(not adder_d_in(7) and adder_r_in(7) and adder_out(7))) and adder_nadd_sub);
-- SUB
--#####################################################################
-- LOGICAL OPERATIONS FOR ONE OPERAND
--########################## NEG OPERATION ####################
neg_op_out(0) <= not alu_data_d_in(0) xor '1';
neg_op_carry(0) <= not alu_data_d_in(0) and '1';
neg_op:for i in 1 to 7 generate
neg_op_out(i) <= not alu_data_d_in(i) xor neg_op_carry(i-1);
neg_op_carry(i) <= not alu_data_d_in(i) and neg_op_carry(i-1);
end generate;
neg_op_out(8) <= neg_op_carry(7) xor '1';
neg_op_carry(8) <= neg_op_carry(7); -- ??!!
-- CARRY FLAGS FOR NEG INSTRUCTION:
-- CARRY FLAG -> neg_op_out(8)
-- HALF CARRY FLAG -> neg_op_carry(3)
-- TOW's COMPLEMENT OVERFLOW FLAG -> alu_data_d_in(7) and neg_op_carry(6)
--############################################################################
--########################## INC, DEC OPERATIONS ####################
incdec_op_out(0) <= alu_data_d_in(0) xor '1';
incdec_op_carry(0) <= alu_data_d_in(0) xor idc_dec;
inc_dec:for i in 1 to 7 generate
incdec_op_out(i) <= alu_data_d_in(i) xor incdec_op_carry(i-1);
incdec_op_carry(i) <= (alu_data_d_in(i) xor idc_dec) and incdec_op_carry(i-1);
end generate;
-- TOW's COMPLEMENT OVERFLOW FLAG -> (alu_data_d_in(7) xor idc_dec) and incdec_op_carry(6)
--####################################################################
--########################## COM OPERATION ###################################
com_op_out <= not alu_data_d_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
-- CARRY FLAG (C) -> '1'
--############################################################################
-- LOGICAL OPERATIONS FOR TWO OPERANDS
--########################## AND OPERATION ###################################
and_op_out <= alu_data_d_in and alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
--########################## OR OPERATION ###################################
or_op_out <= alu_data_d_in or alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
--########################## EOR OPERATION ###################################
eor_op_out <= alu_data_d_in xor alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
-- SHIFT OPERATIONS
-- ########################## RIGHT(LSR, ROR, ASR) #######################
right_shift_out(7) <= (idc_ror and alu_c_flag_in_int) or (idc_asr and alu_data_d_in(7)); -- right_shift_out(7)
shift_right:for i in 6 downto 0 generate
right_shift_out(i) <= alu_data_d_in(i+1);
end generate;
-- FLAGS
-- CARRY FLAG (C) -> alu_data_d_in(0)
-- NEGATIVE FLAG (N) -> right_shift_out(7)
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> N xor C (left_shift_out(7) xor alu_data_d_in(0))
-- #######################################################################
-- ################################## SWAP ###############################
swap_h:for i in 7 downto 4 generate
swap_out(i) <= alu_data_d_in(i-4);
end generate;
swap_l:for i in 3 downto 0 generate
swap_out(i) <= alu_data_d_in(i+4);
end generate;
-- #######################################################################
-- ALU OUTPUT MUX
alu_data_out_mux:for i in alu_data_out_int'range generate
alu_data_out_int(i) <= (adder_out(i) and (idc_add or idc_adc or (idc_adiw or adiw_st) or -- !!!!!
idc_sub or idc_subi or idc_sbc or idc_sbci or
(idc_sbiw or sbiw_st) or -- !!!!!
idc_cpse or idc_cp or idc_cpc or idc_cpi)) or
(neg_op_out(i) and idc_neg) or -- NEG
(incdec_op_out(i) and (idc_inc or idc_dec)) or -- INC/DEC
(com_op_out(i) and idc_com) or -- COM
(and_op_out(i) and (idc_and or idc_andi)) or -- AND/ANDI
(or_op_out(i) and (idc_or or idc_ori)) or -- OR/ORI
(eor_op_out(i) and idc_eor) or -- EOR
(right_shift_out(i) and (idc_lsr or idc_ror or idc_asr)) or -- LSR/ROR/ASR
(swap_out(i) and idc_swap); -- SWAP
end generate;
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ALU FLAGS OUTPUTS @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
alu_h_flag_out <= (adder_carry(3) and -- ADDER INSTRUCTIONS
(idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_cp or idc_cpc or idc_cpi)) or
(not neg_op_carry(3) and idc_neg); -- H-flag problem with NEG instruction fixing -- NEG
alu_s_flag_out <= alu_n_flag_out_int xor alu_v_flag_out_int;
alu_v_flag_out_int <= (adder_v_flag_out and
(idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or adiw_st or sbiw_st or idc_cp or idc_cpi or idc_cpc)) or
((alu_data_d_in(7) and neg_op_carry(6)) and idc_neg) or -- NEG
(not alu_data_d_in(7) and incdec_op_carry(6) and idc_inc) or -- INC
(alu_data_d_in(7) and incdec_op_carry(6) and idc_dec) or -- DEC
((alu_n_flag_out_int xor alu_c_flag_out_int) and (idc_lsr or idc_ror or idc_asr)); -- LSR,ROR,ASR
alu_n_flag_out_int <= alu_data_out_int(7);
alu_z_flag_out_int <= '1' when alu_data_out_int="00000000" else '0';
alu_c_flag_out_int <= (adder_out(8) and
(idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi)) or -- ADDER
(not alu_z_flag_out_int and idc_neg) or -- NEG
(alu_data_d_in(0) and (idc_lsr or idc_ror or idc_asr)) or idc_com;
-- @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
end rtl;

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--************************************************************************************************
-- Top entity for AVR core
-- Version 1.82? (Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok
-- Modified 31.08.2006
-- SLEEP and CLRWDT instructions support was added
-- BREAK instructions support was added
-- PM clock enable was added
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use Work.AVR_Core_CompPack.all;
entity AVR_Core is port(
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
-- JTAG OCD support
valid_instr : out std_logic;
insert_nop : in std_logic;
block_irq : in std_logic;
change_flow : out std_logic;
-- Program Memory
pc : out std_logic_vector(15 downto 0);
inst : in std_logic_vector(15 downto 0);
-- I/O control
adr : out std_logic_vector(15 downto 0);
iore : out std_logic;
iowe : out std_logic;
-- Data memory control
ramadr : out std_logic_vector(15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic;
-- Data paths
dbusin : in std_logic_vector(7 downto 0);
dbusout : out std_logic_vector(7 downto 0);
-- Interrupt
irqlines : in std_logic_vector(22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
--Sleep Control
sleepi : out std_logic;
irqok : out std_logic;
globint : out std_logic;
--Watchdog
wdri : out std_logic
);
end AVR_Core;
architecture Struct of avr_core is
signal dbusin_int : std_logic_vector(7 downto 0);
signal dbusout_int : std_logic_vector(7 downto 0);
signal adr_int : std_logic_vector(15 downto 0);
signal iowe_int : std_logic;
signal iore_int : std_logic;
-- SIGNALS FOR INSTRUCTION AND STATES
signal idc_add : std_logic;
signal idc_adc : std_logic;
signal idc_adiw : std_logic;
signal idc_sub : std_logic;
signal idc_subi : std_logic;
signal idc_sbc : std_logic;
signal idc_sbci : std_logic;
signal idc_sbiw : std_logic;
signal adiw_st : std_logic;
signal sbiw_st : std_logic;
signal idc_and : std_logic;
signal idc_andi : std_logic;
signal idc_or : std_logic;
signal idc_ori : std_logic;
signal idc_eor : std_logic;
signal idc_com : std_logic;
signal idc_neg : std_logic;
signal idc_inc : std_logic;
signal idc_dec : std_logic;
signal idc_cp : std_logic;
signal idc_cpc : std_logic;
signal idc_cpi : std_logic;
signal idc_cpse : std_logic;
signal idc_lsr : std_logic;
signal idc_ror : std_logic;
signal idc_asr : std_logic;
signal idc_swap : std_logic;
signal sbi_st : std_logic;
signal cbi_st : std_logic;
signal idc_bst : std_logic;
signal idc_bset : std_logic;
signal idc_bclr : std_logic;
signal idc_sbic : std_logic;
signal idc_sbis : std_logic;
signal idc_sbrs : std_logic;
signal idc_sbrc : std_logic;
signal idc_brbs : std_logic;
signal idc_brbc : std_logic;
signal idc_reti : std_logic;
signal alu_data_r_in : std_logic_vector(7 downto 0);
signal alu_data_out : std_logic_vector(7 downto 0);
signal reg_rd_in : std_logic_vector(7 downto 0);
signal reg_rd_out : std_logic_vector(7 downto 0);
signal reg_rr_out : std_logic_vector(7 downto 0);
signal reg_rd_adr : std_logic_vector(4 downto 0);
signal reg_rr_adr : std_logic_vector(4 downto 0);
signal reg_h_out : std_logic_vector(15 downto 0);
signal reg_z_out : std_logic_vector(15 downto 0);
signal reg_h_adr : std_logic_vector(2 downto 0);
signal reg_rd_wr : std_logic;
signal post_inc : std_logic;
signal pre_dec : std_logic;
signal reg_h_wr : std_logic;
signal sreg_fl_in : std_logic_vector(7 downto 0);
signal sreg_out : std_logic_vector(7 downto 0);
signal sreg_fl_wr_en : std_logic_vector(7 downto 0);
signal spl_out : std_logic_vector(7 downto 0);
signal sph_out : std_logic_vector(7 downto 0);
signal rampz_out : std_logic_vector(7 downto 0);
signal sp_ndown_up : std_logic;
signal sp_en : std_logic;
signal bit_num_r_io : std_logic_vector(2 downto 0);
signal branch : std_logic_vector(2 downto 0);
signal bitpr_io_out : std_logic_vector(7 downto 0);
signal bit_pr_sreg_out : std_logic_vector(7 downto 0);
signal sreg_flags : std_logic_vector(7 downto 0);
signal bld_op_out : std_logic_vector(7 downto 0);
signal reg_file_rd_in : std_logic_vector(7 downto 0);
signal bit_test_op_out : std_logic;
signal alu_c_flag_out : std_logic;
signal alu_z_flag_out : std_logic;
signal alu_n_flag_out : std_logic;
signal alu_v_flag_out : std_logic;
signal alu_s_flag_out : std_logic;
signal alu_h_flag_out : std_logic;
begin
pm_fetch_dec_Inst:component pm_fetch_dec port map(
-- Clock and reset
cp2 => cp2,
cp2en => cp2en,
ireset => ireset,
-- JTAG OCD support
valid_instr => valid_instr,
insert_nop => insert_nop,
block_irq => block_irq,
change_flow => change_flow,
-- Program memory
pc => pc,
inst => inst,
-- I/O control
adr => adr_int,
iore => iore_int,
iowe => iowe_int,
-- Data memory control
ramadr => ramadr,
ramre => ramre,
ramwe => ramwe,
cpuwait => cpuwait,
-- Data paths
dbusin => dbusin_int,
dbusout => dbusout_int,
-- Interrupt
irqlines => irqlines,
irqack => irqack,
irqackad => irqackad,
--Sleep
sleepi => sleepi,
irqok => irqok,
--Watchdog
wdri => wdri,
-- ALU interface(Data inputs)
alu_data_r_in => alu_data_r_in,
-- ALU interface(Instruction inputs)
idc_add_out => idc_add,
idc_adc_out => idc_adc,
idc_adiw_out => idc_adiw,
idc_sub_out => idc_sub,
idc_subi_out => idc_subi,
idc_sbc_out => idc_sbc,
idc_sbci_out => idc_sbci,
idc_sbiw_out => idc_sbiw,
adiw_st_out => adiw_st,
sbiw_st_out => sbiw_st,
idc_and_out => idc_and,
idc_andi_out => idc_andi,
idc_or_out => idc_or,
idc_ori_out => idc_ori,
idc_eor_out => idc_eor,
idc_com_out => idc_com,
idc_neg_out => idc_neg,
idc_inc_out => idc_inc,
idc_dec_out => idc_dec,
idc_cp_out => idc_cp,
idc_cpc_out => idc_cpc,
idc_cpi_out => idc_cpi,
idc_cpse_out => idc_cpse,
idc_lsr_out => idc_lsr,
idc_ror_out => idc_ror,
idc_asr_out => idc_asr,
idc_swap_out => idc_swap,
-- ALU interface(Data output)
alu_data_out => alu_data_out,
-- ALU interface(Flag outputs)
alu_c_flag_out => alu_c_flag_out,
alu_z_flag_out => alu_z_flag_out,
alu_n_flag_out => alu_n_flag_out,
alu_v_flag_out => alu_v_flag_out,
alu_s_flag_out => alu_s_flag_out,
alu_h_flag_out => alu_h_flag_out,
-- General purpose register file interface
reg_rd_in => reg_rd_in,
reg_rd_out => reg_rd_out,
reg_rd_adr => reg_rd_adr,
reg_rr_out => reg_rr_out,
reg_rr_adr => reg_rr_adr,
reg_rd_wr => reg_rd_wr,
post_inc => post_inc,
pre_dec => pre_dec,
reg_h_wr => reg_h_wr,
reg_h_out => reg_h_out,
reg_h_adr => reg_h_adr,
reg_z_out => reg_z_out,
-- I/O register file interface
sreg_fl_in => sreg_fl_in, --??
globint => sreg_out(7), -- SREG I flag
sreg_fl_wr_en => sreg_fl_wr_en,
spl_out => spl_out,
sph_out => sph_out,
sp_ndown_up => sp_ndown_up,
sp_en => sp_en,
rampz_out => rampz_out,
-- Bit processor interface
bit_num_r_io => bit_num_r_io,
bitpr_io_out => bitpr_io_out,
branch => branch,
bit_pr_sreg_out => bit_pr_sreg_out,
bld_op_out => bld_op_out,
bit_test_op_out => bit_test_op_out,
sbi_st_out => sbi_st,
cbi_st_out => cbi_st,
idc_bst_out => idc_bst,
idc_bset_out => idc_bset,
idc_bclr_out => idc_bclr,
idc_sbic_out => idc_sbic,
idc_sbis_out => idc_sbis,
idc_sbrs_out => idc_sbrs,
idc_sbrc_out => idc_sbrc,
idc_brbs_out => idc_brbs,
idc_brbc_out => idc_brbc,
idc_reti_out => idc_reti);
GPRF_Inst:component reg_file port map (
--Clock and reset
cp2 => cp2,
cp2en => cp2en,
ireset => ireset,
reg_rd_in => reg_rd_in,
reg_rd_out => reg_rd_out,
reg_rd_adr => reg_rd_adr,
reg_rr_out => reg_rr_out,
reg_rr_adr => reg_rr_adr,
reg_rd_wr => reg_rd_wr,
post_inc => post_inc,
pre_dec => pre_dec,
reg_h_wr => reg_h_wr,
reg_h_out => reg_h_out,
reg_h_adr => reg_h_adr,
reg_z_out => reg_z_out);
BP_Inst:component bit_processor port map(
--Clock and reset
cp2 => cp2,
cp2en => cp2en,
ireset => ireset,
bit_num_r_io => bit_num_r_io,
dbusin => dbusin_int,
bitpr_io_out => bitpr_io_out,
sreg_out => sreg_out,
branch => branch,
bit_pr_sreg_out => bit_pr_sreg_out,
bld_op_out => bld_op_out,
reg_rd_out => reg_rd_out,
bit_test_op_out => bit_test_op_out,
-- Instructions and states
sbi_st => sbi_st,
cbi_st => cbi_st,
idc_bst => idc_bst,
idc_bset => idc_bset,
idc_bclr => idc_bclr,
idc_sbic => idc_sbic,
idc_sbis => idc_sbis,
idc_sbrs => idc_sbrs,
idc_sbrc => idc_sbrc,
idc_brbs => idc_brbs,
idc_brbc => idc_brbc,
idc_reti => idc_reti);
io_dec_Inst:component io_adr_dec port map (
adr => adr_int,
iore => iore_int,
dbusin_int => dbusin_int, -- LOCAL DATA BUS OUTPUT
dbusin_ext => dbusin, -- EXTERNAL DATA BUS INPUT
spl_out => spl_out,
sph_out => sph_out,
sreg_out => sreg_out,
rampz_out => rampz_out
);
IORegs_Inst: component io_reg_file port map(
--Clock and reset
cp2 => cp2,
cp2en => cp2en,
ireset => ireset,
adr => adr_int,
iowe => iowe_int,
dbusout => dbusout_int,
sreg_fl_in => sreg_fl_in,
sreg_out => sreg_out,
sreg_fl_wr_en => sreg_fl_wr_en,
spl_out => spl_out,
sph_out => sph_out,
sp_ndown_up => sp_ndown_up,
sp_en => sp_en,
rampz_out => rampz_out);
ALU_Inst:component alu_avr port map(
-- Data inputs
alu_data_r_in => alu_data_r_in,
alu_data_d_in => reg_rd_out,
alu_c_flag_in => sreg_out(0),
alu_z_flag_in => sreg_out(1),
-- Instructions and states
idc_add => idc_add,
idc_adc => idc_adc,
idc_adiw => idc_adiw,
idc_sub => idc_sub,
idc_subi => idc_subi,
idc_sbc => idc_sbc,
idc_sbci => idc_sbci,
idc_sbiw => idc_sbiw,
adiw_st => adiw_st,
sbiw_st => sbiw_st,
idc_and => idc_and,
idc_andi => idc_andi,
idc_or => idc_or,
idc_ori => idc_ori,
idc_eor => idc_eor,
idc_com => idc_com,
idc_neg => idc_neg,
idc_inc => idc_inc,
idc_dec => idc_dec,
idc_cp => idc_cp,
idc_cpc => idc_cpc,
idc_cpi => idc_cpi,
idc_cpse => idc_cpse,
idc_lsr => idc_lsr,
idc_ror => idc_ror,
idc_asr => idc_asr,
idc_swap => idc_swap,
-- Data outputs
alu_data_out => alu_data_out,
-- Flag outputs
alu_c_flag_out => alu_c_flag_out,
alu_z_flag_out => alu_z_flag_out,
alu_n_flag_out => alu_n_flag_out,
alu_v_flag_out => alu_v_flag_out,
alu_s_flag_out => alu_s_flag_out,
alu_h_flag_out => alu_h_flag_out);
-- Outputs
adr <= adr_int;
iowe <= iowe_int;
iore <= iore_int;
dbusout <= dbusout_int;
-- Sleep support
globint <= sreg_out(7); -- I flag
end Struct;

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--************************************************************************************************
-- "Bit processor" for AVR core
-- Version 1.3(Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok
-- Modified 29.08.2003
-- Unused inputs(sreg_bit_num[2..0],idc_sbi,idc_cbi,idc_bld) was removed.
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity bit_processor is port(
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
bit_num_r_io : in std_logic_vector(2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
dbusin : in std_logic_vector(7 downto 0); -- SBI/CBI/SBIS/SBIC IN
bitpr_io_out : out std_logic_vector(7 downto 0); -- SBI/CBI OUT
sreg_out : in std_logic_vector(7 downto 0); -- BRBS/BRBC/BLD IN
branch : in std_logic_vector(2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
bit_pr_sreg_out : out std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY)
bld_op_out : out std_logic_vector(7 downto 0); -- BLD OUT (T FLAG)
reg_rd_out : in std_logic_vector(7 downto 0); -- BST/SBRS/SBRC IN
bit_test_op_out : out std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC/BRBC/BRBS
-- Instructions and states
sbi_st : in std_logic;
cbi_st : in std_logic;
idc_bst : in std_logic;
idc_bset : in std_logic;
idc_bclr : in std_logic;
idc_sbic : in std_logic;
idc_sbis : in std_logic;
idc_sbrs : in std_logic;
idc_sbrc : in std_logic;
idc_brbs : in std_logic;
idc_brbc : in std_logic;
idc_reti : in std_logic
);
end bit_processor;
architecture RTL of bit_processor is
signal sreg_t_flag : std_logic; -- FOR BLD INSTRUCTION
signal temp_in_data : std_logic_vector(7 downto 0);
signal sreg_t_temp : std_logic_vector(7 downto 0);
signal bit_num_decode : std_logic_vector(7 downto 0);
signal bit_pr_sreg_out_int : std_logic_vector(7 downto 0);
-- SBIS/SBIC/SBRS/SBRC SIGNALS
signal bit_test_in : std_logic_vector(7 downto 0);
signal bit_test_mux_out : std_logic_vector(7 downto 0);
-- BRBS/BRBC SIGNALS
signal branch_decode : std_logic_vector(7 downto 0);
signal branch_mux : std_logic_vector(7 downto 0);
begin
sreg_t_flag <= sreg_out(6);
-- SBI/CBI STORE REGISTER
sbi_cbi:process(cp2,ireset)
begin
if ireset='0' then
temp_in_data <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
temp_in_data <= dbusin;
end if;
end if;
end process;
sbi_cbi_logic:for i in dbusin'range generate
bitpr_io_out(i) <= '1' when (sbi_st='1' and bit_num_decode(i)='1') else -- SBI
'0' when (cbi_st='1' and bit_num_decode(i)='1') else -- CBI
temp_in_data(i); -- ???
end generate;
-- ########################################################################################
-- BST PART (LOAD T BIT OF SREG FROM THE GENERAL PURPOSE REGISTER)
bit_num_decode_logic:for i in bit_num_decode'range generate
bit_num_decode(i) <= '1' when (i=bit_num_r_io) else '0';
end generate;
sreg_t_temp(0) <= reg_rd_out(0) when bit_num_decode(0)='1' else '0';
bld_logic:for i in 1 to 7 generate
sreg_t_temp(i)<= reg_rd_out(i) when bit_num_decode(i)='1' else sreg_t_temp(i-1);
end generate;
-- BLD LOGIC
bld_inst:for i in reg_rd_out'range generate
bld_op_out(i) <= sreg_t_flag when (i=bit_num_r_io) else reg_rd_out(i);
end generate;
-- ########################################################################################
-- BCLR/BSET/BST/RETI LOGIC
bclr_bset_logic:for i in 0 to 6 generate
bit_pr_sreg_out_int(i) <= (idc_bset and not reg_rd_out(i)) or (not idc_bclr and reg_rd_out(i));
end generate;
-- SREG REGISTER BIT 7 - INTERRUPT ENABLE FLAG
bit_pr_sreg_out_int(7) <= (idc_bset and not reg_rd_out(7)) or (not idc_bclr and reg_rd_out(7)) or idc_reti;
bit_pr_sreg_out <= bit_pr_sreg_out_int(7)&sreg_t_temp(7)&bit_pr_sreg_out_int(5 downto 0) when (idc_bst='1')
else bit_pr_sreg_out_int;
-- SBIC/SBIS/SBRS/SBRC LOGIC
bit_test_in <= dbusin when (idc_sbis='1' or idc_sbic='1') else reg_rd_out;
bit_test_mux_out(0) <= bit_test_in(0) when bit_num_decode(0)='1' else '0';
it_test_mux:for i in 1 to 7 generate
bit_test_mux_out(i)<= bit_test_in(i) when bit_num_decode(i)='1' else bit_test_mux_out(i-1);
end generate;
bit_test_op_out <= (bit_test_mux_out(7) and (idc_sbis or idc_sbrs)) or
(not bit_test_mux_out(7) and (idc_sbic or idc_sbrc)) or
(branch_mux(7) and idc_brbs) or
(not branch_mux(7) and idc_brbc);
-- BRBS/BRBC LOGIC
branch_decode_logic:for i in branch_decode'range generate
branch_decode(i) <= '1' when (i=branch) else '0';
end generate;
branch_mux(0) <= sreg_out(0) when branch_decode(0)='1' else '0';
branch_mux_logic:for i in 1 to 7 generate
branch_mux(i)<= sreg_out(i) when branch_decode(i)='1' else branch_mux(i-1);
end generate;
end RTL;

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--************************************************************************************************
-- Internal I/O registers decoder/multiplexer for the AVR core
-- Version 1.11
-- Modified 05.06.2003
-- Designed by Ruslan Lepetenok
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
entity io_adr_dec is port (
adr : in std_logic_vector(15 downto 0);
iore : in std_logic;
dbusin_ext : in std_logic_vector(7 downto 0);
dbusin_int : out std_logic_vector(7 downto 0);
spl_out : in std_logic_vector(7 downto 0);
sph_out : in std_logic_vector(7 downto 0);
sreg_out : in std_logic_vector(7 downto 0);
rampz_out : in std_logic_vector(7 downto 0));
end io_adr_dec;
architecture RTL of io_adr_dec is
begin
dbusin_int <= spl_out when (adr=SPL_Address and iore='1') else
sph_out when (adr=SPH_Address and iore='1') else
sreg_out when (adr=SREG_Address and iore='1') else
rampz_out when (adr=RAMPZ_Address and iore='1') else
dbusin_ext;
end RTL;

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--************************************************************************************************
-- Internal I/O registers (implemented inside the core) decoder/multiplexer
-- for AVR core
-- Version 1.3 (Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok
-- Modified 22.04.2004
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity io_reg_file is port (
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
adr : in std_logic_vector(15 downto 0);
iowe : in std_logic;
dbusout : in std_logic_vector(7 downto 0);
sreg_fl_in : in std_logic_vector(7 downto 0);
sreg_out : out std_logic_vector(7 downto 0);
sreg_fl_wr_en : in std_logic_vector (7 downto 0); --FLAGS WRITE ENABLE SIGNALS
spl_out : out std_logic_vector(7 downto 0);
sph_out : out std_logic_vector(7 downto 0);
sp_ndown_up : in std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
sp_en : in std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
rampz_out : out std_logic_vector(7 downto 0));
end io_reg_file;
architecture rtl of io_reg_file is
signal sreg : std_logic_vector(7 downto 0);
signal sph : std_logic_vector(7 downto 0);
signal spl : std_logic_vector(7 downto 0);
signal rampz : std_logic_vector(7 downto 0);
signal sp_int : std_logic_vector(15 downto 0);
signal sp_intp : std_logic_vector(15 downto 0);
signal sp_intm : std_logic_vector(15 downto 0);
signal sp_res : std_logic_vector(15 downto 0);
begin
sreg_write:process(cp2,ireset)
begin
if ireset='0' then
sreg <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
for i in sreg'range loop
if (sreg_fl_wr_en(i)='1' or (adr=SREG_Address and iowe='1')) then -- CLOCK ENABLE
if iowe='1' then
sreg(i) <= dbusout(i); -- FROM THE INTERNAL DATA BUS
else
sreg(i) <= sreg_fl_in(i); -- FROM ALU FLAGS
end if;
end if;
end loop;
end if;
end if;
end process;
sreg_out <= sreg;
sp_intp<=(sph&spl)+1;
sp_intm<=(sph&spl)-1;
sp_res<= sp_intm when sp_ndown_up='0' else sp_intp;
spl_write:process(cp2,ireset)
begin
if ireset='0' then
spl <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (sp_en='1' or (adr=SPL_Address and iowe='1')) then -- CLOCK ENABLE
if iowe='1' then
spl <= dbusout; -- FROM THE INTERNAL DATA BUS
else
spl <= sp_res(7 downto 0); -- FROM SPL BUS
end if;
end if;
end if;
end process;
spl_out <= spl;
sph_write:process(cp2,ireset)
begin
if ireset='0' then
sph <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (sp_en='1' or (adr=SPH_Address and iowe='1')) then -- CLOCK ENABLE
if iowe='1' then
sph <= dbusout; -- FROM THE INTERNAL DATA BUS
else
sph <= sp_res(15 downto 8); -- FROM SPH BUS
end if;
end if;
end if;
end process;
sph_out <= sph;
rampz_write:process(cp2,ireset)
begin
if ireset='0' then
rampz <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (adr=RAMPZ_Address and iowe='1') then -- CLOCK ENABLE
rampz <= dbusout; -- FROM THE INTERNAL DATA BUS
end if;
end if;
end process;
rampz_out <= rampz;
end rtl;

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--**********************************************************************************************
-- General purpose register file for the AVR Core
-- Version 1.4 (Special version for the JTAG OCD)
-- Modified 22.04.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
entity reg_file is port (
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
reg_rd_in : in std_logic_vector(7 downto 0);
reg_rd_out : out std_logic_vector(7 downto 0);
reg_rd_adr : in std_logic_vector(4 downto 0);
reg_rr_out : out std_logic_vector(7 downto 0);
reg_rr_adr : in std_logic_vector(4 downto 0);
reg_rd_wr : in std_logic;
post_inc : in std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
pre_dec : in std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
reg_h_wr : in std_logic;
reg_h_out : out std_logic_vector(15 downto 0);
reg_h_adr : in std_logic_vector(2 downto 0); -- x,y,z
reg_z_out : out std_logic_vector(15 downto 0) -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
);
end reg_file;
architecture RTL of reg_file is
type register_file_type is array(0 to 25) of std_logic_vector(7 downto 0);
type register_mux_type is array(0 to 31) of std_logic_vector(7 downto 0);
signal register_file : register_file_type;
signal r26h : std_logic_vector(7 downto 0);
signal r27h : std_logic_vector(7 downto 0);
signal r28h : std_logic_vector(7 downto 0);
signal r29h : std_logic_vector(7 downto 0);
signal r30h : std_logic_vector(7 downto 0);
signal r31h : std_logic_vector(7 downto 0);
signal register_wr_en : std_logic_vector(31 downto 0);
signal sg_rd_decode : std_logic_vector (31 downto 0);
signal sg_rr_decode : std_logic_vector (31 downto 0);
signal sg_tmp_rd_data : register_mux_type;
signal sg_tmp_rr_data : register_mux_type;
signal sg_adr16_postinc : std_logic_vector (15 downto 0);
signal sg_adr16_predec : std_logic_vector (15 downto 0);
signal reg_h_in : std_logic_vector (15 downto 0);
signal sg_tmp_h_data : std_logic_vector (15 downto 0);
begin
write_decode: for i in 0 to 31 generate
register_wr_en(i) <= '1' when (i=reg_rd_adr and reg_rd_wr='1') else '0';
end generate;
rd_mux_decode: for i in 0 to 31 generate
sg_rd_decode(i) <= '1' when (reg_rd_adr=i) else '0';
end generate;
rr_mux_decode: for i in 0 to 31 generate
sg_rr_decode(i) <= '1' when (reg_rr_adr=i) else '0';
end generate;
reg_z_out <= r31h&r30h; -- R31:R30 OUTPUT FOR LPM/ELPM INSTRUCTIONS
sg_tmp_rd_data(0) <= register_file(0) when sg_rd_decode(0)='1' else (others=>'0');
read_rd_mux: for i in 1 to 25 generate
sg_tmp_rd_data(i) <= register_file(i) when sg_rd_decode(i)='1' else sg_tmp_rd_data(i-1);
end generate;
sg_tmp_rd_data(26) <= r26h when sg_rd_decode(26)='1' else sg_tmp_rd_data(25);
sg_tmp_rd_data(27) <= r27h when sg_rd_decode(27)='1' else sg_tmp_rd_data(26);
sg_tmp_rd_data(28) <= r28h when sg_rd_decode(28)='1' else sg_tmp_rd_data(27);
sg_tmp_rd_data(29) <= r29h when sg_rd_decode(29)='1' else sg_tmp_rd_data(28);
sg_tmp_rd_data(30) <= r30h when sg_rd_decode(30)='1' else sg_tmp_rd_data(29);
sg_tmp_rd_data(31) <= r31h when sg_rd_decode(31)='1' else sg_tmp_rd_data(30);
reg_rd_out <= sg_tmp_rd_data(31);
sg_tmp_rr_data(0) <= register_file(0) when sg_rr_decode(0)='1' else (others=>'0');
read_rr_mux: for i in 1 to 25 generate
sg_tmp_rr_data(i) <= register_file(i) when sg_rr_decode(i)='1' else sg_tmp_rr_data(i-1);
end generate;
sg_tmp_rr_data(26) <= r26h when sg_rr_decode(26)='1' else sg_tmp_rr_data(25);
sg_tmp_rr_data(27) <= r27h when sg_rr_decode(27)='1' else sg_tmp_rr_data(26);
sg_tmp_rr_data(28) <= r28h when sg_rr_decode(28)='1' else sg_tmp_rr_data(27);
sg_tmp_rr_data(29) <= r29h when sg_rr_decode(29)='1' else sg_tmp_rr_data(28);
sg_tmp_rr_data(30) <= r30h when sg_rr_decode(30)='1' else sg_tmp_rr_data(29);
sg_tmp_rr_data(31) <= r31h when sg_rr_decode(31)='1' else sg_tmp_rr_data(30);
reg_rr_out <= sg_tmp_rr_data(31);
h_dat_mux_l:for i in 0 to 7 generate
sg_tmp_h_data(i) <= (r26h(i) and reg_h_adr(0)) or (r28h(i) and reg_h_adr(1)) or (r30h(i) and reg_h_adr(2));
end generate;
h_dat_mux_h:for i in 8 to 15 generate
sg_tmp_h_data(i) <= (r27h(i-8) and reg_h_adr(0)) or (r29h(i-8) and reg_h_adr(1)) or (r31h(i-8) and reg_h_adr(2));
end generate;
sg_adr16_postinc <= sg_tmp_h_data +1;
sg_adr16_predec <= sg_tmp_h_data -1;
-- OUTPUT TO THE ADDRESS BUS
reg_h_out <= sg_adr16_predec when (pre_dec='1') else -- PREDECREMENT
sg_tmp_h_data; -- NO PREDECREMENT
-- TO REGISTERS
reg_h_in <= sg_adr16_postinc when (post_inc='1') else -- POST INC
sg_adr16_predec; -- PRE DEC
-- Register file with global reset (for simulation)
RegFileWithRst:if CResetRegFile generate
R0_R25:process(cp2,ireset)
begin
if ireset='0' then
for i in 0 to 25 loop
register_file(i) <= (others =>'0');
end loop;
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
for i in 0 to 25 loop
if register_wr_en(i)='1' then
register_file(i) <= reg_rd_in;
end if;
end loop;
end if;
end if;
end process;
-- R26 (LOW)
R26:process(cp2,ireset)
begin
if ireset='0' then
r26h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(26)='1' then
r26h <= reg_rd_in;
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
r26h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R27 (HIGH)
R27:process(cp2,ireset)
begin
if ireset='0' then
r27h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(27)='1' then
r27h <= reg_rd_in;
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
r27h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
-- R28 (LOW)
R28:process(cp2,ireset)
begin
if ireset='0' then
r28h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(28)='1' then
r28h <= reg_rd_in;
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
r28h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R29 (HIGH)
R29:process(cp2,ireset)
begin
if ireset='0' then
r29h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(29)='1' then
r29h <= reg_rd_in;
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
r29h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
-- R30 (LOW)
R30:process(cp2,ireset)
begin
if ireset='0' then
r30h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(30)='1' then
r30h <= reg_rd_in;
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
r30h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R31 (HIGH)
R31:process(cp2,ireset)
begin
if ireset='0' then
r31h <= (others =>'0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(31)='1' then
r31h <= reg_rd_in;
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
r31h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
end generate;
-- Register file without global reset (for synthesis)
RegFileWithoutRst:if not CResetRegFile generate
R0_R25:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
for i in 0 to 25 loop
if register_wr_en(i)='1' then
register_file(i) <= reg_rd_in;
end if;
end loop;
end if;
end if;
end process;
-- R26 (LOW)
R26:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(26)='1' then
r26h <= reg_rd_in;
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
r26h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R27 (HIGH)
R27:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(27)='1' then
r27h <= reg_rd_in;
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
r27h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
-- R28 (LOW)
R28:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(28)='1' then
r28h <= reg_rd_in;
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
r28h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R29 (HIGH)
R29:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(29)='1' then
r29h <= reg_rd_in;
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
r29h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
-- R30 (LOW)
R30:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(30)='1' then
r30h <= reg_rd_in;
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
r30h <= reg_h_in(7 downto 0);
end if;
end if;
end if;
end process;
-- R31 (HIGH)
R31:process(cp2)
begin
if (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock enable
if register_wr_en(31)='1' then
r31h <= reg_rd_in;
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
r31h <= reg_h_in(15 downto 8);
end if;
end if;
end if;
end process;
end generate;
end RTL;

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--**********************************************************************************************
-- Frequency divider for AVR uC (40 MHz -> 4 MHz or 40 MHz -> 20 MHz)
-- Version 1.52(Dust Inc version)
-- Modified 16.01.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity FrqDiv is port(
clk_in : in std_logic;
clk_out : out std_logic
);
end FrqDiv;
architecture RTL of FrqDiv is
signal DivCnt : std_logic_vector(3 downto 0);
signal clk_out_int : std_logic;
constant Div2 : boolean := TRUE;
begin
-- Must be sequentially encoded
DivideBy10:if not Div2 generate
Gen:process(clk_in)
begin
if(clk_in='1' and clk_in'event) then -- Clock
if(DivCnt=x"4") then DivCnt <= x"0";
else DivCnt <= DivCnt + 1;
end if;
if(DivCnt=x"4") then clk_out_int <= not clk_out_int;
end if;
end if;
end process;
end generate;
DivideBy10:if Div2 generate
Gen:process(clk_in)
begin
if(clk_in='1' and clk_in'event) then -- Clock
clk_out_int <= not clk_out_int;
end if;
end process;
end generate;
clk_out <= clk_out_int;
end RTL;

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--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGCompPack is
component OCDProgTCK is port(
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From/To cp2 clock domain("Flash" programmer)
FlEEPrgAdr : out std_logic_vector(15 downto 0);
FlPrgRdData : in std_logic_vector(15 downto 0);
EEPrgRdData : in std_logic_vector(7 downto 0);
FlEEPrgWrData : out std_logic_vector(15 downto 0);
ChipEraseStart : out std_logic;
ChipEraseDone : in std_logic;
ProgEnable : out std_logic;
FlWrMStart : out std_logic; -- Multiple
FlWrSStart : out std_logic; -- Single
FlRdMStart : out std_logic; -- Multiple
FlRdSStart : out std_logic; -- Single
EEWrStart : out std_logic;
EERdStart : out std_logic;
TAPCtrlTLR : out std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- CPU reset
jtag_rst : out std_logic
);
end component;
component OCDProgcp2 is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- From/To TCK clock domain("Flash" programmer)
FlEEPrgAdr : in std_logic_vector(15 downto 0);
FlPrgRdData : out std_logic_vector(15 downto 0);
EEPrgRdData : out std_logic_vector(7 downto 0);
FlEEPrgWrData : in std_logic_vector(15 downto 0);
ChipEraseStart : in std_logic;
ChipEraseDone : out std_logic;
ProgEnable : in std_logic;
FlWrMStart : in std_logic; -- Multiple
FlWrSStart : in std_logic; -- Single
FlRdMStart : in std_logic; -- Multiple
FlRdSStart : in std_logic; -- Single
EEWrStart : in std_logic;
EERdStart : in std_logic;
TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic
);
end component;
component Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync1b_TCK is port(
TCK : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync16b_TCK is port(
TCK : in std_logic;
DIn : in std_logic_vector(15 downto 0);
DOut : out std_logic_vector(15 downto 0)
);
end component;
end JTAGCompPack;

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--**********************************************************************************************
-- Fuses/Lock bits and Calibration bytes for JTAG "Flash" Programmer
-- Version 0.11
-- Modified 19.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGDataPack is
-- Extended Fuse Byte
constant C_ExtFuseByte : std_logic_vector(7 downto 0) := x"FD"; -- x"00"
-- Fuse High Byte
constant C_HighFuseByte : std_logic_vector(7 downto 0) := x"19"; -- x"01"
-- Fuse Low Byte
constant C_LowFuseByte : std_logic_vector(7 downto 0) := x"E3"; -- x"00"
-- Lock bits
constant C_LockBits : std_logic_vector(7 downto 0) := x"FF";
-- Signature Bytes(3 Bytes)
constant C_SignByte1 : std_logic_vector(7 downto 0) := x"1E";
constant C_SignByte2 : std_logic_vector(7 downto 0) := x"97";
constant C_SignByte3 : std_logic_vector(7 downto 0) := x"02";
-- Calibration Bytes(4 Bytes)
constant C_CalibrByte1 : std_logic_vector(7 downto 0) := x"C1";
constant C_CalibrByte2 : std_logic_vector(7 downto 0) := x"C2";
constant C_CalibrByte3 : std_logic_vector(7 downto 0) := x"C3";
constant C_CalibrByte4 : std_logic_vector(7 downto 0) := x"C4";
end JTAGDataPack;

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--**********************************************************************************************
-- Top entity for "Flash" programmer (for AVR Core)
-- Version 0.3A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.JTAGCompPack.all;
entity JTAGOCDPrgTop is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic;
-- CPU reset
jtag_rst : out std_logic
);
end JTAGOCDPrgTop;
architecture RTL of JTAGOCDPrgTop is
-- From TCK clock domain to cp2 clock domain with resynchronization
signal ChipEraseStart_TCK : std_logic;
signal ChipEraseStart_cp2 : std_logic;
signal ProgEnable_TCK : std_logic;
signal ProgEnable_cp2 : std_logic;
signal FlWrMStart_TCK : std_logic;
signal FlWrMStart_cp2 : std_logic;
signal FlWrSStart_TCK : std_logic;
signal FlWrSStart_cp2 : std_logic;
signal FlRdMStart_TCK : std_logic;
signal FlRdMStart_cp2 : std_logic;
signal FlRdSStart_TCK : std_logic;
signal FlRdSStart_cp2 : std_logic;
signal EEWrStart_TCK : std_logic;
signal EEWrStart_cp2 : std_logic;
signal EERdStart_TCK : std_logic;
signal EERdStart_cp2 : std_logic;
signal TAPCtrlTLR_TCK : std_logic;
signal TAPCtrlTLR_cp2 : std_logic;
-- From TCK clock domain to cp2 clock domain without resynchronization
signal FlEEPrgAdr_TCK : std_logic_vector(15 downto 0); -- Flash/EEPROM Address
signal FlEEPrgWrData_TCK : std_logic_vector(15 downto 0); -- Flash/EEPROM Data for write
-- From cp2 clock domain to TCK clock domain with resynchronization
signal ChipEraseDone_cp2 : std_logic;
signal ChipEraseDone_TCK : std_logic;
-- From cp2 clock domain to TCK clock domain without resynchronization
signal FlPrgRdData_cp2 : std_logic_vector(15 downto 0); -- Flash Read Data
signal EEPrgRdData_cp2 : std_logic_vector(7 downto 0); -- EEPROM Read Data
begin
OCDProgTCK_Inst:component OCDProgTCK port map(
-- JTAG related inputs/outputs
TRSTn => TRSTn,
TMS => TMS,
TCK => TCK,
TDI => TDI,
TDO => TDO,
TDO_OE => TDO_OE,
-- From/To cp2 clock domain("Flash" programmer)
FlEEPrgAdr => FlEEPrgAdr_TCK,
FlPrgRdData => FlPrgRdData_cp2,
EEPrgRdData => EEPrgRdData_cp2,
FlEEPrgWrData => FlEEPrgWrData_TCK,
ChipEraseStart => ChipEraseStart_TCK,
ChipEraseDone => ChipEraseDone_TCK,
ProgEnable => ProgEnable_TCK,
FlWrMStart => FlWrMStart_TCK,
FlWrSStart => FlWrSStart_TCK,
FlRdMStart => FlRdMStart_TCK,
FlRdSStart => FlRdSStart_TCK,
EEWrStart => EEWrStart_TCK,
EERdStart => EERdStart_TCK,
TAPCtrlTLR => TAPCtrlTLR_TCK,
-- CPU reset
jtag_rst => jtag_rst
);
OCDProgcp2_Inst:component OCDProgcp2 port map(
-- AVR Control
ireset => ireset,
cp2 => cp2,
-- From/To TCK clock domain("Flash" programmer)
FlEEPrgAdr => FlEEPrgAdr_TCK,
FlPrgRdData => FlPrgRdData_cp2,
EEPrgRdData => EEPrgRdData_cp2,
FlEEPrgWrData => FlEEPrgWrData_TCK,
ChipEraseStart => ChipEraseStart_cp2,
ChipEraseDone => ChipEraseDone_cp2,
ProgEnable => ProgEnable_cp2,
FlWrMStart => FlWrMStart_cp2,
FlWrSStart => FlWrSStart_cp2,
FlRdMStart => FlRdMStart_cp2,
FlRdSStart => FlRdSStart_cp2,
EEWrStart => EEWrStart_cp2,
EERdStart => EERdStart_cp2,
TAPCtrlTLR => TAPCtrlTLR_cp2,
-- From the core
PC => PC,
-- To the PM("Flash")
pm_adr => pm_adr,
pm_h_we => pm_h_we,
pm_l_we => pm_l_we,
pm_dout => pm_dout,
pm_din => pm_din,
-- To the "EEPROM"
EEPrgSel => EEPrgSel,
EEAdr => EEAdr,
EEWrData => EEWrData,
EERdData => EERdData,
EEWr => EEWr
);
-- Resynchronizers (TCK to cp2)
ChipEraseStart_Resync_Inst:component Resync1b_cp2 port map(
cp2 => cp2,
DIn => ChipEraseStart_TCK,
DOut => ChipEraseStart_cp2
);
ProgEnable_Resync_Inst:component Resync1b_cp2 port map(
cp2 => cp2,
DIn => ProgEnable_TCK,
DOut => ProgEnable_cp2
);
FlWrMStart_Resync_Inst:component Resync1b_cp2 port map(
cp2 => cp2,
DIn => FlWrMStart_TCK,
DOut => FlWrMStart_cp2
);
FlWrSStart_Resync_Inst:component Resync1b_cp2 port map(
cp2 => cp2,
DIn => FlWrSStart_TCK,
DOut => FlWrSStart_cp2
);
FlRdMStart_Resync_Inst:component Resync1b_cp2 port map(
cp2 => cp2,
DIn => FlRdMStart_TCK,
DOut => FlRdMStart_cp2
);
FlRdSStart_Resync_Inst:component Resync1b_cp2 port map(
cp2 => cp2,
DIn => FlRdSStart_TCK,
DOut => FlRdSStart_cp2
);
EEWrStart_Resync_Inst:component Resync1b_cp2 port map(
cp2 => cp2,
DIn => EEWrStart_TCK,
DOut => EEWrStart_cp2
);
EERdStart_Resync_Inst:component Resync1b_cp2 port map(
cp2 => cp2,
DIn => EERdStart_TCK,
DOut => EERdStart_cp2
);
TAPCtrlTLR_Resync_Inst:component Resync1b_cp2 port map(
cp2 => cp2,
DIn => TAPCtrlTLR_TCK,
DOut => TAPCtrlTLR_cp2
);
-- Resynchronizers (cp2 to TCK)
ChipEraseDone_Resync_Inst:component Resync1b_TCK port map(
TCK => TCK,
DIn => ChipEraseDone_cp2,
DOut => ChipEraseDone_TCK
);
end RTL;

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--**********************************************************************************************
-- Constants for OCD and "Flash" controller for AVR Core
-- Version 0.31
-- Modified 04.06.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGPack is
constant CInstrLength : positive := 4;
-- JTAG instructions
constant C_BYPASS : std_logic_vector(CInstrLength-1 downto 0) := x"F";
constant C_SAMPLE_PRELOAD : std_logic_vector(CInstrLength-1 downto 0) := x"2";
constant C_EXTEST : std_logic_vector(CInstrLength-1 downto 0) := x"0";
constant C_IDCODE : std_logic_vector(CInstrLength-1 downto 0) := x"1";
constant C_AVR_RESET : std_logic_vector(CInstrLength-1 downto 0) := x"C";
-- Program
constant C_PROG_ENABLE : std_logic_vector(CInstrLength-1 downto 0) := x"4";
constant C_PROG_COMMANDS : std_logic_vector(CInstrLength-1 downto 0) := x"5";
constant C_PROG_PAGELOAD : std_logic_vector(CInstrLength-1 downto 0) := x"6";
constant C_PROG_PAGEREAD : std_logic_vector(CInstrLength-1 downto 0) := x"7";
-- OCD (Private)
constant C_FORCE_BREAK : std_logic_vector(CInstrLength-1 downto 0) := x"8";
constant C_RUN : std_logic_vector(CInstrLength-1 downto 0) := x"9";
constant C_EX_INST : std_logic_vector(CInstrLength-1 downto 0) := x"A";
constant C_OCD_ACCESS : std_logic_vector(CInstrLength-1 downto 0) := x"B";
constant C_UNUSED_3 : std_logic_vector(CInstrLength-1 downto 0) := x"3";
constant C_UNUSED_D : std_logic_vector(CInstrLength-1 downto 0) := x"D";
constant C_UNUSED_E : std_logic_vector(CInstrLength-1 downto 0) := x"E";
constant CInitInstrRegVal : std_logic_vector(CInstrLength-1 downto 0) := C_IDCODE; -- May be C_IDCODE or C_BYPASS
-- IDCODE register fields
--constant CVersion : std_logic_vector(3 downto 0) := x"E"; -- Version Number (ATmega16)
--constant CPartNumber : std_logic_vector(15 downto 0) := x"9403"; -- Part Number (ATmega16)
constant CVersion : std_logic_vector(3 downto 0) := x"6"; -- Version Number (ATmega128)
constant CPartNumber : std_logic_vector(15 downto 0) := x"9702"; -- Part Number (ATmega128)
constant CManufacturerId : std_logic_vector(10 downto 0) := "000"&x"1F"; -- Manufacturer ID(Atmel)
constant C_ProgEnableVect : std_logic_vector(15 downto 0) := x"A370";
-- OCD register addresses
constant C_OCDPSB0Adr : std_logic_vector(3 downto 0) := x"0";
constant C_OCDPSB1Adr : std_logic_vector(3 downto 0) := x"1";
constant C_OCDPDMSBAdr : std_logic_vector(3 downto 0) := x"2";
constant C_OCDPDSBAdr : std_logic_vector(3 downto 0) := x"3";
constant C_OCDBCRAdr : std_logic_vector(3 downto 0) := x"8";
constant C_OCDBSRAdr : std_logic_vector(3 downto 0) := x"9";
constant C_OCDOCDRAdr : std_logic_vector(3 downto 0) := x"C";
constant C_OCDCSRAdr : std_logic_vector(3 downto 0) := x"D";
constant C_AVRBreakInst : std_logic_vector(15 downto 0) := x"9598";
constant C_MaxEraseAdr : std_logic_vector(15 downto 0) := x"FFFF";
end JTAGPack;

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--**********************************************************************************************
-- Constants and types for JTAG "Flash" proggrammer for AVR Core
-- Version 0.11
-- Modified 13.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGProgrammerPack is
-- JTAG Programming Instruction (Page 311 Table 131)
constant CPrgComdRgLength : positive := 15;
-- ---------------------------------------------------------------------------------------------------
-- 1a. Chip erase
constant C_Prg_1A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000";
constant C_Prg_1A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010000110000000"; -- "011000110000000"
constant C_Prg_1A_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
constant C_Prg_1A_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
-- 1b. Poll for chip erase complete
constant C_Prg_1B : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001110000000"; -- "011001110000000"
-- ---------------------------------------------------------------------------------------------------
-- 2a. Enter Flash Write
constant C_Prg_2A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010000";
-- 2b. Load Address High Byte (+ 8 Bit)
constant C_Prg_2B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 2c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_2C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 2d. Load Data Low Byte (+ 8 Bit)
constant C_Prg_2D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 2e. Load Data High Byte (+ 8 Bit)
constant C_Prg_2E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010111";
-- 2f. Latch Data
constant C_Prg_2F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000";
constant C_Prg_2F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 2g. Write Flash Page
constant C_Prg_2G_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2G_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000";
constant C_Prg_2G_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_2G_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 2h. Poll for Page Write complete
constant C_Prg_2H : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 3a. Enter Flash Read
constant C_Prg_3A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000010";
-- 3b. Load Address High Byte (+ 8 Bit)
constant C_Prg_3B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 3c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_3C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 3d. Read Data Low and High Byte
constant C_Prg_3D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_3D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_3D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 4a. Enter EEPROM Write
constant C_Prg_4A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100010001";
-- 4b. Load Address High Byte (+ 8 Bit)
constant C_Prg_4B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 4c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_4C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 4d. Load Data Byte (+ 8 Bit)
constant C_Prg_4D : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 4e. Latch Data
constant C_Prg_4E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_4E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "111011100000000";
constant C_Prg_4E_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 4f. Write EEPROM Page
constant C_Prg_4F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_4F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_4F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_4F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 4g. Poll for Page Write complete
constant C_Prg_4G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 5a. Enter EEPROM Read
constant C_Prg_5A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000011";
-- 5b. Load Address High Byte (+ 8 Bit)
constant C_Prg_5B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000111";
-- 5c. Load Address Low Byte (+ 8 Bit)
constant C_Prg_5C : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 5d. Read Data Byte
constant C_Prg_5D_1 : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0110011";
constant C_Prg_5D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_5D_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 6a. Enter Fuse Write
constant C_Prg_6A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001101000000";
-- 6b. Load Data Low Byte(6) (+ 8 Bit)
constant C_Prg_6B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6c. Write Fuse Extended byte
constant C_Prg_6C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
constant C_Prg_6C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011100100000000";
constant C_Prg_6C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
constant C_Prg_6C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
-- 6d. Poll for Fuse Write complete
constant C_Prg_6D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6e. Load Data Low Byte (+ 8 Bit)
constant C_Prg_6E : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6f. Write Fuse High byte
constant C_Prg_6F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_6F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011010100000000";
constant C_Prg_6F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
constant C_Prg_6F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6g. Poll for Fuse Write complete
constant C_Prg_6G : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- 6h. Load Data Low Byte (+ 8 Bit)
constant C_Prg_6H : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0010011";
-- 6i. Write Fuse Low byte
constant C_Prg_6I_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_6I_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_6I_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_6I_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 6j. Poll for Fuse Write complete
constant C_Prg_6J : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 7a. Enter Lock bit Write
constant C_Prg_7A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100100000";
-- 7b. Load Data Byte (+6 Bit)
constant C_Prg_7B : std_logic_vector(CPrgComdRgLength-6-1 downto 0) := "001001111";
-- 7c. Write Lock bits
constant C_Prg_7C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_7C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011000100000000";
constant C_Prg_7C_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
constant C_Prg_7C_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 7d. Poll for Lock bit Write complete
constant C_Prg_7D : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 8a. Enter Fuse/Lock bit Read
constant C_Prg_8A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000100";
-- 8b. Read Extended Fuse Byte
constant C_Prg_8B_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000";
constant C_Prg_8B_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101100000000";
-- 8c. Read Fuse High Byte
constant C_Prg_8C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000";
constant C_Prg_8C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111100000000";
-- 8d. Read Fuse Low Byte
constant C_Prg_8D_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_8D_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- 8e. Read Lock bits
constant C_Prg_8E_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_8E_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
--8f. Read Fuses and Lock bits 0111010000000
constant C_Prg_8F_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011101000000000";
constant C_Prg_8F_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011111000000000";
constant C_Prg_8F_3 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_8F_4 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_8F_5 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 9a. Enter Signature Byte Read 0100010001000
constant C_Prg_9A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000";
-- 9b. Load Address Byte (+ 8 Bit)
constant C_Prg_9B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 9c. Read Signature Byte
constant C_Prg_9C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001000000000";
constant C_Prg_9C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
-- 10a. Enter Calibration Byte Read
constant C_Prg_10A : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100001000";
-- 10b. Load Address Byte (+ 8 Bit)
constant C_Prg_10B : std_logic_vector(CPrgComdRgLength-8-1 downto 0) := "0000011";
-- 10c. Read Calibration Byte
constant C_Prg_10C_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011000000000";
constant C_Prg_10C_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011011100000000";
-- ---------------------------------------------------------------------------------------------------
-- 11a. Load No Operation Command
constant C_Prg_11A_1 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "010001100000000";
constant C_Prg_11A_2 : std_logic_vector(CPrgComdRgLength-1 downto 0) := "011001100000000";
-- ---------------------------------------------------------------------------------------------------
end JTAGProgrammerPack;

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--**********************************************************************************************
-- JTAG TAP controller SM
-- Version 0.2
-- Modified 14.06.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGTAPCtrlSMPack is
type TAPCtrlState_Type is (TestLogicReset,RunTestIdle,
SelectDRScan,CaptureDR,ShiftDR,Exit1DR,PauseDR,Exit2DR,UpdateDR,
SelectIRScan,CaptureIR,ShiftIR,Exit1IR,PauseIR,Exit2IR,UpdateIR);
function FnTAPNextState(CurrentTAPState : TAPCtrlState_Type; TMS : std_logic) return TAPCtrlState_Type;
function FnJTAGRgSh (ShRg : std_logic_vector ; DataIn : std_logic) return std_logic_vector;
end JTAGTAPCtrlSMPack;
package body JTAGTAPCtrlSMPack is
function FnTAPNextState(CurrentTAPState : TAPCtrlState_Type; TMS : std_logic) return TAPCtrlState_Type is
variable NextTAPState : TAPCtrlState_Type;
begin
case CurrentTAPState is
when TestLogicReset =>
if (TMS='0') then NextTAPState := RunTestIdle;
else NextTAPState := TestLogicReset;
end if;
when RunTestIdle =>
if (TMS='1') then NextTAPState := SelectDRScan;
else NextTAPState := RunTestIdle;
end if;
-- Data register
when SelectDRScan =>
if (TMS='1') then NextTAPState := SelectIRScan;
else NextTAPState := CaptureDR;
end if;
when CaptureDR =>
if (TMS='1') then NextTAPState := Exit1DR;
else NextTAPState := ShiftDR;
end if;
when ShiftDR =>
if (TMS='1') then NextTAPState := Exit1DR;
else NextTAPState := ShiftDR;
end if;
when Exit1DR =>
if (TMS='1') then NextTAPState := UpdateDR;
else NextTAPState := PauseDR;
end if;
when PauseDR =>
if (TMS='1') then NextTAPState := Exit2DR;
else NextTAPState := PauseDR;
end if;
when Exit2DR =>
if (TMS='1') then NextTAPState := UpdateDR;
else NextTAPState := ShiftDR;
end if;
when UpdateDR =>
if (TMS='1') then NextTAPState := SelectDRScan;
else NextTAPState := RunTestIdle;
end if;
-- Instruction register
when SelectIRScan =>
if (TMS='1') then NextTAPState := TestLogicReset;
else NextTAPState := CaptureIR;
end if;
when CaptureIR =>
if (TMS='1') then NextTAPState := Exit1IR;
else NextTAPState := ShiftIR;
end if;
when ShiftIR =>
if (TMS='1') then NextTAPState := Exit1IR;
else NextTAPState := ShiftIR;
end if;
when Exit1IR =>
if (TMS='1') then NextTAPState := UpdateIR;
else NextTAPState := PauseIR;
end if;
when PauseIR =>
if (TMS='1') then NextTAPState := Exit2IR;
else NextTAPState := PauseIR;
end if;
when Exit2IR =>
if (TMS='1') then NextTAPState := UpdateIR;
else NextTAPState := ShiftIR;
end if;
when UpdateIR =>
if (TMS='1') then NextTAPState := SelectDRScan;
else NextTAPState := RunTestIdle;
end if;
when others => NextTAPState := TestLogicReset;
end case;
return NextTAPState;
end FnTAPNextState; -- End of funcrtion
function FnJTAGRgSh (ShRg : std_logic_vector ; DataIn : std_logic) return std_logic_vector is
variable TmpVector : std_logic_vector(ShRg'range);
begin
TmpVector := DataIn&ShRg(ShRg'high downto ShRg'low+1);
return TmpVector;
end FnJTAGRgSh; -- End of function
end JTAGTAPCtrlSMPack;

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--**********************************************************************************************
-- JTAG "Flash" programmer for AVR Core(TCK Clock Domain)
-- Version 0.4
-- Modified 20.06.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.JTAGPack.all;
use WORK.JTAGProgrammerPack.all;
use WORK.JTAGDataPack.all;
use WORK.JTAGTAPCtrlSMPack.all;
entity OCDProgTCK is port(
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From/To cp2 clock domain("Flash" programmer)
FlEEPrgAdr : out std_logic_vector(15 downto 0);
FlPrgRdData : in std_logic_vector(15 downto 0);
EEPrgRdData : in std_logic_vector(7 downto 0);
FlEEPrgWrData : out std_logic_vector(15 downto 0);
ChipEraseStart : out std_logic;
ChipEraseDone : in std_logic;
ProgEnable : out std_logic;
FlWrMStart : out std_logic; -- Multiple
FlWrSStart : out std_logic; -- Single
FlRdMStart : out std_logic; -- Multiple
FlRdSStart : out std_logic; -- Single
EEWrStart : out std_logic;
EERdStart : out std_logic;
TAPCtrlTLR : out std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- CPU reset
jtag_rst : out std_logic
);
end OCDProgTCK;
architecture RTL of OCDProgTCK is
signal CurrentTAPState : TAPCtrlState_Type;
signal NextTAPState : TAPCtrlState_Type;
-- JTAG Registers
-- Instruction registers
signal InstructionShRg : std_logic_vector(CInstrLength-1 downto 0); -- Shift
signal InstructionRg : std_logic_vector(CInstrLength-1 downto 0); -- Update
-- Bypass register
signal BypassShRg : std_logic; -- Shift(only)
-- **********************************************************************
signal IDCODEShRg : std_logic_vector(31 downto 0);
signal DataRegsOutMux : std_logic;
signal UnusedInstr : std_logic; -- Unsupported instruction
-- Reset chain (1 bit length, no updade register)
signal ResetShRg : std_logic;
-- ************************* Programmer part ********************************************
-- Program chains
signal PERSh : std_logic_vector(15 downto 0); -- Programming Enable Register (Shift part ?only?)
signal PCRSh : std_logic_vector(14 downto 0); -- Programming Command Register (Shift part)
signal PCRUd : std_logic_vector(PCRSh'range); -- Programming Command Register (Update part)
signal PCRShIn : std_logic_vector(PCRSh'range); -- Programming Command Register Input
signal VFPLSh : std_logic_vector(7 downto 0); -- Virtual Flash Page Load Register (Shift part only)
signal VFPRSh : std_logic_vector(7 downto 0); -- Virtual Flash Page Read Register (Shift part only)
signal VFPRShIn : std_logic_vector(VFPRSh'range); -- Virtual Flash Page Read Register Input
signal ProgEnable_Int : std_logic;
-- TCK counter for Virtual Flash Page Load/Read commands
signal VFPCnt : std_logic_vector(3 downto 0);
signal LdDataLow : std_logic; -- Load low byte of data
signal LdDataHigh : std_logic; -- Load high byte of data and runs "Flash" write SM(cp2 clock domain)
signal FlashAdrIncrEn : std_logic; -- Enables increment of VFPCnt (when LdDataHigh='1')
signal LatchWrData : std_logic;
-- Address(16-bit) and Instruction For Write (16-bit) registers located in TCK clock domaim
signal FlEEPrgAdr_Int : std_logic_vector(15 downto 0); -- Copy of output
-- Address counter length
constant CPageAdrCntLength : positive range 7 to 8 := 7; -- 8 for ATmega128, 7 for ATmega16,...
-- "Flash" programmer state machines (located in TCK clock domaim)
type ChipEraseSMStType is (ChipEraseSMStIdle,ChipEraseSMSt1,ChipEraseSMSt2,ChipEraseSMSt3);
signal ChipEraseSM_CurrentState : ChipEraseSMStType; -- Chip erase
signal ChipEraseSM_NextState : ChipEraseSMStType; -- Chip erase (combinatorial)
signal FlashWr_St : std_logic; -- 2
signal FlashRd_St : std_logic; -- 3
signal EEPROMWr_St : std_logic; -- 4
signal EEPROMRd_St : std_logic; -- 5
signal FuseWr_St : std_logic; -- 6
signal LockWr_St : std_logic; -- 7
signal FuseLockRd_St : std_logic; -- 8
signal SignByteRd_St : std_logic; -- 9
signal LoadNOP_St : std_logic; -- 11
-- EEPROM Write Support
signal EEWrStart_Int : std_logic;
signal EERdStart_Int : std_logic;
begin
TAPStateReg:process(TCK,TRSTn)
begin
if(TRSTn='0') then -- Reset
CurrentTAPState <= TestLogicReset;
elsif(TCK='1' and TCK'event) then -- Clock(rising edge)
CurrentTAPState <= NextTAPState;
end if;
end process;
NextTAPState <= FnTAPNextState(CurrentTAPState,TMS);
-- Instruction register
InstructionRegisterShift:process(TCK,TRSTn)
begin
if(TRSTn='0') then -- Reset
InstructionShRg <= (others => '0');
elsif(TCK='1' and TCK'event) then -- Clock(rising edge)
case CurrentTAPState is
--when CaptureIR => InstructionShRg <= InstructionRg(InstructionRg'high downto 2)&"01"; -- !!! TBD !!!
when CaptureIR => InstructionShRg <= InstructionRg; -- !!! TBD !!!
when ShiftIR => InstructionShRg <= FnJTAGRgSh(InstructionShRg,TDI);
when others => null;
end case;
end if;
end process;
InstructionRegisterUpdate:process(TCK,TRSTn)
begin
if (TRSTn='0') then -- Reset
InstructionRg <= CInitInstrRegVal;
elsif (TCK='0' and TCK'event) then -- Clock(falling edge)
if (CurrentTAPState=TestLogicReset) then
InstructionRg <= CInitInstrRegVal; -- Set to give IDCODE or BYPASS instruction
elsif CurrentTAPState=UpdateIR then
InstructionRg <= InstructionShRg;
end if;
end if;
end process;
-- Data registers
-- ID Code register
IDCodeRegisterShift:process(TCK,TRSTn)
begin
if (TRSTn='0') then -- Reset
IDCODEShRg <= (others => '0');
elsif (TCK='1' and TCK'event) then -- Clock(rising edge)
if (InstructionRg=C_IDCODE) then -- The Instruction register content enables The Data register shift
case CurrentTAPState is
when CaptureDR => IDCODEShRg <= CVersion&CPartNumber&CManufacturerId&'1';
when ShiftDR => IDCODEShRg <= FnJTAGRgSh(IDCODEShRg,TDI);
when others => null;
end case;
end if;
end if;
end process;
-- Bypass register
BypassRegisterShift:process(TCK,TRSTn)
begin
if (TRSTn='0') then -- Reset
BypassShRg <= '0';
elsif (TCK='1' and TCK'event) then -- Clock(rising edge)
if (InstructionRg=C_BYPASS) then -- !!! TBD !!!
case CurrentTAPState is
when ShiftDR => BypassShRg <= TDI;
when others => BypassShRg <= '0'; -- ??? TBD
end case;
end if;
end if;
end process;
DORegAndTDOOE:process(TCK,TRSTn)
begin
if (TRSTn='0') then -- Reset
TDO <= '0';
TDO_OE <= '0';
elsif (TCK='0' and TCK'event) then -- Clock(falling edge)
TDO <= DataRegsOutMux;
if (CurrentTAPState=ShiftIR or CurrentTAPState=ShiftDR) then
TDO_OE <= '1';
else
TDO_OE <= '0';
end if;
end if;
end process;
-- ***************************************************************************************
UnusedInstr <= '1' when (InstructionRg=C_UNUSED_3 or InstructionRg=C_UNUSED_D or
InstructionRg=C_UNUSED_E or InstructionRg=C_OCD_ACCESS or InstructionRg= C_EX_INST) else '0';
DataRegsOutMux <= InstructionShRg(InstructionShRg'low) when CurrentTAPState=ShiftIR else -- !!! TBD !!!
'0' when InstructionRg=C_SAMPLE_PRELOAD or InstructionRg=C_EXTEST else -- !!! TBD !!!
IDCODEShRg(IDCODEShRg'low) when InstructionRg=C_IDCODE else
ResetShRg when InstructionRg=C_AVR_RESET else
PERSh(PERSh'low) when InstructionRg=C_PROG_ENABLE else
PCRSh(PCRSh'low) when InstructionRg=C_PROG_COMMANDS else
VFPLSh(VFPLSh'low) when InstructionRg=C_PROG_PAGELOAD else
VFPRSh(VFPRSh'low) when InstructionRg=C_PROG_PAGEREAD else
BypassShRg;
-- ***************************************************************************************
-- Reset chain (1 bit length, no updade register)
ResetRegisterShift:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge)
if(InstructionRg=C_AVR_RESET and CurrentTAPState=ShiftDR) then
ResetShRg <= TDI;
end if;
end if;
end process;
jtag_rst <= ResetShRg;
-- ************************************************************************************
-- ************************* Programmer part ********************************************
-- ************************************************************************************
-- Programming Enable Register(no update circuit)
PER_Shift:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge)
if(InstructionRg=C_PROG_ENABLE and CurrentTAPState=ShiftDR) then
PERSh <= FnJTAGRgSh(PERSh,TDI);
end if;
end if;
end process;
-- Programming enable signal generation(!!! TBD !!!)
PE_Gen_Rg:process(TCK)
begin
if(TCK='0' and TCK'event) then -- Clock(falling edge)
if(InstructionRg=C_PROG_ENABLE and CurrentTAPState=UpdateDR) then -- ???
if(PERSh=C_ProgEnableVect) then
ProgEnable_Int <= '1';
else
ProgEnable_Int <= '0';
end if;
end if;
end if;
end process;
-- Programming Command Register
PCR_Shift:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge)
if(InstructionRg=C_PROG_COMMANDS) then
case CurrentTAPState is
when CaptureDR => PCRSh <= PCRShIn; -- Load data
when ShiftDR => PCRSh <= FnJTAGRgSh(PCRSh,TDI);
when others => null;
end case;
end if;
end if;
end process;
PCRShIn(14 downto 10) <= PCRSh(14 downto 10);
PCRShIn(8) <= PCRSh(8);
-- Poll response !!!TBD!!!
PCRShIn(9) <= '0' when (ChipEraseSM_CurrentState /= ChipEraseSMStIdle) else '1';
PCRReadSystem:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge)
if(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then
if(FlashRd_St='1') then -- Flash read
if(PCRSh=C_Prg_3D_1) then
PCRShIn(7 downto 0) <= FlPrgRdData(7 downto 0); -- Read low flash byte
elsif(PCRSh=C_Prg_3D_2) then
PCRShIn(7 downto 0) <= FlPrgRdData(15 downto 8); -- Read high flash byte
end if;
elsif(EEPROMRd_St='1') then -- EEPROM read
if(PCRSh=C_Prg_5D_2) then
PCRShIn(7 downto 0) <= EEPrgRdData;
end if;
elsif(FuseLockRd_St='1') then -- Fuse/Lock bit Read Mode(8)
case PCRSh is -- !!!TBD!!! (Length)
when C_Prg_8B_1 => -- 8b(8f1) Read Extended Fuse Byte
PCRShIn(7 downto 0) <= C_ExtFuseByte;
when C_Prg_8C_1 => -- 8c(8f2) Read Fuse High Byte
PCRShIn(7 downto 0) <= C_HighFuseByte;
when C_Prg_8D_1 => -- 8d(8f3) Read Fuse Low Byte
PCRShIn(7 downto 0) <= C_LowFuseByte;
when C_Prg_8E_1 => -- 8e(8f4) Read Lock Bits
PCRShIn(7 downto 0) <= C_LockBits;
when others => null;
end case;
elsif (SignByteRd_St='1') then -- Signature Byte Read Mode(9/10)
if(PCRSh=C_Prg_9C_1) then -- Read Signature Byte(9c) -> 0110010_00000000
case FlEEPrgAdr_Int(3 downto 0) is -- !!!TBD!!! (Length)
when x"0" => PCRShIn(7 downto 0) <= C_SignByte1;
when x"1" => PCRShIn(7 downto 0) <= C_SignByte2;
when x"2" => PCRShIn(7 downto 0) <= C_SignByte3;
when others => null;
end case;
elsif(PCRSh=C_Prg_10C_1) then -- Read Calibration Byte(10c) -> 0110110_00000000
case FlEEPrgAdr_Int(3 downto 0) is -- !!!TBD!!! (Length)
when x"0" => PCRShIn(7 downto 0) <= C_CalibrByte1;
when x"1" => PCRShIn(7 downto 0) <= C_CalibrByte2;
when x"2" => PCRShIn(7 downto 0) <= C_CalibrByte3;
when x"3" => PCRShIn(7 downto 0) <= C_CalibrByte4;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
PCR_Update:process(TCK)
begin
if(TCK='0' and TCK'event) then -- Clock(falling edge)
if (CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then -- Clock enable (!!!InstructionRg=C_PROG_COMMANDS!!!)
PCRUd <= PCRSh;
end if;
end if;
end process;
-- Virtual Flash Page Load Register(!!!shift only!!!)
VFPL_Shift:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge)
if(InstructionRg=C_PROG_PAGELOAD and CurrentTAPState=ShiftDR) then
VFPLSh <= FnJTAGRgSh(VFPLSh,TDI);
end if;
end if;
end process;
-- !!! TBD !!!
VFPRShIn <= FlPrgRdData(7 downto 0) when VFPCnt(VFPCnt'high)='0' else -- Low Byte
FlPrgRdData(15 downto 8); -- High Byte
-- Virtual Flash Page Read Register
VFPR_Shift:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge)
if((VFPCnt=x"7" or VFPCnt=x"F"))then -- Load Data (Low/High Byte) !!!TBD!!!
VFPRSh <= VFPRShIn; -- Load data
elsif(InstructionRg=C_PROG_PAGEREAD and CurrentTAPState=ShiftDR) then
VFPRSh <= FnJTAGRgSh(VFPRSh,TDI);
end if;
end if;
end process;
-- TCK counter for Virtual Flash Page Load/Read commands
VFPCounterReg:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge) ???
if(CurrentTAPState=CaptureDR)then -- Clear
VFPCnt <= (others => '0');
elsif(CurrentTAPState=ShiftDR and
(InstructionRg=C_PROG_PAGELOAD or InstructionRg=C_PROG_PAGEREAD)and
(FlashWr_St='1' or FlashRd_St='1')) then -- Was : FlashWr_St='1' only
VFPCnt <= VFPCnt+1; -- Increment
end if;
end if;
end process;
VFPWrControl:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge) ???
if(CurrentTAPState=CaptureDR)then -- Clear
LdDataLow <= '0';
LdDataHigh <= '0';
FlashAdrIncrEn <= '0';
elsif(CurrentTAPState=ShiftDR and InstructionRg=C_PROG_PAGELOAD and FlashWr_St='1') then -- Page Load
if(VFPCnt=x"7") then
LdDataLow <= '1';
else
LdDataLow <= '0';
end if;
if(VFPCnt=x"F") then
LdDataHigh <= '1';
else
LdDataHigh <= '0';
end if;
if(LdDataHigh='1') then -- !!!TBD!!!
FlashAdrIncrEn <= '1';
end if;
end if;
end if;
end process;
VFPRdControl:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge)
if(CurrentTAPState=CaptureDR)then -- Clear
FlRdMStart <= '0';
elsif(CurrentTAPState=ShiftDR and InstructionRg=C_PROG_PAGEREAD and FlashRd_St='1') then -- Page Read
if(VFPCnt=x"1") then
FlRdMStart <= '1';
else
FlRdMStart <= '0';
end if;
end if;
end if;
end process;
LatchWriteData:process(TCK)
begin
if(TCK='0' and TCK'event) then -- Clock(falling edge) ???
if(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and
FlashWr_St='1' and PCRSh=C_Prg_2F_2) then
LatchWrData <= '1';
else
LatchWrData <= '0';
end if;
end if;
end process;
-- EEPROM
EEPROMWrRdCtrl:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge) ???
if(CurrentTAPState=CaptureDR)then -- Clear
EEWrStart_Int <= '0';
elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and EEPROMWr_St='1' and PCRSh=C_Prg_4E_2) then -- EEPROM Write
EEWrStart_Int <= '1';
else
EEWrStart_Int <= '0';
end if;
if(CurrentTAPState=CaptureDR)then -- Clear
EERdStart_Int <= '0';
elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and EEPROMRd_St='1' and PCRSh(14 downto 8)=C_Prg_5D_1) then -- EEPROM Read ! was C_Prg_5D_2
EERdStart_Int <= '1';
else
EERdStart_Int <= '0';
end if;
end if;
end process;
-- Flash single beat operations (Write/Read)
FlashSingleWrRdCtrl:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(rising edge) ???
if(CurrentTAPState=CaptureDR)then
FlWrSStart <= '0';
elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and FlashWr_St='1' and PCRSh=C_Prg_2F_2) then -- Flash write (single)
FlWrSStart <= '1';
else
FlWrSStart <= '0';
end if;
if(CurrentTAPState=CaptureDR)then
FlRdSStart <= '0';
elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and FlashRd_St='1' and PCRSh=C_Prg_3D_1) then -- Flash read (single)
FlRdSStart <= '1';
else
FlRdSStart <= '0';
end if;
end if;
end process;
-- Address register
FlashProgrammerAdrReg:process(TCK)
begin
if(TCK='0' and TCK'event) then -- Clock(falling edge) like udate reg ???
if(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then
if(PCRSh(14 downto 8)="0000011") then -- Load Address Low Byte(2c,3c,4c,5c,9b,10b)
FlEEPrgAdr_Int(7 downto 0) <= PCRSh(7 downto 0);
elsif(PCRSh(14 downto 8)="0000111")then -- Load Address High Byte(2b,3b,4b,5b)
FlEEPrgAdr_Int(15 downto 8) <= PCRSh(7 downto 0);
end if;
elsif(((CurrentTAPState=ShiftDR or CurrentTAPState=Exit1DR)and
InstructionRg=C_PROG_PAGELOAD and LdDataHigh='1' and FlashAdrIncrEn='1')or -- Write "Flash"
(CurrentTAPState=ShiftDR and InstructionRg=C_PROG_PAGEREAD and FlashRd_St='1' and VFPCnt=x"E")) then -- Read "Flash"
-- Increment address counter
FlEEPrgAdr_Int(CPageAdrCntLength-1 downto 0)<=FlEEPrgAdr_Int(CPageAdrCntLength-1 downto 0)+1;
end if;
end if;
end process;
-- Data register
FlashProgrammerDataReg:process(TCK)
begin
if(TCK='0' and TCK'event) then -- Clock(falling edge) like udate reg ???
if(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then
if(PCRSh(14 downto 8)="0010011") then -- Load Data Low Byte(2d,4d,6b,6e,6h,7b)
FlEEPrgWrData(7 downto 0) <= PCRSh(7 downto 0);
elsif(PCRSh(14 downto 8)="0010111") then -- Load Data High Byte(2e)
FlEEPrgWrData(15 downto 8) <= PCRSh(7 downto 0);
end if;
elsif((CurrentTAPState=ShiftDR or CurrentTAPState=Exit1DR)and (InstructionRg=C_PROG_PAGELOAD)) then
if(LdDataLow='1') then -- Load Data Low Byte(from the Virtual Flash Page Load Register)
FlEEPrgWrData(7 downto 0) <= VFPLSh;
elsif(LdDataHigh='1') then -- Load Data High Byte(from the Virtual Flash Page Load Register)
FlEEPrgWrData(15 downto 8) <= VFPLSh;
end if;
end if;
end if;
end process;
-- Programmer State Machines
EraseSMRg:process(TCK,TRSTn)
begin
if(TRSTn='0') then -- Reset (!!!TBD!!!)
ChipEraseSM_CurrentState <= ChipEraseSMStIdle;
elsif(TCK='1' and TCK'event) then -- Clock(rising edge)
if (CurrentTAPState=TestLogicReset) then -- Test-Logic-Reset state
ChipEraseSM_CurrentState <= ChipEraseSMStIdle;
elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then
ChipEraseSM_CurrentState <= ChipEraseSM_NextState;
end if;
end if;
end process;
-- Programmer State Machines
ChipEraseStartDFF:process(TCK,TRSTn)
begin
if(TRSTn='0') then -- Reset (!!!TBD!!!)
ChipEraseStart <= '0';
elsif(TCK='1' and TCK'event) then -- Clock(rising edge)
if(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS and PCRSh=C_Prg_1A_1 and ProgEnable_Int='1') then
ChipEraseStart <= '1';
else
ChipEraseStart <= '0';
end if;
end if;
end process;
EraseSMComb:process(ChipEraseSM_CurrentState,PCRUd,ChipEraseDone,ProgEnable_Int) -- Combinatorial
begin
case ChipEraseSM_CurrentState is
when ChipEraseSMStIdle =>
if(PCRUd=C_Prg_1A_1 and ProgEnable_Int='1') then
ChipEraseSM_NextState <= ChipEraseSMSt1;
else
ChipEraseSM_NextState <= ChipEraseSMStIdle;
end if;
when ChipEraseSMSt1 =>
if(PCRUd=C_Prg_1A_2) then
ChipEraseSM_NextState <= ChipEraseSMSt2;
else
ChipEraseSM_NextState <= ChipEraseSMStIdle; -- Leaving Erase Mode
end if;
when ChipEraseSMSt2 =>
if(PCRUd=C_Prg_1A_3) then
ChipEraseSM_NextState <= ChipEraseSMSt3;
else
ChipEraseSM_NextState <= ChipEraseSMStIdle; -- Leaving Erase Mode
end if;
when ChipEraseSMSt3 =>
if(ChipEraseDone='1') then
ChipEraseSM_NextState <= ChipEraseSMStIdle;
else
ChipEraseSM_NextState <= ChipEraseSMSt3;
end if;
when others => ChipEraseSM_NextState <= ChipEraseSMStIdle;
end case;
end process;
ProgSMsRegs:process(TCK,TRSTn)
begin
if(TRSTn='0') then -- Reset (!!!TBD!!!)
FlashWr_St <= '0';
FlashRd_St <= '0';
EEPROMWr_St <= '0';
EEPROMRd_St <= '0';
FuseWr_St <= '0';
LockWr_St <= '0';
FuseLockRd_St <= '0';
SignByteRd_St <= '0';
LoadNOP_St <= '0';
elsif(TCK='1' and TCK'event) then -- Clock(rising edge)
if(CurrentTAPState=TestLogicReset)then
FlashWr_St <= '0';
FlashRd_St <= '0';
EEPROMWr_St <= '0';
EEPROMRd_St <= '0';
FuseWr_St <= '0';
LockWr_St <= '0';
FuseLockRd_St <= '0';
SignByteRd_St <= '0';
LoadNOP_St <= '0';
elsif(CurrentTAPState=UpdateDR and InstructionRg=C_PROG_COMMANDS) then
case FlashWr_St is
when '0' =>
if(PCRUd=C_Prg_2A and ProgEnable_Int='1')then
FlashWr_St <= '1';
end if;
when '1' =>
if(PCRUd(14 downto 8)=C_Prg_2A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_2A(7 downto 0))then
FlashWr_St <= '0';
end if;
when others => null;
end case;
case FlashRd_St is
when '0' =>
if(PCRUd=C_Prg_3A and ProgEnable_Int='1')then
FlashRd_St <= '1';
end if;
when '1' =>
if(PCRUd(14 downto 8)=C_Prg_3A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_3A(7 downto 0))then
FlashRd_St <= '0';
end if;
when others => null;
end case;
case EEPROMWr_St is
when '0' =>
if(PCRUd=C_Prg_4A and ProgEnable_Int='1')then
EEPROMWr_St <= '1';
end if;
when '1' =>
if(PCRUd(14 downto 8)=C_Prg_4A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_4A(7 downto 0))then
EEPROMWr_St <= '0';
end if;
when others => null;
end case;
case EEPROMRd_St is
when '0' =>
if(PCRUd=C_Prg_5A and ProgEnable_Int='1')then
EEPROMRd_St <= '1';
end if;
when '1' =>
if(PCRUd(14 downto 8)=C_Prg_5A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_5A(7 downto 0))then
EEPROMRd_St <= '0';
end if;
when others => null;
end case;
case FuseWr_St is
when '0' =>
if(PCRUd=C_Prg_6A and ProgEnable_Int='1')then
FuseWr_St <= '1';
end if;
when '1' =>
if(PCRUd(14 downto 8)=C_Prg_6A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_6A(7 downto 0))then
FuseWr_St <= '0';
end if;
when others => null;
end case;
case LockWr_St is
when '0' =>
if(PCRUd=C_Prg_7A and ProgEnable_Int='1')then
LockWr_St <= '1';
end if;
when '1' =>
if(PCRUd(14 downto 8)=C_Prg_7A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_7A(7 downto 0))then
LockWr_St <= '0';
end if;
when others => null;
end case;
case FuseLockRd_St is
when '0' =>
if(PCRUd=C_Prg_8A and ProgEnable_Int='1')then
FuseLockRd_St <= '1';
end if;
when '1' =>
if(PCRUd(14 downto 8)=C_Prg_8A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_8A(7 downto 0))then
FuseLockRd_St <= '0';
end if;
when others => null;
end case;
case SignByteRd_St is
when '0' =>
if(PCRUd=C_Prg_9A and ProgEnable_Int='1')then
SignByteRd_St <= '1';
end if;
when '1' =>
if(PCRUd(14 downto 8)=C_Prg_9A(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_9A(7 downto 0))then
SignByteRd_St <= '0';
end if;
when others => null;
end case;
case LoadNOP_St is
when '0' =>
if(PCRUd=C_Prg_11A_1 and ProgEnable_Int='1')then
LoadNOP_St <= '1';
end if;
when '1' =>
if(PCRUd(14 downto 8)=C_Prg_11A_1(14 downto 8) and PCRUd(7 downto 0)/=C_Prg_11A_1(7 downto 0))then
LoadNOP_St <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TAPResetFlag:process(TCK,TRSTn)
begin
if(TRSTn='0') then -- Reset (!!!TBD!!!)
TAPCtrlTLR <= '1';
elsif(TCK='1' and TCK'event) then -- Clock(rising edge)
if((CurrentTAPState=SelectIRScan and TMS='1')or(CurrentTAPState=TestLogicReset and TMS='0'))then
TAPCtrlTLR <= '1';
else
TAPCtrlTLR <= '0';
end if;
end if;
end process;
-- *************************** End of programmer part *******************************
-- Outputs
FlEEPrgAdr <= FlEEPrgAdr_Int;
FlWrMStart <= LdDataHigh;
ProgEnable <= ProgEnable_Int;
end RTL;

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--**********************************************************************************************
-- JTAG "Flash" programmer for AVR Core(cp2 Clock Domain)
-- Version 0.5
-- Modified 20.06.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.JTAGPack.all;
use WORK.AVRuCPackage.all;
entity OCDProgcp2 is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- From/To TCK clock domain("Flash" programmer)
FlEEPrgAdr : in std_logic_vector(15 downto 0);
FlPrgRdData : out std_logic_vector(15 downto 0);
EEPrgRdData : out std_logic_vector(7 downto 0);
FlEEPrgWrData : in std_logic_vector(15 downto 0);
ChipEraseStart : in std_logic;
ChipEraseDone : out std_logic;
ProgEnable : in std_logic;
FlWrMStart : in std_logic; -- Multiple
FlWrSStart : in std_logic; -- Single
FlRdMStart : in std_logic; -- Multiple
FlRdSStart : in std_logic; -- Single
EEWrStart : in std_logic;
EERdStart : in std_logic;
TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic
);
end OCDProgcp2;
architecture RTL of OCDProgcp2 is
-- **********************************************************************************
-- *************************** Programmer part *********************************************
-- **********************************************************************************
-- Edge detectors
signal TAPCtrlTLRDel : std_logic; -- TAP Run-Test/Idle
-- Chip Erase Start edge detector
signal ChipEraseStartDel : std_logic;
-- Flash Write Start(using Virtual Flash Page Load Register) edge detector
signal FlWrMStartDel : std_logic;
-- Flash Write Start(using Load Data Low(2d)/Load Data High(2e)) edge detector
signal FlWrSStartDel : std_logic;
-- Flash Read Start(using Virtual Flash Page Read Register) edge detector
signal FlRdMStartDel : std_logic;
-- Flash Read Start(using Load Data Low and High Byte(3d)) edge detector
signal FlRdSStartDel : std_logic;
-- "Flash" programmer state machines
signal FlWrCnt : std_logic_vector(1 downto 0) ; -- Write
signal FlRdCnt : std_logic_vector(1 downto 0) ; -- Read (Low andHigh bytes)
signal FlRd_St : std_logic; -- "Flash" read(Latch data)
-- "Flash" address and data registers
signal FlashPrgAdrRg : std_logic_vector(15 downto 0); -- Address(Write/Read)
signal FlashPrgDataRg : std_logic_vector(15 downto 0); -- Data(for Write)
-- Output copies
signal pm_h_we_Int : std_logic;
signal pm_l_we_Int : std_logic;
-- Chip erase
signal ChipErase_St : std_logic;
-- "EEPROM" support
-- Edge detectors
signal EEWrStartDel : std_logic;
signal EERdStartDel : std_logic;
-- EEPROM address and data registers
signal EEPrgAdrRg : std_logic_vector(EEAdr'range); -- Address(Write/Read)
signal EEPrgDataRg : std_logic_vector(EEWrData'range); -- Data(for Write)
signal EEWr_Int : std_logic;
-- EEPROM programmer state machines
signal EEWrCnt : std_logic_vector(1 downto 0) ; -- Write
signal EERdCnt : std_logic_vector(1 downto 0) ; -- Read
signal EERd_St : std_logic;
begin
-- ***************************** Programmer part ********************************
FlashWriteCntAndCtrl:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge)
-- Edge detectors
TAPCtrlTLRDel <= TAPCtrlTLR;
FlWrMStartDel <= FlWrMStart;
FlWrSStartDel <= FlWrSStart;
-- Delay counter
if(TAPCtrlTLR='1') then -- Reset counter
FlWrCnt <= (others => '0');
elsif((FlWrMStart='0' and FlWrMStartDel='1')or
(FlWrSStart='0' and FlWrSStartDel='1')) then
FlWrCnt <= "01";
elsif(FlWrCnt/="00") then
FlWrCnt <= FlWrCnt + 1;
end if;
-- Control
if(TAPCtrlTLR='1') then -- Reset control signals
pm_h_we_Int <= '0';
pm_l_we_Int <= '0';
else
case pm_h_we_Int is
when '0' =>
if((ChipEraseStart='1' and ChipEraseStartDel='0') or FlWrCnt="11") then
pm_h_we_Int <= '1';
end if;
when '1' =>
if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then
pm_h_we_Int <= '0';
end if;
when others => null;
end case;
case pm_l_we_Int is
when '0' =>
if((ChipEraseStart='1' and ChipEraseStartDel='0') or FlWrCnt="11") then
pm_l_we_Int <= '1';
end if;
when '1' =>
if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then
pm_l_we_Int <= '0';
end if;
when others => null;
end case;
end if;
-- Address (for Erase,Write and Read!!!)
if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase -> Clear address counter
FlashPrgAdrRg <= (others => '0');
elsif(ChipErase_St='1') then -- Chip erase -> increment aaddress
FlashPrgAdrRg <= FlashPrgAdrRg + 1;
elsif(FlWrCnt="11" or FlRdCnt="11") then -- Normal mode
FlashPrgAdrRg <= FlEEPrgAdr;
end if;
-- Data
if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase
FlashPrgDataRg <= (others => '1');
elsif(FlWrCnt="11") then -- Write to flash
FlashPrgDataRg <= FlEEPrgWrData;
end if;
-- EEPROM Address (for Erase,Write and Read!!!)
if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase -> Clear address counter
EEPrgAdrRg <= (others => '0');
elsif(ChipErase_St='1') then -- Chip erase -> increment aaddress
EEPrgAdrRg <= EEPrgAdrRg + 1;
elsif(EEWrCnt="11" or EERdCnt="11") then -- Normal mode
EEPrgAdrRg <= FlEEPrgAdr(EEPrgAdrRg'range);
end if;
-- EEPROM Data
if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase
EEPrgDataRg <= (others => '1');
elsif(EEWrCnt="11") then -- Write to EEPROM
EEPrgDataRg <= FlEEPrgWrData(EEPrgDataRg'range);
end if;
-- EEPROM Write
case EEWr_Int is
when '0' =>
if((ChipEraseStart='1' and ChipEraseStartDel='0') or EEWrCnt="11") then
EEWr_Int <= '1';
end if;
when '1' =>
if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then
EEWr_Int <= '0';
end if;
when others => EEWr_Int <= '0';
end case;
-- EEPROM Read state
if(EERdCnt="11") then
EERd_St <= '1';
else
EERd_St <= '0';
end if;
end if;
end process;
-- "Flash" write enables
pm_l_we <= pm_l_we_Int;
pm_h_we <= pm_h_we_Int;
-- "Flash" data inputs
pm_din <= FlashPrgDataRg;
-- EEPROM
EEAdr <= EEPrgAdrRg;
EEWrData <= EEPrgDataRg;
EEWr <= EEWr_Int;
EEPrgSel <= ProgEnable; -- !!!TBD!!! (Add EESAVE)
-- Flash read
FlashReadCntAndCtrl:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge)
-- Edge detectors
FlRdMStartDel <= FlRdMStart;
FlRdSStartDel <= FlRdSStart;
-- EEPROM edge detectors
EEWrStartDel <= EEWrStart;
EERdStartDel <= EERdStart;
-- Delay counter (for read)
if(TAPCtrlTLR='1') then -- Reset counter
FlRdCnt <= (others => '0');
elsif((FlRdMStart='0' and FlRdMStartDel='1')or
(FlRdSStart='0' and FlRdSStartDel='1')) then
FlRdCnt <= "01";
elsif(FlRdCnt/="00") then
FlRdCnt <= FlRdCnt + 1;
end if;
if(FlRdCnt="11") then
FlRd_St <= '1';
else
FlRd_St <= '0';
end if;
if(FlRd_St='1') then -- Latch read data
FlPrgRdData <= pm_dout;
end if;
-- EEPROM Read delay counter
if(TAPCtrlTLR='1') then -- Reset counter
EERdCnt <= (others => '0');
elsif(EERdStart='0' and EERdStartDel='1') then -- Falling edge
EERdCnt <= "01";
elsif(EERdCnt/="00") then
EERdCnt <= EERdCnt + 1;
end if;
-- EEPROM Write delay counter
if(TAPCtrlTLR='1') then -- Reset counter
EEWrCnt <= (others => '0');
elsif(EEWrStart='0' and EEWrStartDel='1') then -- Falling edge
EEWrCnt <= "01";
elsif(EEWrCnt/="00") then
EEWrCnt <= EEWrCnt + 1;
end if;
-- EEPROM Read latch
if(EERd_St='1') then
EEPrgRdData <= EERdData;
end if;
end if;
end process;
-- Chip Erase
ChipEraseState:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge)
ChipEraseStartDel <= ChipEraseStart; -- Edge detector
if (TAPCtrlTLR='1') then -- Reset
ChipErase_St <= '0';
else
case ChipErase_St is
when '0' =>
if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase
ChipErase_St <= '1';
end if;
when '1' =>
if (FlashPrgAdrRg=C_MaxEraseAdr) then
ChipErase_St <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- !!!TBD!!!
ChipEraseDone <= not ChipErase_St;
-- *************************** End of programmer part *******************************
pm_adr <= FlashPrgAdrRg when (ProgEnable='1') else -- Programming Mode
PC; -- Normal Operations
end RTL;

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src/AVR8/JTAG_OCD_Prg/Resync16b_TCK.vhd Normal file
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--**********************************************************************************************
-- Resynchronizer(16 bit,TCK clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync16b_TCK is port(
TCK : in std_logic;
DIn : in std_logic_vector(15 downto 0);
DOut : out std_logic_vector(15 downto 0)
);
end Resync16b_TCK;
architecture RTL of Resync16b_TCK is
signal DIn_Tmp : std_logic_vector(DIn'range);
begin
ResynchronizerStageOne:process(TCK)
begin
if(TCK='0' and TCK'event) then -- Clock(Falling edge)
DIn_Tmp <= DIn; -- Stage 1
end if;
end process;
ResynchronizerStageTwo:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(Rising edge)
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;

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src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd Normal file
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--**********************************************************************************************
-- Resynchronizer(1 bit,TCK clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync1b_TCK is port(
TCK : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end Resync1b_TCK;
architecture RTL of Resync1b_TCK is
signal DIn_Tmp : std_logic;
begin
ResynchronizerStageOne:process(TCK)
begin
if(TCK='0' and TCK'event) then -- Clock(Falling edge)
DIn_Tmp <= DIn; -- Stage 1
end if;
end process;
ResynchronizerStageTwo:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(Rising edge)
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;

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--**********************************************************************************************
-- Resynchronizer(1 bit,cp2 clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end Resync1b_cp2;
architecture RTL of Resync1b_cp2 is
signal DIn_Tmp : std_logic;
begin
ResynchronizerDFFs:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock
DIn_Tmp <= DIn; -- Stage 1
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;

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--************************************************************************************************
-- Arrbiter and Address/Data multiplexer for AVR core
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 27.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.MemAccessCtrlPack.all;
entity ArbiterAndMux is port(
--Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Bus masters
busmin : in MastersOutBus_Type;
busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0);
-- Memory Address,Data and Control
ramadr : out std_logic_vector(15 downto 0);
ramdout : out std_logic_vector(7 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic
);
end ArbiterAndMux;
architecture RTL of ArbiterAndMux is
signal sel_mast : std_logic_vector(CNumOfBusMasters-1 downto 0);
signal sel_mast_rg : std_logic_vector(sel_mast'range);
constant c_zero_vect : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0');
begin
StoreBusMNum:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
sel_mast_rg <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(cpuwait='1') then -- Store selected bus master number
sel_mast_rg <= sel_mast;
end if;
end if;
end process;
-- Fixed priority arbitration
ArbitrationComb:process(busmin) -- Combinatorial
begin
sel_mast <= (others => '0');
for i in 0 to CNumOfBusMasters-1 loop
if(busmin(i).ramre='1' or busmin(i).ramwe='1') then
sel_mast(i) <= '1';
exit;
end if;
end loop;
end process;
MuxComb:process(busmin,sel_mast,sel_mast_rg,cpuwait) -- Combinatorial
begin
ramadr <= (others => '0');
ramdout <= (others => '0');
ramre <= '0';
ramwe <= '0';
for i in 0 to CNumOfBusMasters-1 loop
if(cpuwait='1') then
if(sel_mast_rg(i)='1') then
ramadr <= busmin(i).ramadr;
ramdout <= busmin(i).dout;
ramre <= busmin(i).ramre;
ramwe <= busmin(i).ramwe;
end if;
else -- cpuwait='0'
if(sel_mast(i)='1') then
ramadr <= busmin(i).ramadr;
ramdout <= busmin(i).dout;
ramre <= busmin(i).ramre;
ramwe <= busmin(i).ramwe;
end if;
end if;
end loop;
end process;
WaitGenComb:process(cpuwait,busmin,sel_mast) -- Combinatorial
begin
busmwait <= (others => '0');
if((busmin(busmwait'low).ramre='1' or busmin(busmwait'low).ramwe='1') and cpuwait='1') then
busmwait(busmwait'low) <= '1';
end if;
for i in 1 to CNumOfBusMasters-1 loop
if((busmin(i).ramre='1' or busmin(i).ramwe='1')and(sel_mast(i-1 downto 0)/=c_zero_vect(i-1 downto 0) or cpuwait='1')) then
busmwait(i) <= '1';
end if;
end loop;
end process;
-- For the purpose of test only
--ramdout(sel_mast'range) <= sel_mast;
-- For the purpose of test only
end RTL;

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-- *****************************************************************************************
--
-- Version 0.1
-- Modified 24.07.2005
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.MemAccessCtrlPack.all;
package MemAccessCompPack is
component ArbiterAndMux is port(
--Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Bus masters
busmin : in MastersOutBus_Type;
busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0);
-- Memory Address,Data and Control
ramadr : out std_logic_vector(15 downto 0);
ramdout : out std_logic_vector(7 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic
);
end component;
component MemRdMux is port(
slv_outs : in SlavesOutBus_Type;
ram_sel : in std_logic; -- Data RAM selection(optional input)
ram_dout : in std_logic_vector(7 downto 0); -- Data memory output
dout : out std_logic_vector(7 downto 0) -- Data output
);
end component;
component RAMAdrDcd is port(
ramadr : in std_logic_vector(15 downto 0);
ramre : in std_logic;
ramwe : in std_logic;
-- Memory mapped I/O i/f
stb_IO : out std_logic;
stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0);
-- Data memory i/f
ram_we : out std_logic;
ram_ce : out std_logic;
ram_sel : out std_logic
);
end component;
end MemAccessCompPack;

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-- *****************************************************************************************
--
-- Version 0.14
-- Modified 02.08.2005
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package MemAccessCtrlPack is
constant CNumOfBusMasters : positive := 3;
constant CNumOfSlaves : positive := 2;
constant CUseRAMSel : boolean := FALSE;
-- Masters
type MastOutBus_Type is record
ramadr : std_logic_vector(15 downto 0);
dout : std_logic_vector(7 downto 0);
ramre : std_logic;
ramwe : std_logic;
end record;
type MastersOutBus_Type is array(CNumOfBusMasters-1 downto 0) of MastOutBus_Type;
-- Slave
type SlvOutBus_Type is record
dout : std_logic_vector(7 downto 0);
out_en : std_logic;
end record;
type SlavesOutBus_Type is array(CNumOfSlaves-1 downto 0) of SlvOutBus_Type;
-- Memory address decoder
constant CMemMappedIOBaseAdr : std_logic_vector(3 downto 0) := x"D";
constant CDRAMBaseAdr : std_logic_vector(1 downto 0) := "00";
end MemAccessCtrlPack;

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--************************************************************************************************
--
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified 24.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.MemAccessCtrlPack.all;
entity MemRdMux is port(
slv_outs : in SlavesOutBus_Type;
ram_sel : in std_logic; -- Data RAM selection(optional input)
ram_dout : in std_logic_vector(7 downto 0); -- Data memory output
dout : out std_logic_vector(7 downto 0) -- Data output
);
end MemRdMux;
architecture RTL of MemRdMux is
constant c_zero_vect : std_logic_vector(CNumOfSlaves-1 downto 0) := (others => '0');
signal slv_data_out : std_logic_vector(dout'range);
--CUseRAMSel
begin
SlvSelOutMux:process(slv_outs) -- Combinatorial
begin
slv_data_out <= (others => '0');
for i in 0 to CNumOfSlaves-1 loop
if(slv_outs(i).out_en='1') then
slv_data_out <= slv_outs(i).dout;
exit;
end if;
end loop;
end process;
RamSelIsNotUsed:if not CUseRAMSel generate
OutMux:process(slv_outs,slv_data_out,ram_dout) -- Combinatorial
begin
dout <= ram_dout;
for i in 0 to CNumOfSlaves-1 loop
if(slv_outs(i).out_en='1') then
dout <= slv_data_out;
exit;
end if;
end loop;
end process;
end generate;
RamSelIsUsed:if CUseRAMSel generate
dout <= ram_dout when (ram_sel='1') else slv_data_out;
end generate;
end RTL;

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--************************************************************************************************
-- Address decoder
-- Version 0.11A
-- Designed by Ruslan Lepetenok
-- Modified 31.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.MemAccessCtrlPack.all;
entity RAMAdrDcd is port(
ramadr : in std_logic_vector(15 downto 0);
ramre : in std_logic;
ramwe : in std_logic;
-- Memory mapped I/O i/f
stb_IO : out std_logic;
stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0);
-- Data memory i/f
ram_we : out std_logic;
ram_ce : out std_logic;
ram_sel : out std_logic
);
end RAMAdrDcd;
architecture RTL of RAMAdrDcd is
signal ram_sel_int : std_logic;
begin
stb_IO <= '1' when (ramadr(ramadr'high downto ramadr'high-CMemMappedIOBaseAdr'high) = CMemMappedIOBaseAdr) else '0';
--MMIOAdrDcd:process(ramadr)
--begin
-- stb_IOmod <= (others => '0');
-- for i in 0 to CNumOfSlaves-1 loop
-- if(ramadr(7 downto 4)=i) then
-- stb_IOmod(i) <= '1';
-- end if;
-- end loop;
--end process;
-- For the purpose of test only
--stb_IOmod(0) <= '1' when ramadr(15 downto 4)=x"017" else '0';
--stb_IOmod(1) <= '1' when ramadr(15 downto 4)=x"018" else '0';
stb_IOmod(0) <= '1' when ramadr(7 downto 4)=x"0" else '0';
stb_IOmod(1) <= '1' when ramadr(7 downto 4)=x"1" else '0';
-- For the purpose of test only
-- RAM i/f
ram_sel_int <= '1'when (ramadr(ramadr'high downto ramadr'high-CDRAMBaseAdr'high) = CDRAMBaseAdr) else '0';
ram_sel <= ram_sel_int;
ram_we <= ram_sel_int and ramwe;
ram_ce <= ram_sel_int and (ramwe or ramre);
end RTL;

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--************************************************************************************************
-- 16Kx8(16 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 30.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XDM16Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM16Kx8;
architecture RTL of XDM16Kx8 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-9)-1 downto 0);
signal cp2n : std_logic;
signal gnd : std_logic;
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_Byte:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(8 downto 0),
DI => din(7 downto 0),
EN => ce,
CLK => cp2,
WE => WEB(i),
RST => gnd
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;

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--************************************************************************************************
-- 32Kx8(32 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified 29.10.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XDM32Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(14 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM32Kx8;
architecture RTL of XDM32Kx8 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-9)-1 downto 0);
signal cp2n : std_logic;
signal gnd : std_logic;
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_Byte:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(8 downto 0),
DI => din(7 downto 0),
EN => ce,
CLK => cp2,
WE => WEB(i),
RST => gnd
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;

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--************************************************************************************************
-- 4Kx8(16 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Jack Gassett for use with Papilio
-- Modified 30.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XDM4Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CDATAMEMSIZE downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM4Kx8;
architecture RTL of XDM4Kx8 is
type RAMBlDOut_Type is array(2**(address'length-11)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-11)-1 downto 0);
signal cp2n : std_logic;
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 11)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-11)-1 generate
RAM_Byte:component RAMB16_S9 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(10 downto 0),
DI => din(7 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(i)
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 11)));
end RTL;

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--************************************************************************************************
-- PM/DM memory components declarations for AVR core (Xilinx)
-- Version 0.4
-- Designed by Ruslan Lepetenok
-- Modified 29.10.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package XMemCompPack is
component XPM16Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
weh : in std_logic;
wel : in std_logic
);
end component;
component XDM16Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end component;
component XDM32Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(14 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end component;
-- XPM8Kx16 was moved to the top level
component XPM4Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(11 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end component;
-- XDM4Kx8 was moved to the top level
end XMemCompPack;

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--************************************************************************************************
-- 8Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified by Jack Gassett for use with Papilio
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.prog_mem_init_pkg.all; -- Init file for program memory.
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM10Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM10Kx16;
architecture RTL of XPM10Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
--RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word0:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word0_INIT_00,
INIT_01 => PM_Inst_RAM_Word0_INIT_01,
INIT_02 => PM_Inst_RAM_Word0_INIT_02,
INIT_03 => PM_Inst_RAM_Word0_INIT_03,
INIT_04 => PM_Inst_RAM_Word0_INIT_04,
INIT_05 => PM_Inst_RAM_Word0_INIT_05,
INIT_06 => PM_Inst_RAM_Word0_INIT_06,
INIT_07 => PM_Inst_RAM_Word0_INIT_07,
INIT_08 => PM_Inst_RAM_Word0_INIT_08,
INIT_09 => PM_Inst_RAM_Word0_INIT_09,
INIT_0A => PM_Inst_RAM_Word0_INIT_0A,
INIT_0B => PM_Inst_RAM_Word0_INIT_0B,
INIT_0C => PM_Inst_RAM_Word0_INIT_0C,
INIT_0D => PM_Inst_RAM_Word0_INIT_0D,
INIT_0E => PM_Inst_RAM_Word0_INIT_0E,
INIT_0F => PM_Inst_RAM_Word0_INIT_0F,
INIT_10 => PM_Inst_RAM_Word0_INIT_10,
INIT_11 => PM_Inst_RAM_Word0_INIT_11,
INIT_12 => PM_Inst_RAM_Word0_INIT_12,
INIT_13 => PM_Inst_RAM_Word0_INIT_13,
INIT_14 => PM_Inst_RAM_Word0_INIT_14,
INIT_15 => PM_Inst_RAM_Word0_INIT_15,
INIT_16 => PM_Inst_RAM_Word0_INIT_16,
INIT_17 => PM_Inst_RAM_Word0_INIT_17,
INIT_18 => PM_Inst_RAM_Word0_INIT_18,
INIT_19 => PM_Inst_RAM_Word0_INIT_19,
INIT_1A => PM_Inst_RAM_Word0_INIT_1A,
INIT_1B => PM_Inst_RAM_Word0_INIT_1B,
INIT_1C => PM_Inst_RAM_Word0_INIT_1C,
INIT_1D => PM_Inst_RAM_Word0_INIT_1D,
INIT_1E => PM_Inst_RAM_Word0_INIT_1E,
INIT_1F => PM_Inst_RAM_Word0_INIT_1F,
INIT_20 => PM_Inst_RAM_Word0_INIT_20,
INIT_21 => PM_Inst_RAM_Word0_INIT_21,
INIT_22 => PM_Inst_RAM_Word0_INIT_22,
INIT_23 => PM_Inst_RAM_Word0_INIT_23,
INIT_24 => PM_Inst_RAM_Word0_INIT_24,
INIT_25 => PM_Inst_RAM_Word0_INIT_25,
INIT_26 => PM_Inst_RAM_Word0_INIT_26,
INIT_27 => PM_Inst_RAM_Word0_INIT_27,
INIT_28 => PM_Inst_RAM_Word0_INIT_28,
INIT_29 => PM_Inst_RAM_Word0_INIT_29,
INIT_2A => PM_Inst_RAM_Word0_INIT_2A,
INIT_2B => PM_Inst_RAM_Word0_INIT_2B,
INIT_2C => PM_Inst_RAM_Word0_INIT_2C,
INIT_2D => PM_Inst_RAM_Word0_INIT_2D,
INIT_2E => PM_Inst_RAM_Word0_INIT_2E,
INIT_2F => PM_Inst_RAM_Word0_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word0_INIT_30,
INIT_31 => PM_Inst_RAM_Word0_INIT_31,
INIT_32 => PM_Inst_RAM_Word0_INIT_32,
INIT_33 => PM_Inst_RAM_Word0_INIT_33,
INIT_34 => PM_Inst_RAM_Word0_INIT_34,
INIT_35 => PM_Inst_RAM_Word0_INIT_35,
INIT_36 => PM_Inst_RAM_Word0_INIT_36,
INIT_37 => PM_Inst_RAM_Word0_INIT_37,
INIT_38 => PM_Inst_RAM_Word0_INIT_38,
INIT_39 => PM_Inst_RAM_Word0_INIT_39,
INIT_3A => PM_Inst_RAM_Word0_INIT_3A,
INIT_3B => PM_Inst_RAM_Word0_INIT_3B,
INIT_3C => PM_Inst_RAM_Word0_INIT_3C,
INIT_3D => PM_Inst_RAM_Word0_INIT_3D,
INIT_3E => PM_Inst_RAM_Word0_INIT_3E,
INIT_3F => PM_Inst_RAM_Word0_INIT_3F
)
port map(
DO => RAMBlDOut(0)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(0)
);
RAM_Word1:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word1_INIT_00,
INIT_01 => PM_Inst_RAM_Word1_INIT_01,
INIT_02 => PM_Inst_RAM_Word1_INIT_02,
INIT_03 => PM_Inst_RAM_Word1_INIT_03,
INIT_04 => PM_Inst_RAM_Word1_INIT_04,
INIT_05 => PM_Inst_RAM_Word1_INIT_05,
INIT_06 => PM_Inst_RAM_Word1_INIT_06,
INIT_07 => PM_Inst_RAM_Word1_INIT_07,
INIT_08 => PM_Inst_RAM_Word1_INIT_08,
INIT_09 => PM_Inst_RAM_Word1_INIT_09,
INIT_0A => PM_Inst_RAM_Word1_INIT_0A,
INIT_0B => PM_Inst_RAM_Word1_INIT_0B,
INIT_0C => PM_Inst_RAM_Word1_INIT_0C,
INIT_0D => PM_Inst_RAM_Word1_INIT_0D,
INIT_0E => PM_Inst_RAM_Word1_INIT_0E,
INIT_0F => PM_Inst_RAM_Word1_INIT_0F,
INIT_10 => PM_Inst_RAM_Word1_INIT_10,
INIT_11 => PM_Inst_RAM_Word1_INIT_11,
INIT_12 => PM_Inst_RAM_Word1_INIT_12,
INIT_13 => PM_Inst_RAM_Word1_INIT_13,
INIT_14 => PM_Inst_RAM_Word1_INIT_14,
INIT_15 => PM_Inst_RAM_Word1_INIT_15,
INIT_16 => PM_Inst_RAM_Word1_INIT_16,
INIT_17 => PM_Inst_RAM_Word1_INIT_17,
INIT_18 => PM_Inst_RAM_Word1_INIT_18,
INIT_19 => PM_Inst_RAM_Word1_INIT_19,
INIT_1A => PM_Inst_RAM_Word1_INIT_1A,
INIT_1B => PM_Inst_RAM_Word1_INIT_1B,
INIT_1C => PM_Inst_RAM_Word1_INIT_1C,
INIT_1D => PM_Inst_RAM_Word1_INIT_1D,
INIT_1E => PM_Inst_RAM_Word1_INIT_1E,
INIT_1F => PM_Inst_RAM_Word1_INIT_1F,
INIT_20 => PM_Inst_RAM_Word1_INIT_20,
INIT_21 => PM_Inst_RAM_Word1_INIT_21,
INIT_22 => PM_Inst_RAM_Word1_INIT_22,
INIT_23 => PM_Inst_RAM_Word1_INIT_23,
INIT_24 => PM_Inst_RAM_Word1_INIT_24,
INIT_25 => PM_Inst_RAM_Word1_INIT_25,
INIT_26 => PM_Inst_RAM_Word1_INIT_26,
INIT_27 => PM_Inst_RAM_Word1_INIT_27,
INIT_28 => PM_Inst_RAM_Word1_INIT_28,
INIT_29 => PM_Inst_RAM_Word1_INIT_29,
INIT_2A => PM_Inst_RAM_Word1_INIT_2A,
INIT_2B => PM_Inst_RAM_Word1_INIT_2B,
INIT_2C => PM_Inst_RAM_Word1_INIT_2C,
INIT_2D => PM_Inst_RAM_Word1_INIT_2D,
INIT_2E => PM_Inst_RAM_Word1_INIT_2E,
INIT_2F => PM_Inst_RAM_Word1_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word1_INIT_30,
INIT_31 => PM_Inst_RAM_Word1_INIT_31,
INIT_32 => PM_Inst_RAM_Word1_INIT_32,
INIT_33 => PM_Inst_RAM_Word1_INIT_33,
INIT_34 => PM_Inst_RAM_Word1_INIT_34,
INIT_35 => PM_Inst_RAM_Word1_INIT_35,
INIT_36 => PM_Inst_RAM_Word1_INIT_36,
INIT_37 => PM_Inst_RAM_Word1_INIT_37,
INIT_38 => PM_Inst_RAM_Word1_INIT_38,
INIT_39 => PM_Inst_RAM_Word1_INIT_39,
INIT_3A => PM_Inst_RAM_Word1_INIT_3A,
INIT_3B => PM_Inst_RAM_Word1_INIT_3B,
INIT_3C => PM_Inst_RAM_Word1_INIT_3C,
INIT_3D => PM_Inst_RAM_Word1_INIT_3D,
INIT_3E => PM_Inst_RAM_Word1_INIT_3E,
INIT_3F => PM_Inst_RAM_Word1_INIT_3F
)
port map(
DO => RAMBlDOut(1)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(1)
);
RAM_Word2:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word2_INIT_00,
INIT_01 => PM_Inst_RAM_Word2_INIT_01,
INIT_02 => PM_Inst_RAM_Word2_INIT_02,
INIT_03 => PM_Inst_RAM_Word2_INIT_03,
INIT_04 => PM_Inst_RAM_Word2_INIT_04,
INIT_05 => PM_Inst_RAM_Word2_INIT_05,
INIT_06 => PM_Inst_RAM_Word2_INIT_06,
INIT_07 => PM_Inst_RAM_Word2_INIT_07,
INIT_08 => PM_Inst_RAM_Word2_INIT_08,
INIT_09 => PM_Inst_RAM_Word2_INIT_09,
INIT_0A => PM_Inst_RAM_Word2_INIT_0A,
INIT_0B => PM_Inst_RAM_Word2_INIT_0B,
INIT_0C => PM_Inst_RAM_Word2_INIT_0C,
INIT_0D => PM_Inst_RAM_Word2_INIT_0D,
INIT_0E => PM_Inst_RAM_Word2_INIT_0E,
INIT_0F => PM_Inst_RAM_Word2_INIT_0F,
INIT_10 => PM_Inst_RAM_Word2_INIT_10,
INIT_11 => PM_Inst_RAM_Word2_INIT_11,
INIT_12 => PM_Inst_RAM_Word2_INIT_12,
INIT_13 => PM_Inst_RAM_Word2_INIT_13,
INIT_14 => PM_Inst_RAM_Word2_INIT_14,
INIT_15 => PM_Inst_RAM_Word2_INIT_15,
INIT_16 => PM_Inst_RAM_Word2_INIT_16,
INIT_17 => PM_Inst_RAM_Word2_INIT_17,
INIT_18 => PM_Inst_RAM_Word2_INIT_18,
INIT_19 => PM_Inst_RAM_Word2_INIT_19,
INIT_1A => PM_Inst_RAM_Word2_INIT_1A,
INIT_1B => PM_Inst_RAM_Word2_INIT_1B,
INIT_1C => PM_Inst_RAM_Word2_INIT_1C,
INIT_1D => PM_Inst_RAM_Word2_INIT_1D,
INIT_1E => PM_Inst_RAM_Word2_INIT_1E,
INIT_1F => PM_Inst_RAM_Word2_INIT_1F,
INIT_20 => PM_Inst_RAM_Word2_INIT_20,
INIT_21 => PM_Inst_RAM_Word2_INIT_21,
INIT_22 => PM_Inst_RAM_Word2_INIT_22,
INIT_23 => PM_Inst_RAM_Word2_INIT_23,
INIT_24 => PM_Inst_RAM_Word2_INIT_24,
INIT_25 => PM_Inst_RAM_Word2_INIT_25,
INIT_26 => PM_Inst_RAM_Word2_INIT_26,
INIT_27 => PM_Inst_RAM_Word2_INIT_27,
INIT_28 => PM_Inst_RAM_Word2_INIT_28,
INIT_29 => PM_Inst_RAM_Word2_INIT_29,
INIT_2A => PM_Inst_RAM_Word2_INIT_2A,
INIT_2B => PM_Inst_RAM_Word2_INIT_2B,
INIT_2C => PM_Inst_RAM_Word2_INIT_2C,
INIT_2D => PM_Inst_RAM_Word2_INIT_2D,
INIT_2E => PM_Inst_RAM_Word2_INIT_2E,
INIT_2F => PM_Inst_RAM_Word2_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word2_INIT_30,
INIT_31 => PM_Inst_RAM_Word2_INIT_31,
INIT_32 => PM_Inst_RAM_Word2_INIT_32,
INIT_33 => PM_Inst_RAM_Word2_INIT_33,
INIT_34 => PM_Inst_RAM_Word2_INIT_34,
INIT_35 => PM_Inst_RAM_Word2_INIT_35,
INIT_36 => PM_Inst_RAM_Word2_INIT_36,
INIT_37 => PM_Inst_RAM_Word2_INIT_37,
INIT_38 => PM_Inst_RAM_Word2_INIT_38,
INIT_39 => PM_Inst_RAM_Word2_INIT_39,
INIT_3A => PM_Inst_RAM_Word2_INIT_3A,
INIT_3B => PM_Inst_RAM_Word2_INIT_3B,
INIT_3C => PM_Inst_RAM_Word2_INIT_3C,
INIT_3D => PM_Inst_RAM_Word2_INIT_3D,
INIT_3E => PM_Inst_RAM_Word2_INIT_3E,
INIT_3F => PM_Inst_RAM_Word2_INIT_3F
)
port map(
DO => RAMBlDOut(2)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(2)
);
RAM_Word3:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word3_INIT_00,
INIT_01 => PM_Inst_RAM_Word3_INIT_01,
INIT_02 => PM_Inst_RAM_Word3_INIT_02,
INIT_03 => PM_Inst_RAM_Word3_INIT_03,
INIT_04 => PM_Inst_RAM_Word3_INIT_04,
INIT_05 => PM_Inst_RAM_Word3_INIT_05,
INIT_06 => PM_Inst_RAM_Word3_INIT_06,
INIT_07 => PM_Inst_RAM_Word3_INIT_07,
INIT_08 => PM_Inst_RAM_Word3_INIT_08,
INIT_09 => PM_Inst_RAM_Word3_INIT_09,
INIT_0A => PM_Inst_RAM_Word3_INIT_0A,
INIT_0B => PM_Inst_RAM_Word3_INIT_0B,
INIT_0C => PM_Inst_RAM_Word3_INIT_0C,
INIT_0D => PM_Inst_RAM_Word3_INIT_0D,
INIT_0E => PM_Inst_RAM_Word3_INIT_0E,
INIT_0F => PM_Inst_RAM_Word3_INIT_0F,
INIT_10 => PM_Inst_RAM_Word3_INIT_10,
INIT_11 => PM_Inst_RAM_Word3_INIT_11,
INIT_12 => PM_Inst_RAM_Word3_INIT_12,
INIT_13 => PM_Inst_RAM_Word3_INIT_13,
INIT_14 => PM_Inst_RAM_Word3_INIT_14,
INIT_15 => PM_Inst_RAM_Word3_INIT_15,
INIT_16 => PM_Inst_RAM_Word3_INIT_16,
INIT_17 => PM_Inst_RAM_Word3_INIT_17,
INIT_18 => PM_Inst_RAM_Word3_INIT_18,
INIT_19 => PM_Inst_RAM_Word3_INIT_19,
INIT_1A => PM_Inst_RAM_Word3_INIT_1A,
INIT_1B => PM_Inst_RAM_Word3_INIT_1B,
INIT_1C => PM_Inst_RAM_Word3_INIT_1C,
INIT_1D => PM_Inst_RAM_Word3_INIT_1D,
INIT_1E => PM_Inst_RAM_Word3_INIT_1E,
INIT_1F => PM_Inst_RAM_Word3_INIT_1F,
INIT_20 => PM_Inst_RAM_Word3_INIT_20,
INIT_21 => PM_Inst_RAM_Word3_INIT_21,
INIT_22 => PM_Inst_RAM_Word3_INIT_22,
INIT_23 => PM_Inst_RAM_Word3_INIT_23,
INIT_24 => PM_Inst_RAM_Word3_INIT_24,
INIT_25 => PM_Inst_RAM_Word3_INIT_25,
INIT_26 => PM_Inst_RAM_Word3_INIT_26,
INIT_27 => PM_Inst_RAM_Word3_INIT_27,
INIT_28 => PM_Inst_RAM_Word3_INIT_28,
INIT_29 => PM_Inst_RAM_Word3_INIT_29,
INIT_2A => PM_Inst_RAM_Word3_INIT_2A,
INIT_2B => PM_Inst_RAM_Word3_INIT_2B,
INIT_2C => PM_Inst_RAM_Word3_INIT_2C,
INIT_2D => PM_Inst_RAM_Word3_INIT_2D,
INIT_2E => PM_Inst_RAM_Word3_INIT_2E,
INIT_2F => PM_Inst_RAM_Word3_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word3_INIT_30,
INIT_31 => PM_Inst_RAM_Word3_INIT_31,
INIT_32 => PM_Inst_RAM_Word3_INIT_32,
INIT_33 => PM_Inst_RAM_Word3_INIT_33,
INIT_34 => PM_Inst_RAM_Word3_INIT_34,
INIT_35 => PM_Inst_RAM_Word3_INIT_35,
INIT_36 => PM_Inst_RAM_Word3_INIT_36,
INIT_37 => PM_Inst_RAM_Word3_INIT_37,
INIT_38 => PM_Inst_RAM_Word3_INIT_38,
INIT_39 => PM_Inst_RAM_Word3_INIT_39,
INIT_3A => PM_Inst_RAM_Word3_INIT_3A,
INIT_3B => PM_Inst_RAM_Word3_INIT_3B,
INIT_3C => PM_Inst_RAM_Word3_INIT_3C,
INIT_3D => PM_Inst_RAM_Word3_INIT_3D,
INIT_3E => PM_Inst_RAM_Word3_INIT_3E,
INIT_3F => PM_Inst_RAM_Word3_INIT_3F
)
port map(
DO => RAMBlDOut(3)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(3)
);
RAM_Word4:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word4_INIT_00,
INIT_01 => PM_Inst_RAM_Word4_INIT_01,
INIT_02 => PM_Inst_RAM_Word4_INIT_02,
INIT_03 => PM_Inst_RAM_Word4_INIT_03,
INIT_04 => PM_Inst_RAM_Word4_INIT_04,
INIT_05 => PM_Inst_RAM_Word4_INIT_05,
INIT_06 => PM_Inst_RAM_Word4_INIT_06,
INIT_07 => PM_Inst_RAM_Word4_INIT_07,
INIT_08 => PM_Inst_RAM_Word4_INIT_08,
INIT_09 => PM_Inst_RAM_Word4_INIT_09,
INIT_0A => PM_Inst_RAM_Word4_INIT_0A,
INIT_0B => PM_Inst_RAM_Word4_INIT_0B,
INIT_0C => PM_Inst_RAM_Word4_INIT_0C,
INIT_0D => PM_Inst_RAM_Word4_INIT_0D,
INIT_0E => PM_Inst_RAM_Word4_INIT_0E,
INIT_0F => PM_Inst_RAM_Word4_INIT_0F,
INIT_10 => PM_Inst_RAM_Word4_INIT_10,
INIT_11 => PM_Inst_RAM_Word4_INIT_11,
INIT_12 => PM_Inst_RAM_Word4_INIT_12,
INIT_13 => PM_Inst_RAM_Word4_INIT_13,
INIT_14 => PM_Inst_RAM_Word4_INIT_14,
INIT_15 => PM_Inst_RAM_Word4_INIT_15,
INIT_16 => PM_Inst_RAM_Word4_INIT_16,
INIT_17 => PM_Inst_RAM_Word4_INIT_17,
INIT_18 => PM_Inst_RAM_Word4_INIT_18,
INIT_19 => PM_Inst_RAM_Word4_INIT_19,
INIT_1A => PM_Inst_RAM_Word4_INIT_1A,
INIT_1B => PM_Inst_RAM_Word4_INIT_1B,
INIT_1C => PM_Inst_RAM_Word4_INIT_1C,
INIT_1D => PM_Inst_RAM_Word4_INIT_1D,
INIT_1E => PM_Inst_RAM_Word4_INIT_1E,
INIT_1F => PM_Inst_RAM_Word4_INIT_1F,
INIT_20 => PM_Inst_RAM_Word4_INIT_20,
INIT_21 => PM_Inst_RAM_Word4_INIT_21,
INIT_22 => PM_Inst_RAM_Word4_INIT_22,
INIT_23 => PM_Inst_RAM_Word4_INIT_23,
INIT_24 => PM_Inst_RAM_Word4_INIT_24,
INIT_25 => PM_Inst_RAM_Word4_INIT_25,
INIT_26 => PM_Inst_RAM_Word4_INIT_26,
INIT_27 => PM_Inst_RAM_Word4_INIT_27,
INIT_28 => PM_Inst_RAM_Word4_INIT_28,
INIT_29 => PM_Inst_RAM_Word4_INIT_29,
INIT_2A => PM_Inst_RAM_Word4_INIT_2A,
INIT_2B => PM_Inst_RAM_Word4_INIT_2B,
INIT_2C => PM_Inst_RAM_Word4_INIT_2C,
INIT_2D => PM_Inst_RAM_Word4_INIT_2D,
INIT_2E => PM_Inst_RAM_Word4_INIT_2E,
INIT_2F => PM_Inst_RAM_Word4_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word4_INIT_30,
INIT_31 => PM_Inst_RAM_Word4_INIT_31,
INIT_32 => PM_Inst_RAM_Word4_INIT_32,
INIT_33 => PM_Inst_RAM_Word4_INIT_33,
INIT_34 => PM_Inst_RAM_Word4_INIT_34,
INIT_35 => PM_Inst_RAM_Word4_INIT_35,
INIT_36 => PM_Inst_RAM_Word4_INIT_36,
INIT_37 => PM_Inst_RAM_Word4_INIT_37,
INIT_38 => PM_Inst_RAM_Word4_INIT_38,
INIT_39 => PM_Inst_RAM_Word4_INIT_39,
INIT_3A => PM_Inst_RAM_Word4_INIT_3A,
INIT_3B => PM_Inst_RAM_Word4_INIT_3B,
INIT_3C => PM_Inst_RAM_Word4_INIT_3C,
INIT_3D => PM_Inst_RAM_Word4_INIT_3D,
INIT_3E => PM_Inst_RAM_Word4_INIT_3E,
INIT_3F => PM_Inst_RAM_Word4_INIT_3F
)
port map(
DO => RAMBlDOut(4)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(4)
);
RAM_Word5:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word5_INIT_00,
INIT_01 => PM_Inst_RAM_Word5_INIT_01,
INIT_02 => PM_Inst_RAM_Word5_INIT_02,
INIT_03 => PM_Inst_RAM_Word5_INIT_03,
INIT_04 => PM_Inst_RAM_Word5_INIT_04,
INIT_05 => PM_Inst_RAM_Word5_INIT_05,
INIT_06 => PM_Inst_RAM_Word5_INIT_06,
INIT_07 => PM_Inst_RAM_Word5_INIT_07,
INIT_08 => PM_Inst_RAM_Word5_INIT_08,
INIT_09 => PM_Inst_RAM_Word5_INIT_09,
INIT_0A => PM_Inst_RAM_Word5_INIT_0A,
INIT_0B => PM_Inst_RAM_Word5_INIT_0B,
INIT_0C => PM_Inst_RAM_Word5_INIT_0C,
INIT_0D => PM_Inst_RAM_Word5_INIT_0D,
INIT_0E => PM_Inst_RAM_Word5_INIT_0E,
INIT_0F => PM_Inst_RAM_Word5_INIT_0F,
INIT_10 => PM_Inst_RAM_Word5_INIT_10,
INIT_11 => PM_Inst_RAM_Word5_INIT_11,
INIT_12 => PM_Inst_RAM_Word5_INIT_12,
INIT_13 => PM_Inst_RAM_Word5_INIT_13,
INIT_14 => PM_Inst_RAM_Word5_INIT_14,
INIT_15 => PM_Inst_RAM_Word5_INIT_15,
INIT_16 => PM_Inst_RAM_Word5_INIT_16,
INIT_17 => PM_Inst_RAM_Word5_INIT_17,
INIT_18 => PM_Inst_RAM_Word5_INIT_18,
INIT_19 => PM_Inst_RAM_Word5_INIT_19,
INIT_1A => PM_Inst_RAM_Word5_INIT_1A,
INIT_1B => PM_Inst_RAM_Word5_INIT_1B,
INIT_1C => PM_Inst_RAM_Word5_INIT_1C,
INIT_1D => PM_Inst_RAM_Word5_INIT_1D,
INIT_1E => PM_Inst_RAM_Word5_INIT_1E,
INIT_1F => PM_Inst_RAM_Word5_INIT_1F,
INIT_20 => PM_Inst_RAM_Word5_INIT_20,
INIT_21 => PM_Inst_RAM_Word5_INIT_21,
INIT_22 => PM_Inst_RAM_Word5_INIT_22,
INIT_23 => PM_Inst_RAM_Word5_INIT_23,
INIT_24 => PM_Inst_RAM_Word5_INIT_24,
INIT_25 => PM_Inst_RAM_Word5_INIT_25,
INIT_26 => PM_Inst_RAM_Word5_INIT_26,
INIT_27 => PM_Inst_RAM_Word5_INIT_27,
INIT_28 => PM_Inst_RAM_Word5_INIT_28,
INIT_29 => PM_Inst_RAM_Word5_INIT_29,
INIT_2A => PM_Inst_RAM_Word5_INIT_2A,
INIT_2B => PM_Inst_RAM_Word5_INIT_2B,
INIT_2C => PM_Inst_RAM_Word5_INIT_2C,
INIT_2D => PM_Inst_RAM_Word5_INIT_2D,
INIT_2E => PM_Inst_RAM_Word5_INIT_2E,
INIT_2F => PM_Inst_RAM_Word5_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word5_INIT_30,
INIT_31 => PM_Inst_RAM_Word5_INIT_31,
INIT_32 => PM_Inst_RAM_Word5_INIT_32,
INIT_33 => PM_Inst_RAM_Word5_INIT_33,
INIT_34 => PM_Inst_RAM_Word5_INIT_34,
INIT_35 => PM_Inst_RAM_Word5_INIT_35,
INIT_36 => PM_Inst_RAM_Word5_INIT_36,
INIT_37 => PM_Inst_RAM_Word5_INIT_37,
INIT_38 => PM_Inst_RAM_Word5_INIT_38,
INIT_39 => PM_Inst_RAM_Word5_INIT_39,
INIT_3A => PM_Inst_RAM_Word5_INIT_3A,
INIT_3B => PM_Inst_RAM_Word5_INIT_3B,
INIT_3C => PM_Inst_RAM_Word5_INIT_3C,
INIT_3D => PM_Inst_RAM_Word5_INIT_3D,
INIT_3E => PM_Inst_RAM_Word5_INIT_3E,
INIT_3F => PM_Inst_RAM_Word5_INIT_3F
)
port map(
DO => RAMBlDOut(5)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(5)
);
RAM_Word6:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word6_INIT_00,
INIT_01 => PM_Inst_RAM_Word6_INIT_01,
INIT_02 => PM_Inst_RAM_Word6_INIT_02,
INIT_03 => PM_Inst_RAM_Word6_INIT_03,
INIT_04 => PM_Inst_RAM_Word6_INIT_04,
INIT_05 => PM_Inst_RAM_Word6_INIT_05,
INIT_06 => PM_Inst_RAM_Word6_INIT_06,
INIT_07 => PM_Inst_RAM_Word6_INIT_07,
INIT_08 => PM_Inst_RAM_Word6_INIT_08,
INIT_09 => PM_Inst_RAM_Word6_INIT_09,
INIT_0A => PM_Inst_RAM_Word6_INIT_0A,
INIT_0B => PM_Inst_RAM_Word6_INIT_0B,
INIT_0C => PM_Inst_RAM_Word6_INIT_0C,
INIT_0D => PM_Inst_RAM_Word6_INIT_0D,
INIT_0E => PM_Inst_RAM_Word6_INIT_0E,
INIT_0F => PM_Inst_RAM_Word6_INIT_0F,
INIT_10 => PM_Inst_RAM_Word6_INIT_10,
INIT_11 => PM_Inst_RAM_Word6_INIT_11,
INIT_12 => PM_Inst_RAM_Word6_INIT_12,
INIT_13 => PM_Inst_RAM_Word6_INIT_13,
INIT_14 => PM_Inst_RAM_Word6_INIT_14,
INIT_15 => PM_Inst_RAM_Word6_INIT_15,
INIT_16 => PM_Inst_RAM_Word6_INIT_16,
INIT_17 => PM_Inst_RAM_Word6_INIT_17,
INIT_18 => PM_Inst_RAM_Word6_INIT_18,
INIT_19 => PM_Inst_RAM_Word6_INIT_19,
INIT_1A => PM_Inst_RAM_Word6_INIT_1A,
INIT_1B => PM_Inst_RAM_Word6_INIT_1B,
INIT_1C => PM_Inst_RAM_Word6_INIT_1C,
INIT_1D => PM_Inst_RAM_Word6_INIT_1D,
INIT_1E => PM_Inst_RAM_Word6_INIT_1E,
INIT_1F => PM_Inst_RAM_Word6_INIT_1F,
INIT_20 => PM_Inst_RAM_Word6_INIT_20,
INIT_21 => PM_Inst_RAM_Word6_INIT_21,
INIT_22 => PM_Inst_RAM_Word6_INIT_22,
INIT_23 => PM_Inst_RAM_Word6_INIT_23,
INIT_24 => PM_Inst_RAM_Word6_INIT_24,
INIT_25 => PM_Inst_RAM_Word6_INIT_25,
INIT_26 => PM_Inst_RAM_Word6_INIT_26,
INIT_27 => PM_Inst_RAM_Word6_INIT_27,
INIT_28 => PM_Inst_RAM_Word6_INIT_28,
INIT_29 => PM_Inst_RAM_Word6_INIT_29,
INIT_2A => PM_Inst_RAM_Word6_INIT_2A,
INIT_2B => PM_Inst_RAM_Word6_INIT_2B,
INIT_2C => PM_Inst_RAM_Word6_INIT_2C,
INIT_2D => PM_Inst_RAM_Word6_INIT_2D,
INIT_2E => PM_Inst_RAM_Word6_INIT_2E,
INIT_2F => PM_Inst_RAM_Word6_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word6_INIT_30,
INIT_31 => PM_Inst_RAM_Word6_INIT_31,
INIT_32 => PM_Inst_RAM_Word6_INIT_32,
INIT_33 => PM_Inst_RAM_Word6_INIT_33,
INIT_34 => PM_Inst_RAM_Word6_INIT_34,
INIT_35 => PM_Inst_RAM_Word6_INIT_35,
INIT_36 => PM_Inst_RAM_Word6_INIT_36,
INIT_37 => PM_Inst_RAM_Word6_INIT_37,
INIT_38 => PM_Inst_RAM_Word6_INIT_38,
INIT_39 => PM_Inst_RAM_Word6_INIT_39,
INIT_3A => PM_Inst_RAM_Word6_INIT_3A,
INIT_3B => PM_Inst_RAM_Word6_INIT_3B,
INIT_3C => PM_Inst_RAM_Word6_INIT_3C,
INIT_3D => PM_Inst_RAM_Word6_INIT_3D,
INIT_3E => PM_Inst_RAM_Word6_INIT_3E,
INIT_3F => PM_Inst_RAM_Word6_INIT_3F
)
port map(
DO => RAMBlDOut(6)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(6)
);
RAM_Word7:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(7)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(7)
);
--end generate;
RAM_Word8:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(8)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(8)
);
--end generate;
RAM_Word9:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(9)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(9)
);
--end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;

81
src/AVR8/Memory/XPM16Kx16.vhd Normal file
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@ -0,0 +1,81 @@
--************************************************************************************************
-- 16Kx16(32 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 30.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM16Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
weh : in std_logic;
wel : in std_logic
);
end XPM16Kx16;
architecture RTL of XPM16Kx16 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEBL : std_logic_vector(2**(address'length-9)-1 downto 0);
signal WEBH : std_logic_vector(2**(address'length-9)-1 downto 0);
signal gnd : std_logic;
begin
gnd <= '0';
WEBH_Dcd:for i in WEBL'range generate
WEBL(i) <= '1' when (wel='1' and address(address'high downto 9)=i) else '0';
end generate ;
WEBL_Dcd:for i in WEBH'range generate
WEBH(i) <= '1' when (weh='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_ByteLow:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(8 downto 0),
DI => din(7 downto 0),
EN => ce,
CLK => cp2,
WE => WEBL(i),
RST => gnd
);
RAM_ByteHigh:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(15 downto 8),
ADDR => address(8 downto 0),
DI => din(15 downto 8),
EN => ce,
CLK => cp2,
WE => WEBH(i),
RST => gnd
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;

156
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@ -0,0 +1,156 @@
--************************************************************************************************
-- 4Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok modified by Jack Gassett for use with Spartan 3E
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM4Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(11 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM4Kx16;
architecture RTL of XPM4Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C005B940C",
INIT_01 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C007E940C",
INIT_02 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C009D940C",
INIT_03 => X"0404040404040030003600000000003200350038000000000031003700000000",
INIT_04 => X"0804020120100804020180402010080402010303030303030202020202020404",
INIT_05 => X"BFDEE0DFEFCFBE1F241100000000000000000604030000010200070000002010",
INIT_06 => X"07B136A2F3C89631920D95D8C004BF0B9503EF0FE0F3E2ECE0B0E6A0E010BFCD",
INIT_07 => X"0000940C0194940C018D940EF7E107B136AB921DC001E0B0E6A2E010BE1BF7C9",
INIT_08 => X"0151940EE0600060918000F5940EE090E080E070E0610151940EE06100609180",
INIT_09 => X"B60F920F921F95080129940EE06100609180950800F5940EE090E080E070E061",
INIT_0A => X"006791300066912093BF93AF939F938F937F936F935F934F933F932F2411920F",
INIT_0B => X"376D5F6A2F671DB11DA196022F822F932FA42FB5006A91700069915000689140",
INIT_0C => X"93A00067939000669380006A93601DB11DA196032F822F932FA42FB5576DF040",
INIT_0D => X"006293801DB11DA19601006591B0006491A00063919000629180006993B00068",
INIT_0E => X"912F913F914F915F916F917F918F919F91AF91BF006593B0006493A000639390",
INIT_0F => X"914094F8B78F2F192F082EF72EE6931F930F92FF92EF9518901F900FBE0F900F",
INIT_10 => X"006891A0006791900066918094F8B72FBF8F0069917000689160006791500066",
INIT_11 => X"90EF90FF910F911FF760071B070A06F916E80BB70BA60B951B84BF2F006991B0",
INIT_12 => X"2FE84F9F57822F932F82E0302F289508BF876081B787BF836084B78394789508",
INIT_13 => X"5AE01FFF0FEEE0F02FE8F0A923882D8095C82FF32FE24F3F58262D9095C82FF9",
INIT_14 => X"938C2B89918C9508938C23899590918CF42923662DB095C896312DA095C84FFF",
INIT_15 => X"2FE84F9F57822F952F842D2095C82FF92FE84F9F558E2F952F84E0502F489508",
INIT_16 => X"B58FF4193023F0512322F10923332D3095C82FF52FE44F5F58462D9095C82FF9",
INIT_17 => X"96312DA095C84FFF59E81FFF0FEEE0F02FE3BD8F7D8FB58FF4193024C004778F",
INIT_18 => X"940E0121940E9508938C2B89918C9508938C23899590918CF42923662DB095C8",
INIT_19 => X"000000000000000000000000000000000000000DCFFF94F8CFFD0080940E0097",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 255
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map(
DO => RAMBlDOut(i)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(i)
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;

735
src/AVR8/Memory/XPM8Kx16.vhd Normal file
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@ -0,0 +1,735 @@
--************************************************************************************************
-- 8Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified by Jack Gassett for use with Papilio
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.prog_mem_init_pkg.all; -- Init file for program memory.
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM8Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CPROGMEMSIZE downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM8Kx16;
architecture RTL of XPM8Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
--RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word0:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word0_INIT_00,
INIT_01 => PM_Inst_RAM_Word0_INIT_01,
INIT_02 => PM_Inst_RAM_Word0_INIT_02,
INIT_03 => PM_Inst_RAM_Word0_INIT_03,
INIT_04 => PM_Inst_RAM_Word0_INIT_04,
INIT_05 => PM_Inst_RAM_Word0_INIT_05,
INIT_06 => PM_Inst_RAM_Word0_INIT_06,
INIT_07 => PM_Inst_RAM_Word0_INIT_07,
INIT_08 => PM_Inst_RAM_Word0_INIT_08,
INIT_09 => PM_Inst_RAM_Word0_INIT_09,
INIT_0A => PM_Inst_RAM_Word0_INIT_0A,
INIT_0B => PM_Inst_RAM_Word0_INIT_0B,
INIT_0C => PM_Inst_RAM_Word0_INIT_0C,
INIT_0D => PM_Inst_RAM_Word0_INIT_0D,
INIT_0E => PM_Inst_RAM_Word0_INIT_0E,
INIT_0F => PM_Inst_RAM_Word0_INIT_0F,
INIT_10 => PM_Inst_RAM_Word0_INIT_10,
INIT_11 => PM_Inst_RAM_Word0_INIT_11,
INIT_12 => PM_Inst_RAM_Word0_INIT_12,
INIT_13 => PM_Inst_RAM_Word0_INIT_13,
INIT_14 => PM_Inst_RAM_Word0_INIT_14,
INIT_15 => PM_Inst_RAM_Word0_INIT_15,
INIT_16 => PM_Inst_RAM_Word0_INIT_16,
INIT_17 => PM_Inst_RAM_Word0_INIT_17,
INIT_18 => PM_Inst_RAM_Word0_INIT_18,
INIT_19 => PM_Inst_RAM_Word0_INIT_19,
INIT_1A => PM_Inst_RAM_Word0_INIT_1A,
INIT_1B => PM_Inst_RAM_Word0_INIT_1B,
INIT_1C => PM_Inst_RAM_Word0_INIT_1C,
INIT_1D => PM_Inst_RAM_Word0_INIT_1D,
INIT_1E => PM_Inst_RAM_Word0_INIT_1E,
INIT_1F => PM_Inst_RAM_Word0_INIT_1F,
INIT_20 => PM_Inst_RAM_Word0_INIT_20,
INIT_21 => PM_Inst_RAM_Word0_INIT_21,
INIT_22 => PM_Inst_RAM_Word0_INIT_22,
INIT_23 => PM_Inst_RAM_Word0_INIT_23,
INIT_24 => PM_Inst_RAM_Word0_INIT_24,
INIT_25 => PM_Inst_RAM_Word0_INIT_25,
INIT_26 => PM_Inst_RAM_Word0_INIT_26,
INIT_27 => PM_Inst_RAM_Word0_INIT_27,
INIT_28 => PM_Inst_RAM_Word0_INIT_28,
INIT_29 => PM_Inst_RAM_Word0_INIT_29,
INIT_2A => PM_Inst_RAM_Word0_INIT_2A,
INIT_2B => PM_Inst_RAM_Word0_INIT_2B,
INIT_2C => PM_Inst_RAM_Word0_INIT_2C,
INIT_2D => PM_Inst_RAM_Word0_INIT_2D,
INIT_2E => PM_Inst_RAM_Word0_INIT_2E,
INIT_2F => PM_Inst_RAM_Word0_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word0_INIT_30,
INIT_31 => PM_Inst_RAM_Word0_INIT_31,
INIT_32 => PM_Inst_RAM_Word0_INIT_32,
INIT_33 => PM_Inst_RAM_Word0_INIT_33,
INIT_34 => PM_Inst_RAM_Word0_INIT_34,
INIT_35 => PM_Inst_RAM_Word0_INIT_35,
INIT_36 => PM_Inst_RAM_Word0_INIT_36,
INIT_37 => PM_Inst_RAM_Word0_INIT_37,
INIT_38 => PM_Inst_RAM_Word0_INIT_38,
INIT_39 => PM_Inst_RAM_Word0_INIT_39,
INIT_3A => PM_Inst_RAM_Word0_INIT_3A,
INIT_3B => PM_Inst_RAM_Word0_INIT_3B,
INIT_3C => PM_Inst_RAM_Word0_INIT_3C,
INIT_3D => PM_Inst_RAM_Word0_INIT_3D,
INIT_3E => PM_Inst_RAM_Word0_INIT_3E,
INIT_3F => PM_Inst_RAM_Word0_INIT_3F
)
port map(
DO => RAMBlDOut(0)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(0)
);
RAM_Word1:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word1_INIT_00,
INIT_01 => PM_Inst_RAM_Word1_INIT_01,
INIT_02 => PM_Inst_RAM_Word1_INIT_02,
INIT_03 => PM_Inst_RAM_Word1_INIT_03,
INIT_04 => PM_Inst_RAM_Word1_INIT_04,
INIT_05 => PM_Inst_RAM_Word1_INIT_05,
INIT_06 => PM_Inst_RAM_Word1_INIT_06,
INIT_07 => PM_Inst_RAM_Word1_INIT_07,
INIT_08 => PM_Inst_RAM_Word1_INIT_08,
INIT_09 => PM_Inst_RAM_Word1_INIT_09,
INIT_0A => PM_Inst_RAM_Word1_INIT_0A,
INIT_0B => PM_Inst_RAM_Word1_INIT_0B,
INIT_0C => PM_Inst_RAM_Word1_INIT_0C,
INIT_0D => PM_Inst_RAM_Word1_INIT_0D,
INIT_0E => PM_Inst_RAM_Word1_INIT_0E,
INIT_0F => PM_Inst_RAM_Word1_INIT_0F,
INIT_10 => PM_Inst_RAM_Word1_INIT_10,
INIT_11 => PM_Inst_RAM_Word1_INIT_11,
INIT_12 => PM_Inst_RAM_Word1_INIT_12,
INIT_13 => PM_Inst_RAM_Word1_INIT_13,
INIT_14 => PM_Inst_RAM_Word1_INIT_14,
INIT_15 => PM_Inst_RAM_Word1_INIT_15,
INIT_16 => PM_Inst_RAM_Word1_INIT_16,
INIT_17 => PM_Inst_RAM_Word1_INIT_17,
INIT_18 => PM_Inst_RAM_Word1_INIT_18,
INIT_19 => PM_Inst_RAM_Word1_INIT_19,
INIT_1A => PM_Inst_RAM_Word1_INIT_1A,
INIT_1B => PM_Inst_RAM_Word1_INIT_1B,
INIT_1C => PM_Inst_RAM_Word1_INIT_1C,
INIT_1D => PM_Inst_RAM_Word1_INIT_1D,
INIT_1E => PM_Inst_RAM_Word1_INIT_1E,
INIT_1F => PM_Inst_RAM_Word1_INIT_1F,
INIT_20 => PM_Inst_RAM_Word1_INIT_20,
INIT_21 => PM_Inst_RAM_Word1_INIT_21,
INIT_22 => PM_Inst_RAM_Word1_INIT_22,
INIT_23 => PM_Inst_RAM_Word1_INIT_23,
INIT_24 => PM_Inst_RAM_Word1_INIT_24,
INIT_25 => PM_Inst_RAM_Word1_INIT_25,
INIT_26 => PM_Inst_RAM_Word1_INIT_26,
INIT_27 => PM_Inst_RAM_Word1_INIT_27,
INIT_28 => PM_Inst_RAM_Word1_INIT_28,
INIT_29 => PM_Inst_RAM_Word1_INIT_29,
INIT_2A => PM_Inst_RAM_Word1_INIT_2A,
INIT_2B => PM_Inst_RAM_Word1_INIT_2B,
INIT_2C => PM_Inst_RAM_Word1_INIT_2C,
INIT_2D => PM_Inst_RAM_Word1_INIT_2D,
INIT_2E => PM_Inst_RAM_Word1_INIT_2E,
INIT_2F => PM_Inst_RAM_Word1_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word1_INIT_30,
INIT_31 => PM_Inst_RAM_Word1_INIT_31,
INIT_32 => PM_Inst_RAM_Word1_INIT_32,
INIT_33 => PM_Inst_RAM_Word1_INIT_33,
INIT_34 => PM_Inst_RAM_Word1_INIT_34,
INIT_35 => PM_Inst_RAM_Word1_INIT_35,
INIT_36 => PM_Inst_RAM_Word1_INIT_36,
INIT_37 => PM_Inst_RAM_Word1_INIT_37,
INIT_38 => PM_Inst_RAM_Word1_INIT_38,
INIT_39 => PM_Inst_RAM_Word1_INIT_39,
INIT_3A => PM_Inst_RAM_Word1_INIT_3A,
INIT_3B => PM_Inst_RAM_Word1_INIT_3B,
INIT_3C => PM_Inst_RAM_Word1_INIT_3C,
INIT_3D => PM_Inst_RAM_Word1_INIT_3D,
INIT_3E => PM_Inst_RAM_Word1_INIT_3E,
INIT_3F => PM_Inst_RAM_Word1_INIT_3F
)
port map(
DO => RAMBlDOut(1)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(1)
);
RAM_Word2:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word2_INIT_00,
INIT_01 => PM_Inst_RAM_Word2_INIT_01,
INIT_02 => PM_Inst_RAM_Word2_INIT_02,
INIT_03 => PM_Inst_RAM_Word2_INIT_03,
INIT_04 => PM_Inst_RAM_Word2_INIT_04,
INIT_05 => PM_Inst_RAM_Word2_INIT_05,
INIT_06 => PM_Inst_RAM_Word2_INIT_06,
INIT_07 => PM_Inst_RAM_Word2_INIT_07,
INIT_08 => PM_Inst_RAM_Word2_INIT_08,
INIT_09 => PM_Inst_RAM_Word2_INIT_09,
INIT_0A => PM_Inst_RAM_Word2_INIT_0A,
INIT_0B => PM_Inst_RAM_Word2_INIT_0B,
INIT_0C => PM_Inst_RAM_Word2_INIT_0C,
INIT_0D => PM_Inst_RAM_Word2_INIT_0D,
INIT_0E => PM_Inst_RAM_Word2_INIT_0E,
INIT_0F => PM_Inst_RAM_Word2_INIT_0F,
INIT_10 => PM_Inst_RAM_Word2_INIT_10,
INIT_11 => PM_Inst_RAM_Word2_INIT_11,
INIT_12 => PM_Inst_RAM_Word2_INIT_12,
INIT_13 => PM_Inst_RAM_Word2_INIT_13,
INIT_14 => PM_Inst_RAM_Word2_INIT_14,
INIT_15 => PM_Inst_RAM_Word2_INIT_15,
INIT_16 => PM_Inst_RAM_Word2_INIT_16,
INIT_17 => PM_Inst_RAM_Word2_INIT_17,
INIT_18 => PM_Inst_RAM_Word2_INIT_18,
INIT_19 => PM_Inst_RAM_Word2_INIT_19,
INIT_1A => PM_Inst_RAM_Word2_INIT_1A,
INIT_1B => PM_Inst_RAM_Word2_INIT_1B,
INIT_1C => PM_Inst_RAM_Word2_INIT_1C,
INIT_1D => PM_Inst_RAM_Word2_INIT_1D,
INIT_1E => PM_Inst_RAM_Word2_INIT_1E,
INIT_1F => PM_Inst_RAM_Word2_INIT_1F,
INIT_20 => PM_Inst_RAM_Word2_INIT_20,
INIT_21 => PM_Inst_RAM_Word2_INIT_21,
INIT_22 => PM_Inst_RAM_Word2_INIT_22,
INIT_23 => PM_Inst_RAM_Word2_INIT_23,
INIT_24 => PM_Inst_RAM_Word2_INIT_24,
INIT_25 => PM_Inst_RAM_Word2_INIT_25,
INIT_26 => PM_Inst_RAM_Word2_INIT_26,
INIT_27 => PM_Inst_RAM_Word2_INIT_27,
INIT_28 => PM_Inst_RAM_Word2_INIT_28,
INIT_29 => PM_Inst_RAM_Word2_INIT_29,
INIT_2A => PM_Inst_RAM_Word2_INIT_2A,
INIT_2B => PM_Inst_RAM_Word2_INIT_2B,
INIT_2C => PM_Inst_RAM_Word2_INIT_2C,
INIT_2D => PM_Inst_RAM_Word2_INIT_2D,
INIT_2E => PM_Inst_RAM_Word2_INIT_2E,
INIT_2F => PM_Inst_RAM_Word2_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word2_INIT_30,
INIT_31 => PM_Inst_RAM_Word2_INIT_31,
INIT_32 => PM_Inst_RAM_Word2_INIT_32,
INIT_33 => PM_Inst_RAM_Word2_INIT_33,
INIT_34 => PM_Inst_RAM_Word2_INIT_34,
INIT_35 => PM_Inst_RAM_Word2_INIT_35,
INIT_36 => PM_Inst_RAM_Word2_INIT_36,
INIT_37 => PM_Inst_RAM_Word2_INIT_37,
INIT_38 => PM_Inst_RAM_Word2_INIT_38,
INIT_39 => PM_Inst_RAM_Word2_INIT_39,
INIT_3A => PM_Inst_RAM_Word2_INIT_3A,
INIT_3B => PM_Inst_RAM_Word2_INIT_3B,
INIT_3C => PM_Inst_RAM_Word2_INIT_3C,
INIT_3D => PM_Inst_RAM_Word2_INIT_3D,
INIT_3E => PM_Inst_RAM_Word2_INIT_3E,
INIT_3F => PM_Inst_RAM_Word2_INIT_3F
)
port map(
DO => RAMBlDOut(2)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(2)
);
RAM_Word3:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word3_INIT_00,
INIT_01 => PM_Inst_RAM_Word3_INIT_01,
INIT_02 => PM_Inst_RAM_Word3_INIT_02,
INIT_03 => PM_Inst_RAM_Word3_INIT_03,
INIT_04 => PM_Inst_RAM_Word3_INIT_04,
INIT_05 => PM_Inst_RAM_Word3_INIT_05,
INIT_06 => PM_Inst_RAM_Word3_INIT_06,
INIT_07 => PM_Inst_RAM_Word3_INIT_07,
INIT_08 => PM_Inst_RAM_Word3_INIT_08,
INIT_09 => PM_Inst_RAM_Word3_INIT_09,
INIT_0A => PM_Inst_RAM_Word3_INIT_0A,
INIT_0B => PM_Inst_RAM_Word3_INIT_0B,
INIT_0C => PM_Inst_RAM_Word3_INIT_0C,
INIT_0D => PM_Inst_RAM_Word3_INIT_0D,
INIT_0E => PM_Inst_RAM_Word3_INIT_0E,
INIT_0F => PM_Inst_RAM_Word3_INIT_0F,
INIT_10 => PM_Inst_RAM_Word3_INIT_10,
INIT_11 => PM_Inst_RAM_Word3_INIT_11,
INIT_12 => PM_Inst_RAM_Word3_INIT_12,
INIT_13 => PM_Inst_RAM_Word3_INIT_13,
INIT_14 => PM_Inst_RAM_Word3_INIT_14,
INIT_15 => PM_Inst_RAM_Word3_INIT_15,
INIT_16 => PM_Inst_RAM_Word3_INIT_16,
INIT_17 => PM_Inst_RAM_Word3_INIT_17,
INIT_18 => PM_Inst_RAM_Word3_INIT_18,
INIT_19 => PM_Inst_RAM_Word3_INIT_19,
INIT_1A => PM_Inst_RAM_Word3_INIT_1A,
INIT_1B => PM_Inst_RAM_Word3_INIT_1B,
INIT_1C => PM_Inst_RAM_Word3_INIT_1C,
INIT_1D => PM_Inst_RAM_Word3_INIT_1D,
INIT_1E => PM_Inst_RAM_Word3_INIT_1E,
INIT_1F => PM_Inst_RAM_Word3_INIT_1F,
INIT_20 => PM_Inst_RAM_Word3_INIT_20,
INIT_21 => PM_Inst_RAM_Word3_INIT_21,
INIT_22 => PM_Inst_RAM_Word3_INIT_22,
INIT_23 => PM_Inst_RAM_Word3_INIT_23,
INIT_24 => PM_Inst_RAM_Word3_INIT_24,
INIT_25 => PM_Inst_RAM_Word3_INIT_25,
INIT_26 => PM_Inst_RAM_Word3_INIT_26,
INIT_27 => PM_Inst_RAM_Word3_INIT_27,
INIT_28 => PM_Inst_RAM_Word3_INIT_28,
INIT_29 => PM_Inst_RAM_Word3_INIT_29,
INIT_2A => PM_Inst_RAM_Word3_INIT_2A,
INIT_2B => PM_Inst_RAM_Word3_INIT_2B,
INIT_2C => PM_Inst_RAM_Word3_INIT_2C,
INIT_2D => PM_Inst_RAM_Word3_INIT_2D,
INIT_2E => PM_Inst_RAM_Word3_INIT_2E,
INIT_2F => PM_Inst_RAM_Word3_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word3_INIT_30,
INIT_31 => PM_Inst_RAM_Word3_INIT_31,
INIT_32 => PM_Inst_RAM_Word3_INIT_32,
INIT_33 => PM_Inst_RAM_Word3_INIT_33,
INIT_34 => PM_Inst_RAM_Word3_INIT_34,
INIT_35 => PM_Inst_RAM_Word3_INIT_35,
INIT_36 => PM_Inst_RAM_Word3_INIT_36,
INIT_37 => PM_Inst_RAM_Word3_INIT_37,
INIT_38 => PM_Inst_RAM_Word3_INIT_38,
INIT_39 => PM_Inst_RAM_Word3_INIT_39,
INIT_3A => PM_Inst_RAM_Word3_INIT_3A,
INIT_3B => PM_Inst_RAM_Word3_INIT_3B,
INIT_3C => PM_Inst_RAM_Word3_INIT_3C,
INIT_3D => PM_Inst_RAM_Word3_INIT_3D,
INIT_3E => PM_Inst_RAM_Word3_INIT_3E,
INIT_3F => PM_Inst_RAM_Word3_INIT_3F
)
port map(
DO => RAMBlDOut(3)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(3)
);
RAM_Word4:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word4_INIT_00,
INIT_01 => PM_Inst_RAM_Word4_INIT_01,
INIT_02 => PM_Inst_RAM_Word4_INIT_02,
INIT_03 => PM_Inst_RAM_Word4_INIT_03,
INIT_04 => PM_Inst_RAM_Word4_INIT_04,
INIT_05 => PM_Inst_RAM_Word4_INIT_05,
INIT_06 => PM_Inst_RAM_Word4_INIT_06,
INIT_07 => PM_Inst_RAM_Word4_INIT_07,
INIT_08 => PM_Inst_RAM_Word4_INIT_08,
INIT_09 => PM_Inst_RAM_Word4_INIT_09,
INIT_0A => PM_Inst_RAM_Word4_INIT_0A,
INIT_0B => PM_Inst_RAM_Word4_INIT_0B,
INIT_0C => PM_Inst_RAM_Word4_INIT_0C,
INIT_0D => PM_Inst_RAM_Word4_INIT_0D,
INIT_0E => PM_Inst_RAM_Word4_INIT_0E,
INIT_0F => PM_Inst_RAM_Word4_INIT_0F,
INIT_10 => PM_Inst_RAM_Word4_INIT_10,
INIT_11 => PM_Inst_RAM_Word4_INIT_11,
INIT_12 => PM_Inst_RAM_Word4_INIT_12,
INIT_13 => PM_Inst_RAM_Word4_INIT_13,
INIT_14 => PM_Inst_RAM_Word4_INIT_14,
INIT_15 => PM_Inst_RAM_Word4_INIT_15,
INIT_16 => PM_Inst_RAM_Word4_INIT_16,
INIT_17 => PM_Inst_RAM_Word4_INIT_17,
INIT_18 => PM_Inst_RAM_Word4_INIT_18,
INIT_19 => PM_Inst_RAM_Word4_INIT_19,
INIT_1A => PM_Inst_RAM_Word4_INIT_1A,
INIT_1B => PM_Inst_RAM_Word4_INIT_1B,
INIT_1C => PM_Inst_RAM_Word4_INIT_1C,
INIT_1D => PM_Inst_RAM_Word4_INIT_1D,
INIT_1E => PM_Inst_RAM_Word4_INIT_1E,
INIT_1F => PM_Inst_RAM_Word4_INIT_1F,
INIT_20 => PM_Inst_RAM_Word4_INIT_20,
INIT_21 => PM_Inst_RAM_Word4_INIT_21,
INIT_22 => PM_Inst_RAM_Word4_INIT_22,
INIT_23 => PM_Inst_RAM_Word4_INIT_23,
INIT_24 => PM_Inst_RAM_Word4_INIT_24,
INIT_25 => PM_Inst_RAM_Word4_INIT_25,
INIT_26 => PM_Inst_RAM_Word4_INIT_26,
INIT_27 => PM_Inst_RAM_Word4_INIT_27,
INIT_28 => PM_Inst_RAM_Word4_INIT_28,
INIT_29 => PM_Inst_RAM_Word4_INIT_29,
INIT_2A => PM_Inst_RAM_Word4_INIT_2A,
INIT_2B => PM_Inst_RAM_Word4_INIT_2B,
INIT_2C => PM_Inst_RAM_Word4_INIT_2C,
INIT_2D => PM_Inst_RAM_Word4_INIT_2D,
INIT_2E => PM_Inst_RAM_Word4_INIT_2E,
INIT_2F => PM_Inst_RAM_Word4_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word4_INIT_30,
INIT_31 => PM_Inst_RAM_Word4_INIT_31,
INIT_32 => PM_Inst_RAM_Word4_INIT_32,
INIT_33 => PM_Inst_RAM_Word4_INIT_33,
INIT_34 => PM_Inst_RAM_Word4_INIT_34,
INIT_35 => PM_Inst_RAM_Word4_INIT_35,
INIT_36 => PM_Inst_RAM_Word4_INIT_36,
INIT_37 => PM_Inst_RAM_Word4_INIT_37,
INIT_38 => PM_Inst_RAM_Word4_INIT_38,
INIT_39 => PM_Inst_RAM_Word4_INIT_39,
INIT_3A => PM_Inst_RAM_Word4_INIT_3A,
INIT_3B => PM_Inst_RAM_Word4_INIT_3B,
INIT_3C => PM_Inst_RAM_Word4_INIT_3C,
INIT_3D => PM_Inst_RAM_Word4_INIT_3D,
INIT_3E => PM_Inst_RAM_Word4_INIT_3E,
INIT_3F => PM_Inst_RAM_Word4_INIT_3F
)
port map(
DO => RAMBlDOut(4)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(4)
);
RAM_Word5:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word5_INIT_00,
INIT_01 => PM_Inst_RAM_Word5_INIT_01,
INIT_02 => PM_Inst_RAM_Word5_INIT_02,
INIT_03 => PM_Inst_RAM_Word5_INIT_03,
INIT_04 => PM_Inst_RAM_Word5_INIT_04,
INIT_05 => PM_Inst_RAM_Word5_INIT_05,
INIT_06 => PM_Inst_RAM_Word5_INIT_06,
INIT_07 => PM_Inst_RAM_Word5_INIT_07,
INIT_08 => PM_Inst_RAM_Word5_INIT_08,
INIT_09 => PM_Inst_RAM_Word5_INIT_09,
INIT_0A => PM_Inst_RAM_Word5_INIT_0A,
INIT_0B => PM_Inst_RAM_Word5_INIT_0B,
INIT_0C => PM_Inst_RAM_Word5_INIT_0C,
INIT_0D => PM_Inst_RAM_Word5_INIT_0D,
INIT_0E => PM_Inst_RAM_Word5_INIT_0E,
INIT_0F => PM_Inst_RAM_Word5_INIT_0F,
INIT_10 => PM_Inst_RAM_Word5_INIT_10,
INIT_11 => PM_Inst_RAM_Word5_INIT_11,
INIT_12 => PM_Inst_RAM_Word5_INIT_12,
INIT_13 => PM_Inst_RAM_Word5_INIT_13,
INIT_14 => PM_Inst_RAM_Word5_INIT_14,
INIT_15 => PM_Inst_RAM_Word5_INIT_15,
INIT_16 => PM_Inst_RAM_Word5_INIT_16,
INIT_17 => PM_Inst_RAM_Word5_INIT_17,
INIT_18 => PM_Inst_RAM_Word5_INIT_18,
INIT_19 => PM_Inst_RAM_Word5_INIT_19,
INIT_1A => PM_Inst_RAM_Word5_INIT_1A,
INIT_1B => PM_Inst_RAM_Word5_INIT_1B,
INIT_1C => PM_Inst_RAM_Word5_INIT_1C,
INIT_1D => PM_Inst_RAM_Word5_INIT_1D,
INIT_1E => PM_Inst_RAM_Word5_INIT_1E,
INIT_1F => PM_Inst_RAM_Word5_INIT_1F,
INIT_20 => PM_Inst_RAM_Word5_INIT_20,
INIT_21 => PM_Inst_RAM_Word5_INIT_21,
INIT_22 => PM_Inst_RAM_Word5_INIT_22,
INIT_23 => PM_Inst_RAM_Word5_INIT_23,
INIT_24 => PM_Inst_RAM_Word5_INIT_24,
INIT_25 => PM_Inst_RAM_Word5_INIT_25,
INIT_26 => PM_Inst_RAM_Word5_INIT_26,
INIT_27 => PM_Inst_RAM_Word5_INIT_27,
INIT_28 => PM_Inst_RAM_Word5_INIT_28,
INIT_29 => PM_Inst_RAM_Word5_INIT_29,
INIT_2A => PM_Inst_RAM_Word5_INIT_2A,
INIT_2B => PM_Inst_RAM_Word5_INIT_2B,
INIT_2C => PM_Inst_RAM_Word5_INIT_2C,
INIT_2D => PM_Inst_RAM_Word5_INIT_2D,
INIT_2E => PM_Inst_RAM_Word5_INIT_2E,
INIT_2F => PM_Inst_RAM_Word5_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word5_INIT_30,
INIT_31 => PM_Inst_RAM_Word5_INIT_31,
INIT_32 => PM_Inst_RAM_Word5_INIT_32,
INIT_33 => PM_Inst_RAM_Word5_INIT_33,
INIT_34 => PM_Inst_RAM_Word5_INIT_34,
INIT_35 => PM_Inst_RAM_Word5_INIT_35,
INIT_36 => PM_Inst_RAM_Word5_INIT_36,
INIT_37 => PM_Inst_RAM_Word5_INIT_37,
INIT_38 => PM_Inst_RAM_Word5_INIT_38,
INIT_39 => PM_Inst_RAM_Word5_INIT_39,
INIT_3A => PM_Inst_RAM_Word5_INIT_3A,
INIT_3B => PM_Inst_RAM_Word5_INIT_3B,
INIT_3C => PM_Inst_RAM_Word5_INIT_3C,
INIT_3D => PM_Inst_RAM_Word5_INIT_3D,
INIT_3E => PM_Inst_RAM_Word5_INIT_3E,
INIT_3F => PM_Inst_RAM_Word5_INIT_3F
)
port map(
DO => RAMBlDOut(5)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(5)
);
RAM_Word6:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word6_INIT_00,
INIT_01 => PM_Inst_RAM_Word6_INIT_01,
INIT_02 => PM_Inst_RAM_Word6_INIT_02,
INIT_03 => PM_Inst_RAM_Word6_INIT_03,
INIT_04 => PM_Inst_RAM_Word6_INIT_04,
INIT_05 => PM_Inst_RAM_Word6_INIT_05,
INIT_06 => PM_Inst_RAM_Word6_INIT_06,
INIT_07 => PM_Inst_RAM_Word6_INIT_07,
INIT_08 => PM_Inst_RAM_Word6_INIT_08,
INIT_09 => PM_Inst_RAM_Word6_INIT_09,
INIT_0A => PM_Inst_RAM_Word6_INIT_0A,
INIT_0B => PM_Inst_RAM_Word6_INIT_0B,
INIT_0C => PM_Inst_RAM_Word6_INIT_0C,
INIT_0D => PM_Inst_RAM_Word6_INIT_0D,
INIT_0E => PM_Inst_RAM_Word6_INIT_0E,
INIT_0F => PM_Inst_RAM_Word6_INIT_0F,
INIT_10 => PM_Inst_RAM_Word6_INIT_10,
INIT_11 => PM_Inst_RAM_Word6_INIT_11,
INIT_12 => PM_Inst_RAM_Word6_INIT_12,
INIT_13 => PM_Inst_RAM_Word6_INIT_13,
INIT_14 => PM_Inst_RAM_Word6_INIT_14,
INIT_15 => PM_Inst_RAM_Word6_INIT_15,
INIT_16 => PM_Inst_RAM_Word6_INIT_16,
INIT_17 => PM_Inst_RAM_Word6_INIT_17,
INIT_18 => PM_Inst_RAM_Word6_INIT_18,
INIT_19 => PM_Inst_RAM_Word6_INIT_19,
INIT_1A => PM_Inst_RAM_Word6_INIT_1A,
INIT_1B => PM_Inst_RAM_Word6_INIT_1B,
INIT_1C => PM_Inst_RAM_Word6_INIT_1C,
INIT_1D => PM_Inst_RAM_Word6_INIT_1D,
INIT_1E => PM_Inst_RAM_Word6_INIT_1E,
INIT_1F => PM_Inst_RAM_Word6_INIT_1F,
INIT_20 => PM_Inst_RAM_Word6_INIT_20,
INIT_21 => PM_Inst_RAM_Word6_INIT_21,
INIT_22 => PM_Inst_RAM_Word6_INIT_22,
INIT_23 => PM_Inst_RAM_Word6_INIT_23,
INIT_24 => PM_Inst_RAM_Word6_INIT_24,
INIT_25 => PM_Inst_RAM_Word6_INIT_25,
INIT_26 => PM_Inst_RAM_Word6_INIT_26,
INIT_27 => PM_Inst_RAM_Word6_INIT_27,
INIT_28 => PM_Inst_RAM_Word6_INIT_28,
INIT_29 => PM_Inst_RAM_Word6_INIT_29,
INIT_2A => PM_Inst_RAM_Word6_INIT_2A,
INIT_2B => PM_Inst_RAM_Word6_INIT_2B,
INIT_2C => PM_Inst_RAM_Word6_INIT_2C,
INIT_2D => PM_Inst_RAM_Word6_INIT_2D,
INIT_2E => PM_Inst_RAM_Word6_INIT_2E,
INIT_2F => PM_Inst_RAM_Word6_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word6_INIT_30,
INIT_31 => PM_Inst_RAM_Word6_INIT_31,
INIT_32 => PM_Inst_RAM_Word6_INIT_32,
INIT_33 => PM_Inst_RAM_Word6_INIT_33,
INIT_34 => PM_Inst_RAM_Word6_INIT_34,
INIT_35 => PM_Inst_RAM_Word6_INIT_35,
INIT_36 => PM_Inst_RAM_Word6_INIT_36,
INIT_37 => PM_Inst_RAM_Word6_INIT_37,
INIT_38 => PM_Inst_RAM_Word6_INIT_38,
INIT_39 => PM_Inst_RAM_Word6_INIT_39,
INIT_3A => PM_Inst_RAM_Word6_INIT_3A,
INIT_3B => PM_Inst_RAM_Word6_INIT_3B,
INIT_3C => PM_Inst_RAM_Word6_INIT_3C,
INIT_3D => PM_Inst_RAM_Word6_INIT_3D,
INIT_3E => PM_Inst_RAM_Word6_INIT_3E,
INIT_3F => PM_Inst_RAM_Word6_INIT_3F
)
port map(
DO => RAMBlDOut(6)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(6)
);
RAM_Word7:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(7)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(7)
);
--end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;

558
src/AVR8/Memory/prog_mem_init.vhd Normal file
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@ -0,0 +1,558 @@
-- VHDL initialization records.
--
-- Release 11.1i - Data2MEM L.33, build 1.5.8 Jul 23, 2008
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--
-- Command: C:\Users\ZBAND0~1\AppData\Local\Temp\build5746311222132730322.tmp\data2mem.exe -bm bitstreams/custom_bd.bmm -bd out.mem -o h E:\Papilio\Cores\GadgetFactory_Arduino_Timer_Counter\AVR8_SoftCore_TimerCounter_SPI\sources\Memory\prog_mem_init.vhd
--
-- Created on 11/24/12 01:13 pm, from:
--
-- Map file - bitstreams\custom_bd.bmm
-- Data file(s) - out.mem
--
-- Address space 'avrmap.rom_code' [0x00000000:0x00003FFF], 16384 bytes in size.
--
-- Bus width = 16 bits, bit lane width = 16 bits, number of bus blocks = 8.
library ieee;
use ieee.std_logic_1164;
package prog_mem_init_pkg is
-- BRAM 0 in address space [0x00000000:0x000007FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word0 LOC = RAMB16_X0Y4;
constant PM_Inst_RAM_Word0_INIT_00 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C0098940C";
constant PM_Inst_RAM_Word0_INIT_01 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C";
constant PM_Inst_RAM_Word0_INIT_02 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C1644940C00C7940C1539940C";
constant PM_Inst_RAM_Word0_INIT_03 : bit_vector(0 to 255) := x"000000280022003100340037003A0000005C222A2C3B5D5B2F3F3D2B5E3E3C7C";
constant PM_Inst_RAM_Word0_INIT_04 : bit_vector(0 to 255) := x"010101010101002000210030003300360039000000270023003200350038003B";
constant PM_Inst_RAM_Word0_INIT_05 : bit_vector(0 to 255) := x"0505050505050404040404040404030303030303030302020202020202020101";
constant PM_Inst_RAM_Word0_INIT_06 : bit_vector(0 to 255) := x"2010080402018040201008040201804020100804020106060606060606060505";
constant PM_Inst_RAM_Word0_INIT_07 : bit_vector(0 to 255) := x"0000000000008040201008040201804020100804020180402010080402018040";
constant PM_Inst_RAM_Word0_INIT_08 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000005000001000000000000";
constant PM_Inst_RAM_Word0_INIT_09 : bit_vector(0 to 255) := x"E6A0E011BFCDBFDEE0DFEFCFBE1F241116DD1193000000000000000000000000";
constant PM_Inst_RAM_Word0_INIT_0A : bit_vector(0 to 255) := x"E014BE1BF7C907B131A2F3C89631920D95D8C004BF0B9503EF0FE3F2E1E2E0B0";
constant PM_Inst_RAM_Word0_INIT_0B : bit_vector(0 to 255) := x"1901940E2FEC2FFD9722C005E0D1E3C0E011F7E107B131AB921DC001E0B1E1A2";
constant PM_Inst_RAM_Word0_INIT_0C : bit_vector(0 to 255) := x"9001918DC0042FB92FA82FF72FE60000940C1907940C170E940EF7C107D132CC";
constant PM_Inst_RAM_Word0_INIT_0D : bit_vector(0 to 255) := x"9508E0808385E186F02030672FF92FE895080B991B88F7C840505041F4211980";
constant PM_Inst_RAM_Word0_INIT_0E : bit_vector(0 to 255) := x"E090C002FD22B14DB98D7F8CB18D9A70C0019870F4113066C002FD60E0302F26";
constant PM_Inst_RAM_Word0_INIT_0F : bit_vector(0 to 255) := x"93DF93CF931F930F92FF9508E081B98D2B892B8470812F8295279536E092C001";
constant PM_Inst_RAM_Word0_INIT_10 : bit_vector(0 to 255) := x"C008E081F4113F8FB18FCFFE9B77B8FF94FA24FF2FD72FC61581940E2F172F06";
constant PM_Inst_RAM_Word0_INIT_11 : bit_vector(0 to 255) := x"2FF92FE8950890FF910F911F91CF91DFE080F388077117600B7D1B6C1581940E";
constant PM_Inst_RAM_Word0_INIT_12 : bit_vector(0 to 255) := x"2F84B96F2FB92FA8950815FC940EE06181842FF92FE8950815FC940EE0608184";
constant PM_Inst_RAM_Word0_INIT_13 : bit_vector(0 to 255) := x"96324F3F5F2EB98F8181CFFE9B77B98F8180CFFE9B77E030E0202FF92FE82F95";
constant PM_Inst_RAM_Word0_INIT_14 : bit_vector(0 to 255) := x"B98FEF8FCFFE9B77B98FEF8FCFFE9B77B98FEF8FCFFE9B77F78907383020E082";
constant PM_Inst_RAM_Word0_INIT_15 : bit_vector(0 to 255) := x"2F8A9715938C9615E1819508E081F4113085718F971A938C961AB18FCFFE9B77";
constant PM_Inst_RAM_Word0_INIT_16 : bit_vector(0 to 255) := x"2F172F061581940E2FD92FC893DF93CF931F930F92FF9508E0800125940E2F9B";
constant PM_Inst_RAM_Word0_INIT_17 : bit_vector(0 to 255) := x"B18FCFFE9B77B8FFC00CE08FF0104071526D0B711B601581940EC00994FA24FF";
constant PM_Inst_RAM_Word0_INIT_18 : bit_vector(0 to 255) := x"91CF91DFE0800125940E2F9D2F8C838DE08DC007E081F4113F8EF3813F8F878A";
constant PM_Inst_RAM_Word0_INIT_19 : bit_vector(0 to 255) := x"EF4F8538812FB98FEF8FF0D12388818E2FD92FC893DF93CF950890FF910F911F";
constant PM_Inst_RAM_Word0_INIT_1A : bit_vector(0 to 255) := x"CFFE9B77832F8738F3A84092508197012F932F824F3F5F2FB94FCFFE9B77C003";
constant PM_Inst_RAM_Word0_INIT_1B : bit_vector(0 to 255) := x"2FC893DF93CF931F930F92FF92EF92DF950891CF91DF821E0125940E2F9D2F8C";
constant PM_Inst_RAM_Word0_INIT_1C : bit_vector(0 to 255) := x"E071E26C2F9D2F8C011E940E2F9D2F8C0194940E2F152F042EF32EE22ED62FD9";
constant PM_Inst_RAM_Word0_INIT_1D : bit_vector(0 to 255) := x"95B6C0042E022D8E2D9F2FA02FB1E030E128CFFE9B77B98F64802D8D00FB940E";
constant PM_Inst_RAM_Word0_INIT_1E : bit_vector(0 to 255) := x"F41120DDF75907383F28EF8F40305028CFFE9B77B98FF7D2940A9587959795A7";
constant PM_Inst_RAM_Word0_INIT_1F : bit_vector(0 to 255) := x"CFFE9B77B92FEF2FE090CFFE9B77B98FEF8FC001E887F41116D8E088C006E985";
constant PM_Inst_RAM_Word0_INIT_20 : bit_vector(0 to 255) := x"92DF92CF950890DF90EF90FF910F911F91CF91DF878AF7C15091C002FF87B18F";
constant PM_Inst_RAM_Word0_INIT_21 : bit_vector(0 to 255) := x"055115412ED32EC22F172F062EF52EE42FD92FC893DF93CF931F930F92FF92EF";
constant PM_Inst_RAM_Word0_INIT_22 : bit_vector(0 to 255) := x"2F8CF7D1952A1F111F001CFF0CEEE029F0393083858BC03DE182F41105710561";
constant PM_Inst_RAM_Word0_INIT_23 : bit_vector(0 to 255) := x"2D4CEF6E2F9D2F8CC026E084F011238801B8940E2D2E2D3F2F402F51E1682F9D";
constant PM_Inst_RAM_Word0_INIT_24 : bit_vector(0 to 255) := x"2F8CC013E185F411238800FB940EE072E5682F9D2F8CF0F12388012C940E2D5D";
constant PM_Inst_RAM_Word0_INIT_25 : bit_vector(0 to 255) := x"2388B18FCFFE9B77B98FEF8FF439238801B8940EE050E040E030E020E06D2F9D";
constant PM_Inst_RAM_Word0_INIT_26 : bit_vector(0 to 255) := x"90CF90DF90EF90FF910F911F91CF91DFE0800125940E2F9D2F8C838DE184F081";
constant PM_Inst_RAM_Word0_INIT_27 : bit_vector(0 to 255) := x"930F92FF92EF92DF92CF92BF92AF929F928FCFF1E0810125940E2F9D2F8C9508";
constant PM_Inst_RAM_Word0_INIT_28 : bit_vector(0 to 255) := x"2F80C081F409051115012E932E822ED72EC62EB52EA42FD92FC893DF93CF931F";
constant PM_Inst_RAM_Word0_INIT_29 : bit_vector(0 to 255) := x"0759174881BB81AA81998188F0712388818EC073F008409250811F930F822F91";
constant PM_Inst_RAM_Word0_INIT_2A : bit_vector(0 to 255) := x"E069F0393083858B82DB82CA82B982A8F538069916888598818FF429077B076A";
constant PM_Inst_RAM_Word0_INIT_2B : bit_vector(0 to 255) := x"238801B8940E2D2A2D3B2D4C2D5DE1612F9D2F8CF7D1956A1CDD1CCC1CBB0CAA";
constant PM_Inst_RAM_Word0_INIT_2C : bit_vector(0 to 255) := x"EF8F838EE081821F8618C03FF40923880165940E2F9D2F8CC046838DE083F019";
constant PM_Inst_RAM_Word0_INIT_2D : bit_vector(0 to 255) := x"2FB12FA0838F8798F3C8059915889601B92FCFFE9B77C004EF2F8598818FB98F";
constant PM_Inst_RAM_Word0_INIT_2E : bit_vector(0 to 255) := x"4F3F5F2FB99F83801FF30FE22DFF2DEEB18FCFFE9B77C00BEF9FE030E0209711";
constant PM_Inst_RAM_Word0_INIT_2F : bit_vector(0 to 255) := x"8589832F87381F310F208538812F938C1DBF0DAEB18FCFFE9B77F390073B172A";
constant PM_Inst_RAM_Word0_INIT_30 : bit_vector(0 to 255) := x"C001E0800125940E2F9D2F8CC0060194940E2F9D2F8CF05840325020F0192388";
constant PM_Inst_RAM_Word0_INIT_31 : bit_vector(0 to 255) := x"92FF92EF9508908F909F90AF90BF90CF90DF90EF90FF910F911F91CF91DFE081";
constant PM_Inst_RAM_Word0_INIT_32 : bit_vector(0 to 255) := x"92BF950890EF90FF910F911F0277940EE012E000E030E0202EF32EE2931F930F";
constant PM_Inst_RAM_Word0_INIT_33 : bit_vector(0 to 255) := x"834C821D821E8619861B2EB62FD92FC893DF93CF931F930F92FF92EF92DF92CF";
constant PM_Inst_RAM_Word0_INIT_34 : bit_vector(0 to 255) := x"15D4940EE060E08C0125940E2F9D2F8C15D4940EE061818C2ED72EC61581940E";
constant PM_Inst_RAM_Word0_INIT_35 : bit_vector(0 to 255) := x"E0809870B98DE58315D4940EE061E08A15D4940EE061E08D15D4940EE061E08B";
constant PM_Inst_RAM_Word0_INIT_36 : bit_vector(0 to 255) := x"097D196C1581940EC009011E940E2F9D2F8CF7D1308A5F8FCFFE9B77B99FEF9F";
constant PM_Inst_RAM_Word0_INIT_37 : bit_vector(0 to 255) := x"878A2F1801B8940EE050E040E030E020E0602F9D2F8CC065E081F01040775D61";
constant PM_Inst_RAM_Word0_INIT_38 : bit_vector(0 to 255) := x"E080C010871BC002FF8201B8940EE050E040E031EA2AE0682F9D2F8CF7513081";
constant PM_Inst_RAM_Word0_INIT_39 : bit_vector(0 to 255) := x"858B878BE082C03DE082F0113A9A879AF7C930845F8FB19FCFFE9B77B92FEF2F";
constant PM_Inst_RAM_Word0_INIT_3A : bit_vector(0 to 255) := x"196C1581940EC0092F17E4702D012CF12CE1C00F2711270024FF24EEF0293082";
constant PM_Inst_RAM_Word0_INIT_3B : bit_vector(0 to 255) := x"2F8C01B8940EE050E040E030E020E3672F9D2F8CC024E088F01040775D61097D";
constant PM_Inst_RAM_Word0_INIT_3C : bit_vector(0 to 255) := x"2F9D2F8CF5313082858BF7112388878A01B8940E2D2E2D3F2F402F51E2692F9D";
constant PM_Inst_RAM_Word0_INIT_3D : bit_vector(0 to 255) := x"E0800125940E2F9D2F8C838DE086F041238801B8940EE050E040E030E020E36A";
constant PM_Inst_RAM_Word0_INIT_3E : bit_vector(0 to 255) := x"CFFE9B77B99FEF9FE080878BE083F4113C807C80B18FCFFE9B77B98FEF8FC01C";
constant PM_Inst_RAM_Word0_INIT_3F : bit_vector(0 to 255) := x"911F91CF91DF00D8940E2D6B2F9D2F8C0125940E2F9D2F8CF7C930835F8FB12F";
-- BRAM 0 in address space [0x00000800:0x00000FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word1 LOC = RAMB16_X0Y8;
constant PM_Inst_RAM_Word1_INIT_00 : bit_vector(0 to 255) := x"E220E090E0802FB72FA62FD92FC893DF93CF950890BF90CF90DF90EF90FF910F";
constant PM_Inst_RAM_Word1_INIT_01 : bit_vector(0 to 255) := x"E090E680F019322EC024E040E057F7B90591308B960183201FF90FE82FFB2FEA";
constant PM_Inst_RAM_Word1_INIT_02 : bit_vector(0 to 255) := x"1754F7B923332D3095C896012FF92FE8F1091732C01AE048E05AF131305AC007";
constant PM_Inst_RAM_Word1_INIT_03 : bit_vector(0 to 255) := x"5F4F83201DF10FE42FFB2FEA5220F408318A56812F82F4A0372FF0B03221F0C0";
constant PM_Inst_RAM_Word1_INIT_04 : bit_vector(0 to 255) := x"927F926F950891CF91DF2F89E090C001E091F0193280918CE090F6C923229129";
constant PM_Inst_RAM_Word1_INIT_05 : bit_vector(0 to 255) := x"2EF52EE42FD92FC893DF93CF931F930F92FF92EF92DF92CF92BF92AF929F928F";
constant PM_Inst_RAM_Word1_INIT_06 : bit_vector(0 to 255) := x"C07BF40807B707A60795178489BD89AC899B898AC085F4092322812C2F172F06";
constant PM_Inst_RAM_Word1_INIT_07 : bit_vector(0 to 255) := x"8529C06A861C861B861A86198618821F821E821DF4490511050104F114E1C08A";
constant PM_Inst_RAM_Word1_INIT_08 : bit_vector(0 to 255) := x"2E952E842E732E6240504040403050219609E09085858DFB8DEA855C854B853A";
constant PM_Inst_RAM_Word1_INIT_09 : bit_vector(0 to 255) := x"090108F108E194084F5F4F4F4F3F5F2FF7D2940A9467947794879496C0042E08";
constant PM_Inst_RAM_Word1_INIT_0A : bit_vector(0 to 255) := x"1D011CF11CE19408F7D2958A94A794B794C794D6C0042ED12EC02CBF2CAE0911";
constant PM_Inst_RAM_Word1_INIT_0B : bit_vector(0 to 255) := x"838D8DB98DA8899F898EF4490551054105311521F02804D904C804B714A61D11";
constant PM_Inst_RAM_Word1_INIT_0C : bit_vector(0 to 255) := x"2D288D9B8D8A8578816F815E814DC01208D908C808B718A6C01787B883AF839E";
constant PM_Inst_RAM_Word1_INIT_0D : bit_vector(0 to 255) := x"1E9D0E8C2C912E88E085C010F431238808D108C108B108A194080F04940E2D39";
constant PM_Inst_RAM_Word1_INIT_0E : bit_vector(0 to 255) := x"910F911F91CF91DFE080C001E081871C870B86FA86E9F72104D104C104B114A1";
constant PM_Inst_RAM_Word1_INIT_0F : bit_vector(0 to 255) := x"93CFCFE6CF73F00930229508906F907F908F909F90AF90BF90CF90DF90EF90FF";
constant PM_Inst_RAM_Word1_INIT_10 : bit_vector(0 to 255) := x"8989C00AE030E020F41923880CC5940E8998858F857E856D2F462FD92FC893DF";
constant PM_Inst_RAM_Word1_INIT_11 : bit_vector(0 to 255) := x"931F930F950891CF91DF2F932F824F3E5E2CF7E1959A1F330F22E095E0302F28";
constant PM_Inst_RAM_Word1_INIT_12 : bit_vector(0 to 255) := x"E0612F912F80C03DFF878183C043F409238881842FF92FE82F192F0893DF93CF";
constant PM_Inst_RAM_Word1_INIT_13 : bit_vector(0 to 255) := x"8F8C89B589A489938982F440308281842FF12FE0F1B997002FD92FC804FF940E";
constant PM_Inst_RAM_Word1_INIT_14 : bit_vector(0 to 255) := x"27AA2F8A2F9B8DB18DA0899789868F8A8F9B899789862FF12FE08FBF8FAE8F9D";
constant PM_Inst_RAM_Word1_INIT_15 : bit_vector(0 to 255) := x"96482F9D2F8C4F7F5E6A2F7D2F6CF0619730011391F0011291E08B8C8B9D27BB";
constant PM_Inst_RAM_Word1_INIT_16 : bit_vector(0 to 255) := x"91CF91DFE080C0010C64940E8383778F81832FF12FE08B8A8B9B8D998D889509";
constant PM_Inst_RAM_Word1_INIT_17 : bit_vector(0 to 255) := x"950891CF91DFE081821CF0112388051E940E2FD92FC893DF93CF9508910F911F";
constant PM_Inst_RAM_Word1_INIT_18 : bit_vector(0 to 255) := x"D000D00093CF93DF931F930F92FF92EF92DF92CF92BF92AF929F928F927F926F";
constant PM_Inst_RAM_Word1_INIT_19 : bit_vector(0 to 255) := x"C0A1F00930819714918C96142FB92FA82ED72EC62EB52EA42EF92EE8B7DEB7CD";
constant PM_Inst_RAM_Word1_INIT_1A : bit_vector(0 to 255) := x"8483847284612DFF2DEEC097E081F41105B105A19700C0B0C09DFF81918C9613";
constant PM_Inst_RAM_Word1_INIT_1B : bit_vector(0 to 255) := x"918D965A2DBF2DAEC085F4092388044E940E2D4A2D5B2D6C2D7D2D9F2D8E8494";
constant PM_Inst_RAM_Word1_INIT_1C : bit_vector(0 to 255) := x"23880F82940E9759917C916D915D914D9656F49104D104C104B114A1975B919C";
constant PM_Inst_RAM_Word1_INIT_1D : bit_vector(0 to 255) := x"917C916D915D914D96152DBF2DAEC0428E118E108A178A162DFF2DEEC06FF409";
constant PM_Inst_RAM_Word1_INIT_1E : bit_vector(0 to 255) := x"975B91FC91ED965A2DBF2DAEC057F40923880F04940E4F3F5F2F2F3D2F2C9718";
constant PM_Inst_RAM_Word1_INIT_1F : bit_vector(0 to 255) := x"E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987817C816B815A8149";
constant PM_Inst_RAM_Word1_INIT_20 : bit_vector(0 to 255) := x"8167815681452DFF2DEEF1B123880F82940E2F9F2F8EF4B0077B076A07591748";
constant PM_Inst_RAM_Word1_INIT_21 : bit_vector(0 to 255) := x"92BD92AD96522DBF2DAEF13123880E5B940EE03FEF2FEF1FEF0F8D938D828570";
constant PM_Inst_RAM_Word1_INIT_22 : bit_vector(0 to 255) := x"2D7DF0912388051E940E2D9F2D8E938C961368809713918C9613975592DC92CD";
constant PM_Inst_RAM_Word1_INIT_23 : bit_vector(0 to 255) := x"044E940E2D9F2D8E2D462D572D682D79F420049D048C047B146A2D4A2D5B2D6C";
constant PM_Inst_RAM_Word1_INIT_24 : bit_vector(0 to 255) := x"90AF90BF90CF90DF90EF90FF910F911F91DF91CF900F900F900F900FE080C001";
constant PM_Inst_RAM_Word1_INIT_25 : bit_vector(0 to 255) := x"F00807B707A60795178489B589A4899389822DFF2DEE9508906F907F908F909F";
constant PM_Inst_RAM_Word1_INIT_26 : bit_vector(0 to 255) := x"92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922FCFDFCF44";
constant PM_Inst_RAM_Word1_INIT_27 : bit_vector(0 to 255) := x"C0EDC0D7FF80818BC0DAF4092388818C2E552E442FD92FC893DF93CF931F930F";
constant PM_Inst_RAM_Word1_INIT_28 : bit_vector(0 to 255) := x"C0BF2C752C641E3D0E2C2C312E27E0752E932E822F372F26085F184E2C5B2C4A";
constant PM_Inst_RAM_Word1_INIT_29 : bit_vector(0 to 255) := x"E0992F152F042EF32EE2818C22B322A22EB6E0612EA6EF6F855C854B853A8529";
constant PM_Inst_RAM_Word1_INIT_2A : bit_vector(0 to 255) := x"1D5F0D4E8D758D648D538D42F44930828DFB8DEAF7D1959A94E794F795079516";
constant PM_Inst_RAM_Word1_INIT_2B : bit_vector(0 to 255) := x"F4490551054105311521F4D920DDF4E904B114A120DE94DA80D4C0411F711F60";
constant PM_Inst_RAM_Word1_INIT_2C : bit_vector(0 to 255) := x"2D222F9F2F8E8578816F815E814DC00D87B883AF839E838D8DB98DA8899F898E";
constant PM_Inst_RAM_Word1_INIT_2D : bit_vector(0 to 255) := x"40704060405050428578816F815E814D8DFB8DEAC080F40923880F04940E2D33";
constant PM_Inst_RAM_Word1_INIT_2E : bit_vector(0 to 255) := x"1F7B1F6A1F590F4889B189A085978586F7D2940A1F771F661F550F44C0048405";
constant PM_Inst_RAM_Word1_INIT_2F : bit_vector(0 to 255) := x"818B2ED92EC8F410059715862CD72CC6099B198AE092E0801D711D611D510D4D";
constant PM_Inst_RAM_Word1_INIT_30 : bit_vector(0 to 255) := x"00FC91B000FB91A000FA919000F99180C080F00906D8E08216C8E080C006FD86";
constant PM_Inst_RAM_Word1_INIT_31 : bit_vector(0 to 255) := x"2CF92CE82D1D2D0C2D3B2D2A0315919003149180C072F409077B076A07591748";
constant PM_Inst_RAM_Word1_INIT_32 : bit_vector(0 to 255) := x"2DA81D5D0D4C2F532F424F3E5E2C2D3B2D2AC0161C9D0C8CF19123880277940E";
constant PM_Inst_RAM_Word1_INIT_33 : bit_vector(0 to 255) := x"E0402D3D2D2C1E9F0E8E0BF31BE2F7D907F517E4938D9181C0022FF32FE22DB9";
constant PM_Inst_RAM_Word1_INIT_34 : bit_vector(0 to 255) := x"1461087D186C87BC87AB879A87891FB51FA41F930F8285BC85AB859A8589E050";
constant PM_Inst_RAM_Word1_INIT_35 : bit_vector(0 to 255) := x"90EF90FF910F911F91CF91DF2F952F84EF5FEF4FC0022D552D44CF3DF0090471";
constant PM_Inst_RAM_Word1_INIT_36 : bit_vector(0 to 255) := x"88CC88BB88AA9508902F903F904F905F906F907F908F909F90AF90BF90CF90DF";
constant PM_Inst_RAM_Word1_INIT_37 : bit_vector(0 to 255) := x"0BA0099F198E2D8A2D9B2DAC2DBDE050E0402F352F24851C850B84FA84E988DD";
constant PM_Inst_RAM_Word1_INIT_38 : bit_vector(0 to 255) := x"23880CC5940EE0402F642F752F862F97CEFCCEF9F40807B507A4079317820BB1";
constant PM_Inst_RAM_Word1_INIT_39 : bit_vector(0 to 255) := x"2ED92EC8B7DEB7CD920F93CF93DF931F930F92FF92EF92DF92CFCFC3CF95F009";
constant PM_Inst_RAM_Word1_INIT_3A : bit_vector(0 to 255) := x"E0414F7F5F6F2F7D2F6C2D9D2D8C8514850384F284E1F080308281842FF92FE8";
constant PM_Inst_RAM_Word1_INIT_3B : bit_vector(0 to 255) := x"90EF90FF910F911F91DF91CF900F2F932F82E030E020F07197010662940EE050";
constant PM_Inst_RAM_Word1_INIT_3C : bit_vector(0 to 255) := x"87B487A3879287811DB11DA1964F85B485A3859285812DFD2DEC950890CF90DF";
constant PM_Inst_RAM_Word1_INIT_3D : bit_vector(0 to 255) := x"F7E195EA1F330F22E0E5E0302F28708F2D8EF7D195FA94E794F795079516E0F5";
constant PM_Inst_RAM_Word1_INIT_3E : bit_vector(0 to 255) := x"2FE6C045F0092388818C2F172F062FD92FC893DF93CF931F930FCFD44F3E5E2C";
constant PM_Inst_RAM_Word1_INIT_3F : bit_vector(0 to 255) := x"0F88E045E0B0E0A08D918D808E198E188A1F8A1E838CE082F4B1318089872FF7";
-- BRAM 0 in address space [0x00001000:0x000017FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word2 LOC = RAMB16_X0Y1;
constant PM_Inst_RAM_Word2_INIT_00 : bit_vector(0 to 255) := x"2FF72FE6838CE083F5413280C0188BBD8BAC8B9B8B8AF7D1954A1FBB1FAA1F99";
constant PM_Inst_RAM_Word2_INIT_01 : bit_vector(0 to 255) := x"0FE8940E2F912F804F3F5E2E2F3D2F2C8F798F688B5F8B4E8D758D648D538D42";
constant PM_Inst_RAM_Word2_INIT_02 : bit_vector(0 to 255) := x"861E861D861C861B861A86198618821F821E821D838BE0818F0A8F1BF0912388";
constant PM_Inst_RAM_Word2_INIT_03 : bit_vector(0 to 255) := x"2F142FD92FC893DF93CF931F9508910F911F91CF91DFE080C0018A198A18861F";
constant PM_Inst_RAM_Word2_INIT_04 : bit_vector(0 to 255) := x"C057F00974822F84F021718185834FFE5EECF7E1957A1FFF0FEEE075E0F02FE6";
constant PM_Inst_RAM_Word2_INIT_05 : bit_vector(0 to 255) := x"E0A0899589848BB887AF879E878D00FC91B000FB91A000FA919000F991808B69";
constant PM_Inst_RAM_Word2_INIT_06 : bit_vector(0 to 255) := x"8F688B5F8B4E2B7B2B6A2B592B48E0B0E0A08D938D82274427552F792F68E0B0";
constant PM_Inst_RAM_Word2_INIT_07 : bit_vector(0 to 255) := x"E0818BBD8BAC8B9B8B8A8DB78DA68D958D84F451970070907188E09085838F79";
constant PM_Inst_RAM_Word2_INIT_08 : bit_vector(0 to 255) := x"2F81838CE084F0D123880FE8940E8D9B8D8A4F3F5E2E2F3D2F2CF5219740C00D";
constant PM_Inst_RAM_Word2_INIT_09 : bit_vector(0 to 255) := x"2F9D2F8CC00AE081C002FD16861C861B861A86198618821F821E821D838B708F";
constant PM_Inst_RAM_Word2_INIT_0A : bit_vector(0 to 255) := x"2FD92FC893DF93CF9508911F91CF91DFE080C0010580940EE070E060E050E040";
constant PM_Inst_RAM_Word2_INIT_0B : bit_vector(0 to 255) := x"899F898EF0A123881061940EE070E060E050E0418D9B8D8A4F3F5F2B2F392F28";
constant PM_Inst_RAM_Word2_INIT_0C : bit_vector(0 to 255) := x"6880818B8FB98FA88B9F8B8E85B881AF819E818DF45905B105A197008DB98DA8";
constant PM_Inst_RAM_Word2_INIT_0D : bit_vector(0 to 255) := x"92DF92CF92BF92AF929F928F927F925F924F923F922F950891CF91DFE081838B";
constant PM_Inst_RAM_Word2_INIT_0E : bit_vector(0 to 255) := x"835E2F072F162ED92EC8B7DEB7CDD000D000D00093CF93DF931F930F92FF92EF";
constant PM_Inst_RAM_Word2_INIT_0F : bit_vector(0 to 255) := x"2DFD2DECC1B1C191FF81918C9613C195F00930819714918C96142FB92FA8834D";
constant PM_Inst_RAM_Word2_INIT_10 : bit_vector(0 to 255) := x"940E2D9D2D8CF03907B707A60795178485B485A3859285818975896489538942";
constant PM_Inst_RAM_Word2_INIT_11 : bit_vector(0 to 255) := x"91FC91ED965A2DBD2DACC132803E802D2E532E422F302F21C17AF4092388044E";
constant PM_Inst_RAM_Word2_INIT_12 : bit_vector(0 to 255) := x"EF7F2278947A8074F7D1951A9587959795A795B6E0192F822F932FA42FB5975B";
constant PM_Inst_RAM_Word2_INIT_13 : bit_vector(0 to 255) := x"914D96152DBD2DACC053F00904911481C057F0092077229322822E97E0712E87";
constant PM_Inst_RAM_Word2_INIT_14 : bit_vector(0 to 255) := x"97002DA091BC900D919D918D9656F48905710561055115419718917C916D915D";
constant PM_Inst_RAM_Word2_INIT_15 : bit_vector(0 to 255) := x"4F3F5F2F2F3D2F2C2F9F2F8EC03587B083A7839683852DFD2DECF17905B105A1";
constant PM_Inst_RAM_Word2_INIT_16 : bit_vector(0 to 255) := x"91FC91ED965A2DBD2DAC815C814B813A8129C12EE050E040F41923880F04940E";
constant PM_Inst_RAM_Word2_INIT_17 : bit_vector(0 to 255) := x"074A07391728E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987975B";
constant PM_Inst_RAM_Word2_INIT_18 : bit_vector(0 to 255) := x"E08087508347833683252DFD2DECC105F439238808AC940E2D9D2D8CF038075B";
constant PM_Inst_RAM_Word2_INIT_19 : bit_vector(0 to 255) := x"975B91FC91ED965A2DBD2DAC2EB92EA8F410059315822CB32CA209991988E092";
constant PM_Inst_RAM_Word2_INIT_1A : bit_vector(0 to 255) := x"C00484051F1B1F0A1EF90EE8EFBFEFAFEF9FEF8E9718911C910D90FD90ED9615";
constant PM_Inst_RAM_Word2_INIT_1B : bit_vector(0 to 255) := x"1CF10CE71F1B1F0A1EF90EE889B189A085978586F7D2940A1F111F001CFF0CEE";
constant PM_Inst_RAM_Word2_INIT_1C : bit_vector(0 to 255) := x"158E00FC91B000FB91A000FA919000F99180F56906B9E09216A9E0901D111D01";
constant PM_Inst_RAM_Word2_INIT_1D : bit_vector(0 to 255) := x"00FC93B000FB93A000FA939000F99380EFBFEFAFEF9FEF8FF46107B107A0059F";
constant PM_Inst_RAM_Word2_INIT_1E : bit_vector(0 to 255) := x"E0A0C09FF4092388020E940E2D352D242D4E2D5F2F602F710315919003149180";
constant PM_Inst_RAM_Word2_INIT_1F : bit_vector(0 to 255) := x"89A48993898285548543853285212DFD2DECF51104911481C0451E5B0E4AE0B2";
constant PM_Inst_RAM_Word2_INIT_20 : bit_vector(0 to 255) := x"930000FA92F000F992E0C083F40923880C64940EF098075B074A0739172889B5";
constant PM_Inst_RAM_Word2_INIT_21 : bit_vector(0 to 255) := x"0CC5940EE0412D6E2D7F2F802F91C00A0316938060810316918000FC931000FB";
constant PM_Inst_RAM_Word2_INIT_22 : bit_vector(0 to 255) := x"C0022FF32FE22DB52DA41D5B0D4A2F532F424F3E5E2C2D392D28C06BF4092388";
constant PM_Inst_RAM_Word2_INIT_23 : bit_vector(0 to 255) := x"2DECE050E0402D3B2D2A083B182A1E5F0E4E0BF31BE2F7D907F517E49381918D";
constant PM_Inst_RAM_Word2_INIT_24 : bit_vector(0 to 255) := x"96192DBD2DAC87B487A3879287811FB51FA41F930F8285B485A3859285812DFD";
constant PM_Inst_RAM_Word2_INIT_25 : bit_vector(0 to 255) := x"17822DA091BC900D919D918D9652CEC2F00904311421971C915C914D913D912D";
constant PM_Inst_RAM_Word2_INIT_26 : bit_vector(0 to 255) := x"01129180C0128383688081838B558B448B338B222DFD2DECF45007B507A40793";
constant PM_Inst_RAM_Word2_INIT_27 : bit_vector(0 to 255) := x"938C961368809713918C96132DBD2DACF0412B89819E818DF0612B8901139190";
constant PM_Inst_RAM_Word2_INIT_28 : bit_vector(0 to 255) := x"2DACE081C007815E814DF0192388051E940E2D9D2D8CC006FF8381832DFD2DEC";
constant PM_Inst_RAM_Word2_INIT_29 : bit_vector(0 to 255) := x"911F91DF91CFBFCDBE0FBFDE94F8B60F96262F952F84EF5FEF4F938C96122DBD";
constant PM_Inst_RAM_Word2_INIT_2A : bit_vector(0 to 255) := x"FD829508902F903F904F905F907F908F909F90AF90BF90CF90DF90EF90FF910F";
constant PM_Inst_RAM_Word2_INIT_2B : bit_vector(0 to 255) := x"08D5940E2F5B2F4A0BBF1BAE9711F7E92000900D2FBF2FAE2FF72FE6CE62CE4D";
constant PM_Inst_RAM_Word2_INIT_2C : bit_vector(0 to 255) := x"900F08D5940EE050E0414F7F5F6F2F7D2F6C8369B7DEB7CD920F93CF93DF9508";
constant PM_Inst_RAM_Word2_INIT_2D : bit_vector(0 to 255) := x"F409238808AC940E2FD92FC893DF93CF931F930F92FF92EF92DF950891DF91CF";
constant PM_Inst_RAM_Word2_INIT_2E : bit_vector(0 to 255) := x"84051F1B1F0A1EF90EE8EFBFEFAFEF9FEF8E8518810F80FE80ED8DFB8DEAC050";
constant PM_Inst_RAM_Word2_INIT_2F : bit_vector(0 to 255) := x"80D41F1B1F0A1EF90EE889B189A085978586F7D2940A1F111F001CFF0CEEC004";
constant PM_Inst_RAM_Word2_INIT_30 : bit_vector(0 to 255) := x"0C9F940E1D911D811D710D6D2D6E2D7F2F802F91C00D0911090108F108E19408";
constant PM_Inst_RAM_Word2_INIT_31 : bit_vector(0 to 255) := x"1F441F330F22C0048405E050E040E032E0208DFB8DEAF78920DD94DAF0F92388";
constant PM_Inst_RAM_Word2_INIT_32 : bit_vector(0 to 255) := x"E0818BBD8BAC8B9B8B8A1FB51FA41F930F8289BD89AC899B898AF7D2940A1F55";
constant PM_Inst_RAM_Word2_INIT_33 : bit_vector(0 to 255) := x"92BF92AF929F928F927F926F950890DF90EF90FF910F911F91CF91DFE080C001";
constant PM_Inst_RAM_Word2_INIT_34 : bit_vector(0 to 255) := x"BFCDBE0FBFDE94F8B60F972BB7DEB7CD93CF93DF931F930F92FF92EF92DF92CF";
constant PM_Inst_RAM_Word2_INIT_35 : bit_vector(0 to 255) := x"2F1D2F0C2F952F84C0F2F0092388918C96142FB92FA82E822ED72EC62EB92EA8";
constant PM_Inst_RAM_Word2_INIT_36 : bit_vector(0 to 255) := x"965B2DBB2DAA8D938D822DFD2DECC0E5F40923880407940E2F712F604F1F5F0F";
constant PM_Inst_RAM_Word2_INIT_37 : bit_vector(0 to 255) := x"2499971C921C921D921D921D96192DBD2DAC8610821782168215975A938E939C";
constant PM_Inst_RAM_Word2_INIT_38 : bit_vector(0 to 255) := x"9516E085C0C0F40997002FF92FE80793940E2D9D2D8CC0492E792E602F912F80";
constant PM_Inst_RAM_Word2_INIT_39 : bit_vector(0 to 255) := x"2DBB2DAAF4992099F4D93E85F01123888180701F2D1EF7D1958A94E794F79507";
constant PM_Inst_RAM_Word2_INIT_3A : bit_vector(0 to 255) := x"935C934D933D932D961D00FC915000FB914000FA913000F991209751931C9651";
constant PM_Inst_RAM_Word2_INIT_3B : bit_vector(0 to 255) := x"2F2800C9940EE050E04B2F7F2F6E2D972D86C02794932499F4C1238881809750";
constant PM_Inst_RAM_Word2_INIT_3C : bit_vector(0 to 255) := x"2DFD2DEC94932499C07E2F612D9B2D8AC086F409338073802D88F4592B232F39";
constant PM_Inst_RAM_Word2_INIT_3D : bit_vector(0 to 255) := x"71822D88CFA7F408071B070A06F916E889B589A4899389828514850384F284E1";
constant PM_Inst_RAM_Word2_INIT_3E : bit_vector(0 to 255) := x"2DACC05FF4A197002F192F0804FF940EE0612D9B2D8AF0512099C06BF0093182";
constant PM_Inst_RAM_Word2_INIT_3F : bit_vector(0 to 255) := x"8A112DFB2DEAC051F40923880AD3940E2D9D2D8CC058F4093082918C96142DBD";
-- BRAM 0 in address space [0x00001800:0x00001FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word3 LOC = RAMB16_X0Y3;
constant PM_Inst_RAM_Word3_INIT_00 : bit_vector(0 to 255) := x"920D9001E08B96312FFD2FEC2FB12FA0F7E9958A921D2FB12FA0E280E011E104";
constant PM_Inst_RAM_Word3_INIT_01 : bit_vector(0 to 255) := x"950996402F912F804F7F5F622F712F60F0499730011391F0011291E0F7E15081";
constant PM_Inst_RAM_Word3_INIT_02 : bit_vector(0 to 255) := x"919C918D96502FB12FA087868797E098E0808B808B912FF12FE0E298E281C00A";
constant PM_Inst_RAM_Word3_INIT_03 : bit_vector(0 to 255) := x"938E939C9657971F919C918D961E9758938E939C96599752938E939C96539751";
constant PM_Inst_RAM_Word3_INIT_04 : bit_vector(0 to 255) := x"962BE080C001083A940E2D4889612DFB2DEA2D9B2D8AF04923880C64940E9756";
constant PM_Inst_RAM_Word3_INIT_05 : bit_vector(0 to 255) := x"909F90AF90BF90CF90DF90EF90FF910F911F91DF91CFBFCDBE0FBFDE94F8B60F";
constant PM_Inst_RAM_Word3_INIT_06 : bit_vector(0 to 255) := x"00FC917000FB916000FA915000F99140F1992388031691809508906F907F908F";
constant PM_Inst_RAM_Word3_INIT_07 : bit_vector(0 to 255) := x"031991600318915003179140F1192388020E940EE031E1240315919003149180";
constant PM_Inst_RAM_Word3_INIT_08 : bit_vector(0 to 255) := x"2388020E940EE031E1240315919003149180F0910571056105511541031A9170";
constant PM_Inst_RAM_Word3_INIT_09 : bit_vector(0 to 255) := x"92EF9508E0809508E08103169210031A9210031992100318921003179210F061";
constant PM_Inst_RAM_Word3_INIT_0A : bit_vector(0 to 255) := x"31E4E0839211E0F1E1E4F0A923880C64940E2F192F082EF72EE6931F930F92FF";
constant PM_Inst_RAM_Word3_INIT_0B : bit_vector(0 to 255) := x"E0810316938060810316918000FC931000FB930000FA92F000F992E0F7D907F8";
constant PM_Inst_RAM_Word3_INIT_0C : bit_vector(0 to 255) := x"91802ED42F192F082EF72EE6931F930F92FF92EF92DF950890EF90FF910F911F";
constant PM_Inst_RAM_Word3_INIT_0D : bit_vector(0 to 255) := x"F0E923880C64940EF0D107B107A0059F158E00FC91B000FB91A000FA919000F9";
constant PM_Inst_RAM_Word3_INIT_0E : bit_vector(0 to 255) := x"00F992E0F0792388031E940EE031E1242D4E2D5F2F602F710315919003149180";
constant PM_Inst_RAM_Word3_INIT_0F : bit_vector(0 to 255) := x"910F911FE080C001E08103169380298D0316918000FC931000FB930000FA92F0";
constant PM_Inst_RAM_Word3_INIT_10 : bit_vector(0 to 255) := x"93DF93CF931F930F92FF92EF92DF92CF92BF92AF929F928F950890DF90EF90FF";
constant PM_Inst_RAM_Word3_INIT_11 : bit_vector(0 to 255) := x"F0083045C04124BB24AA24992488F429234403149360031593702F142ED92EC8";
constant PM_Inst_RAM_Word3_INIT_12 : bit_vector(0 to 255) := x"2FFD2FEC9721E0D02FC1C122F40923880CC5940EE040E090E080E070E060C12C";
constant PM_Inst_RAM_Word3_INIT_13 : bit_vector(0 to 255) := x"2B897090778FE09040F15BEE81804FFE54E24FFE5EECF7E1957A1FFF0FEEE074";
constant PM_Inst_RAM_Word3_INIT_14 : bit_vector(0 to 255) := x"0FCCE064C0FFF40805B105A10591368481B381A2819181804FFE53E6C10BF009";
constant PM_Inst_RAM_Word3_INIT_15 : bit_vector(0 to 255) := x"2D9BC0EEF40904B104A10491148180BB80AA809980884FDD52C6F7E1956A1FDD";
constant PM_Inst_RAM_Word3_INIT_16 : bit_vector(0 to 255) := x"F0094092508001209190011F9180C0E4F40923880CC5940EE0402D682D792D8A";
constant PM_Inst_RAM_Word3_INIT_17 : bit_vector(0 to 255) := x"238801219180C0D0F4092B890123919001229180C0D7F409232201249120C0DC";
constant PM_Inst_RAM_Word3_INIT_18 : bit_vector(0 to 255) := x"87452DFD2DEC5F4FC008E070E06186158384012191808B222DFD2DECC0CBF409";
constant PM_Inst_RAM_Word3_INIT_19 : bit_vector(0 to 255) := x"940A1F330F22C0022E042F372F26E090818485452DFD2DECC0B9F00830485041";
constant PM_Inst_RAM_Word3_INIT_1A : bit_vector(0 to 255) := x"01389120C008E050E040F01905311521012B9130012A9120F74107931782F7E2";
constant PM_Inst_RAM_Word3_INIT_1B : bit_vector(0 to 255) := x"012390F0012290E087508347833683252DFD2DEC013B9150013A914001399130";
constant PM_Inst_RAM_Word3_INIT_1C : bit_vector(0 to 255) := x"8F808F9101269190012591808B168B058AF48AE31D1B1D0A1CF90CE8E010E000";
constant PM_Inst_RAM_Word3_INIT_1D : bit_vector(0 to 255) := x"8F848F738F622DFD2DEC1F911F801D7F0D6E18A2940EE090E080E07001249160";
constant PM_Inst_RAM_Word3_INIT_1E : bit_vector(0 to 255) := x"E040952627332F234F3E5021F7E1955A1F330F22E05501269130012591208F95";
constant PM_Inst_RAM_Word3_INIT_1F : bit_vector(0 to 255) := x"E0A0F019970001289190012791808B518B40873787261F591F481F370F26E050";
constant PM_Inst_RAM_Word3_INIT_20 : bit_vector(0 to 255) := x"0AF31AE22CE82CF92D0A2D1B013791B0013691A00135919001349180C008E0B0";
constant PM_Inst_RAM_Word3_INIT_21 : bit_vector(0 to 255) := x"95479556C00484052DFD2DEC1F5B1F4A1F390F282D2E2D3F2F402F510B150B04";
constant PM_Inst_RAM_Word3_INIT_22 : bit_vector(0 to 255) := x"F410075FE0F0074FE0F0073FE0FF3F258754874387328721F7D2940A95279537";
constant PM_Inst_RAM_Word3_INIT_23 : bit_vector(0 to 255) := x"919001409180C011E0818B872DFD2DECE180F430405040404F3F5F25C006E08C";
constant PM_Inst_RAM_Word3_INIT_24 : bit_vector(0 to 255) := x"91CF91DFE080CFEDE2808FB58FA48F938F822DFD2DEC014391B0014291A00141";
constant PM_Inst_RAM_Word3_INIT_25 : bit_vector(0 to 255) := x"928F927F926F925F924F9508908F909F90AF90BF90CF90DF90EF90FF910F911F";
constant PM_Inst_RAM_Word3_INIT_26 : bit_vector(0 to 255) := x"2EE62ED52EC42FD92FC893DF93CF931F930F92FF92EF92DF92CF92BF92AF929F";
constant PM_Inst_RAM_Word3_INIT_27 : bit_vector(0 to 255) := x"960185BC85AB859A8589C077F40805710561055130422E732E622E512E402EF7";
constant PM_Inst_RAM_Word3_INIT_28 : bit_vector(0 to 255) := x"2799F4293180898F895E894D893C892BC06AF40807B707A6079517841DB11DA1";
constant PM_Inst_RAM_Word3_INIT_29 : bit_vector(0 to 255) := x"2E86F7D1951A9567957795879596E0172D6C2D7D2D8E2D9FC00B2D6D2D7E2D8F";
constant PM_Inst_RAM_Word3_INIT_2A : bit_vector(0 to 255) := x"168800FC91B000FB91A000FA919000F991801EB51EA41E930E822EB92EA82E97";
constant PM_Inst_RAM_Word3_INIT_2B : bit_vector(0 to 255) := x"F4513180898FF1A923880CC5940EE0402D682D792D8A2D9BF04906BB06AA0699";
constant PM_Inst_RAM_Word3_INIT_2C : bit_vector(0 to 255) := x"1FFF0FEE70F077EF2DFD2DECC00E824082514FFE5EEC1FFF0FEE70F02DFD2DEC";
constant PM_Inst_RAM_Word3_INIT_2D : bit_vector(0 to 255) := x"F0803082898A0316938060810316918082738262825182404FFE5EEC1FFF0FEE";
constant PM_Inst_RAM_Word3_INIT_2E : bit_vector(0 to 255) := x"031A92B0031992A003189290031792801EBB1EAA1E990E8885B881AF819E818D";
constant PM_Inst_RAM_Word3_INIT_2F : bit_vector(0 to 255) := x"907F908F909F90AF90BF90CF90DF90EF90FF910F911F91CF91DFE080C001E081";
constant PM_Inst_RAM_Word3_INIT_30 : bit_vector(0 to 255) := x"2EF52EE42FD92FC893DF93CF931F930F92FF92EF92DF92CF9508904F905F906F";
constant PM_Inst_RAM_Word3_INIT_31 : bit_vector(0 to 255) := x"F40807B707A6079517841DB11DA1960185BC85AB859A85892ED32EC22F172F06";
constant PM_Inst_RAM_Word3_INIT_32 : bit_vector(0 to 255) := x"2D7F2F802F91C00B2D6F2F702F812799F4293180898F895E894D893C892BC057";
constant PM_Inst_RAM_Word3_INIT_33 : bit_vector(0 to 255) := x"00FA919000F991801F591F481F370F26F7D195EA9567957795879596E0E72D6E";
constant PM_Inst_RAM_Word3_INIT_34 : bit_vector(0 to 255) := x"0CC5940EE0402F622F732F842F95F049075B074A0739172800FC91B000FB91A0";
constant PM_Inst_RAM_Word3_INIT_35 : bit_vector(0 to 255) := x"E0B0E0A0819181804FFE5EEC1FFF0FEE70F02DFF2DEEF4613180898FF1312388";
constant PM_Inst_RAM_Word3_INIT_36 : bit_vector(0 to 255) := x"70BF81B381A2819181804FFE5EEC1FFF0FEE1FFF0FEE70F077EF2DFF2DEEC00F";
constant PM_Inst_RAM_Word3_INIT_37 : bit_vector(0 to 255) := x"90DF90EF90FF910F911F91CF91DFE080C001E08183B383A2839183802DFD2DEC";
constant PM_Inst_RAM_Word3_INIT_38 : bit_vector(0 to 255) := x"B7DEB7CDD000D00093CF93DF931F930F92FF92EF92DF92CF92BF92AF950890CF";
constant PM_Inst_RAM_Word3_INIT_39 : bit_vector(0 to 255) := x"83B383A2839183802DFD2DECE0B0E0A0E090E0822F172F062EF52EE42ED92EC8";
constant PM_Inst_RAM_Word3_INIT_3A : bit_vector(0 to 255) := x"23880F04940E2D3B2D2A2D4E2D5F2F602F712D9D2D8C1CB11CA194082EBD2EAC";
constant PM_Inst_RAM_Word3_INIT_3B : bit_vector(0 to 255) := x"80E9F0C923880E5B940EE030E020E010E0002D4E2D5F2F602F712D9D2D8CF139";
constant PM_Inst_RAM_Word3_INIT_3C : bit_vector(0 to 255) := x"E0A0EF9FEF88C004E0BFEFAFEF9FEF88F029318089872DFD2DEC811C810B80FA";
constant PM_Inst_RAM_Word3_INIT_3D : bit_vector(0 to 255) := x"911F91DF91CF900F900F900F900FE080C001E081F278071B070A06F916E8E0B0";
constant PM_Inst_RAM_Word3_INIT_3E : bit_vector(0 to 255) := x"92BF92AF929F928F927F926F925F924F950890AF90BF90CF90DF90EF90FF910F";
constant PM_Inst_RAM_Word3_INIT_3F : bit_vector(0 to 255) := x"835A83492ED92EC8B7DEB7CDD000D00093CF93DF931F930F92FF92EF92DF92CF";
-- BRAM 0 in address space [0x00002000:0x000027FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word4 LOC = RAMB16_X0Y2;
constant PM_Inst_RAM_Word4_INIT_00 : bit_vector(0 to 255) := x"2E9AE0A22C811C511C4194082E5D2E4C2711270024FF24EE2E732E62837C836B";
constant PM_Inst_RAM_Word4_INIT_01 : bit_vector(0 to 255) := x"2DAA2DBBF17123880F04940E2D352D242D9D2D8C817C816B815A81492CB12CA1";
constant PM_Inst_RAM_Word4_INIT_02 : bit_vector(0 to 255) := x"1F1B1F0A1EF90EE8F7D2940A1FBB1FAA1F990F88C00484052DFD2DEC2D882D99";
constant PM_Inst_RAM_Word4_INIT_03 : bit_vector(0 to 255) := x"E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987815C814B813A8129";
constant PM_Inst_RAM_Word4_INIT_04 : bit_vector(0 to 255) := x"900F900F900F900FE0818313830282F182E02DF72DE6F268075B074A07391728";
constant PM_Inst_RAM_Word4_INIT_05 : bit_vector(0 to 255) := x"904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F91DF91CF";
constant PM_Inst_RAM_Word4_INIT_06 : bit_vector(0 to 255) := x"930F92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922F9508";
constant PM_Inst_RAM_Word4_INIT_07 : bit_vector(0 to 255) := x"876C875B874A2E392E28BFCDBE0FBFDE94F8B60F972FB7DEB7CD93CF93DF931F";
constant PM_Inst_RAM_Word4_INIT_08 : bit_vector(0 to 255) := x"2E912E80F0590531052105111501913C912D911D910D2FB32FA2872E873F877D";
constant PM_Inst_RAM_Word4_INIT_09 : bit_vector(0 to 255) := x"861980B380A2809180802FF92FE8C01186191CB11CA11C911C8194082EB32EA2";
constant PM_Inst_RAM_Word4_INIT_0A : bit_vector(0 to 255) := x"900D919D918D96192DB32DA28799E091F41105B105A1970185BD85AC859B858A";
constant PM_Inst_RAM_Word4_INIT_0B : bit_vector(0 to 255) := x"2466245524442CC82CD92CEA2CFB87B883AF839E838D1DB11DA196012DA091BC";
constant PM_Inst_RAM_Word4_INIT_0C : bit_vector(0 to 255) := x"F008067B066A0659164885B485A3859285812DF32DE24F1F5F0F2F1D2F0C2477";
constant PM_Inst_RAM_Word4_INIT_0D : bit_vector(0 to 255) := x"E0B22CB12CA12C912E88E082F45005BF05AE059D158C85B881AF819E818DC0A8";
constant PM_Inst_RAM_Word4_INIT_0E : bit_vector(0 to 255) := x"F40923880F04940E2F312F202D4C2D5D2D6E2D7F2D932D822CF12CE12CD12ECB";
constant PM_Inst_RAM_Word4_INIT_0F : bit_vector(0 to 255) := x"05B105A197004F5F4F4F4F3F5F2F2D2C2D3D2D4E2D5F81BC81AB819A8189C088";
constant PM_Inst_RAM_Word4_INIT_10 : bit_vector(0 to 255) := x"0739172885BD85AC859B858A095B094A09391928C00D2EB52EA42E932E82F029";
constant PM_Inst_RAM_Word4_INIT_11 : bit_vector(0 to 255) := x"2D932D82CFA71CF11CE11CD11CC194081C711C611C511C419408F059075B074A";
constant PM_Inst_RAM_Word4_INIT_12 : bit_vector(0 to 255) := x"2C6E2C5D2C4CC04CF4E123880E5B940EE03FEF2FEF1FEF0F2D7F2D6E2D5D2D4C";
constant PM_Inst_RAM_Word4_INIT_13 : bit_vector(0 to 255) := x"2D0C2D1D2D2E2D3F2D442D552D662D772D932D82087108610851084194082C7F";
constant PM_Inst_RAM_Word4_INIT_14 : bit_vector(0 to 255) := x"914D85BF85AEF30004BF04AE049D148C2CC42CD52CE62CF7F1A923880E5B940E";
constant PM_Inst_RAM_Word4_INIT_15 : bit_vector(0 to 255) := x"0E5B940E2D082D192D2A2D3B2D932D82F0510571056105511541917C916D915D";
constant PM_Inst_RAM_Word4_INIT_16 : bit_vector(0 to 255) := x"1CB11CA11C911C819408F06123FF85F982B382A28291828085FF85EEF0B92388";
constant PM_Inst_RAM_Word4_INIT_17 : bit_vector(0 to 255) := x"BFCDBE0FBFDE94F8B60F962FE080C001E081971392BC92AD929D928D2DB32DA2";
constant PM_Inst_RAM_Word4_INIT_18 : bit_vector(0 to 255) := x"904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F91DF91CF";
constant PM_Inst_RAM_Word4_INIT_19 : bit_vector(0 to 255) := x"9380E0B0E0A0E090E082032692100324921003219210032092109508902F903F";
constant PM_Inst_RAM_Word4_INIT_1A : bit_vector(0 to 255) := x"92100345938003469390E091E081033E9210032A93B0032993A0032893900327";
constant PM_Inst_RAM_Word4_INIT_1B : bit_vector(0 to 255) := x"9380E18A10059380E18910049380E18B95080365921003619380036293900349";
constant PM_Inst_RAM_Word4_INIT_1C : bit_vector(0 to 255) := x"1669940EE070E060E255E840E094E08B20109380E083037E9210037F92101006";
constant PM_Inst_RAM_Word4_INIT_1D : bit_vector(0 to 255) := x"E073E16BE093E287032F940EE14CE061E093E18B1895940EE070E660E094E08B";
constant PM_Inst_RAM_Word4_INIT_1E : bit_vector(0 to 255) := x"E073E267E093E4850D04940EE040E073E16BE093E287F43923880D04940EE041";
constant PM_Inst_RAM_Word4_INIT_1F : bit_vector(0 to 255) := x"E963E094E08BF03123880B3A940EE021E050E848E073E465E093E68107E3940E";
constant PM_Inst_RAM_Word4_INIT_20 : bit_vector(0 to 255) := x"E68120199380037D91800662940EE050E041E073E76DE093E6811895940EE070";
constant PM_Inst_RAM_Word4_INIT_21 : bit_vector(0 to 255) := x"E041E073E76DE093E68120189380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_22 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120179380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_23 : bit_vector(0 to 255) := x"E68120159380037D91800662940EE050E041E073E76DE093E68120169380037D";
constant PM_Inst_RAM_Word4_INIT_24 : bit_vector(0 to 255) := x"E041E073E76DE093E68120149380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_25 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120139380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_26 : bit_vector(0 to 255) := x"E68120219380037D91800662940EE050E041E073E76DE093E68120129380037D";
constant PM_Inst_RAM_Word4_INIT_27 : bit_vector(0 to 255) := x"E041E073E76DE093E68120209380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_28 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681201F9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_29 : bit_vector(0 to 255) := x"E681201D9380037D91800662940EE050E041E073E76DE093E681201E9380037D";
constant PM_Inst_RAM_Word4_INIT_2A : bit_vector(0 to 255) := x"E041E073E76DE093E681201C9380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_2B : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681201B9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_2C : bit_vector(0 to 255) := x"E68120299380037D91800662940EE050E041E073E76DE093E681201A9380037D";
constant PM_Inst_RAM_Word4_INIT_2D : bit_vector(0 to 255) := x"E041E073E76DE093E68120289380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_2E : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120279380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_2F : bit_vector(0 to 255) := x"E68120259380037D91800662940EE050E041E073E76DE093E68120269380037D";
constant PM_Inst_RAM_Word4_INIT_30 : bit_vector(0 to 255) := x"E041E073E76DE093E68120249380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_31 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120239380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_32 : bit_vector(0 to 255) := x"E68120319380037D91800662940EE050E041E073E76DE093E68120229380037D";
constant PM_Inst_RAM_Word4_INIT_33 : bit_vector(0 to 255) := x"E041E073E76DE093E68120309380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_34 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681202F9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_35 : bit_vector(0 to 255) := x"E681202D9380037D91800662940EE050E041E073E76DE093E681202E9380037D";
constant PM_Inst_RAM_Word4_INIT_36 : bit_vector(0 to 255) := x"E041E073E76DE093E681202C9380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_37 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681202B9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_38 : bit_vector(0 to 255) := x"E070EA65E094E08BF43031802F18931F95080573940EE093E681202A9380037D";
constant PM_Inst_RAM_Word4_INIT_39 : bit_vector(0 to 255) := x"972BB7DEB7CD93CF93DF9508911F1876940EE050E1402F61E094E08B1757940E";
constant PM_Inst_RAM_Word4_INIT_3A : bit_vector(0 to 255) := x"037E9210037F9210C175F0099706037F9190037E9180BFCDBE0FBFDE94F8B60F";
constant PM_Inst_RAM_Word4_INIT_3B : bit_vector(0 to 255) := x"2F5D2F4CE073E465E093E681F7E15081920D9001E08BE0F0E8E896112FBD2FAC";
constant PM_Inst_RAM_Word4_INIT_3C : bit_vector(0 to 255) := x"940EE093E681201891600AC1940EE093E681201991600B3A940EE5224F5F5F4F";
constant PM_Inst_RAM_Word4_INIT_3D : bit_vector(0 to 255) := x"E681201591600AC1940EE093E681201691600AC1940EE093E681201791600AC1";
constant PM_Inst_RAM_Word4_INIT_3E : bit_vector(0 to 255) := x"91600AC1940EE093E681201391600AC1940EE093E681201491600AC1940EE093";
constant PM_Inst_RAM_Word4_INIT_3F : bit_vector(0 to 255) := x"940EE093E681202091600AC1940EE093E681202191600AC1940EE093E6812012";
-- BRAM 0 in address space [0x00002800:0x00002FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word5 LOC = RAMB16_X0Y7;
constant PM_Inst_RAM_Word5_INIT_00 : bit_vector(0 to 255) := x"E681201D91600AC1940EE093E681201E91600AC1940EE093E681201F91600AC1";
constant PM_Inst_RAM_Word5_INIT_01 : bit_vector(0 to 255) := x"91600AC1940EE093E681201B91600AC1940EE093E681201C91600AC1940EE093";
constant PM_Inst_RAM_Word5_INIT_02 : bit_vector(0 to 255) := x"940EE093E681202891600AC1940EE093E681202991600AC1940EE093E681201A";
constant PM_Inst_RAM_Word5_INIT_03 : bit_vector(0 to 255) := x"E681202591600AC1940EE093E681202691600AC1940EE093E681202791600AC1";
constant PM_Inst_RAM_Word5_INIT_04 : bit_vector(0 to 255) := x"91600AC1940EE093E681202391600AC1940EE093E681202491600AC1940EE093";
constant PM_Inst_RAM_Word5_INIT_05 : bit_vector(0 to 255) := x"940EE093E681203091600AC1940EE093E681203191600AC1940EE093E6812022";
constant PM_Inst_RAM_Word5_INIT_06 : bit_vector(0 to 255) := x"E681202D91600AC1940EE093E681202E91600AC1940EE093E681202F91600AC1";
constant PM_Inst_RAM_Word5_INIT_07 : bit_vector(0 to 255) := x"91600AC1940EE093E681202B91600AC1940EE093E681202C91600AC1940EE093";
constant PM_Inst_RAM_Word5_INIT_08 : bit_vector(0 to 255) := x"91801388940E201A91801895940EE070EA67E094E08B0AC1940EE093E681202A";
constant PM_Inst_RAM_Word5_INIT_09 : bit_vector(0 to 255) := x"91801388940E201E91801388940E201D91801388940E201C91801388940E201B";
constant PM_Inst_RAM_Word5_INIT_0A : bit_vector(0 to 255) := x"940EE070EB6CE094E08B1388940E202191801388940E202091801388940E201F";
constant PM_Inst_RAM_Word5_INIT_0B : bit_vector(0 to 255) := x"940E201591801388940E201491801388940E201391801388940E201291801895";
constant PM_Inst_RAM_Word5_INIT_0C : bit_vector(0 to 255) := x"940E201991801388940E201891801388940E201791801388940E201691801388";
constant PM_Inst_RAM_Word5_INIT_0D : bit_vector(0 to 255) := x"91801388940E202B91801388940E202A91801895940EE070ED61E094E08B1388";
constant PM_Inst_RAM_Word5_INIT_0E : bit_vector(0 to 255) := x"91801388940E202F91801388940E202E91801388940E202D91801388940E202C";
constant PM_Inst_RAM_Word5_INIT_0F : bit_vector(0 to 255) := x"940E202291801895940EE070EE65E094E08B1388940E203191801388940E2030";
constant PM_Inst_RAM_Word5_INIT_10 : bit_vector(0 to 255) := x"940E202691801388940E202591801388940E202491801388940E202391801388";
constant PM_Inst_RAM_Word5_INIT_11 : bit_vector(0 to 255) := x"940EE093E6811388940E202991801388940E202891801388940E202791801388";
constant PM_Inst_RAM_Word5_INIT_12 : bit_vector(0 to 255) := x"1591940EE090E080E077ED60037E9380037F93909601037F9190037E91800573";
constant PM_Inst_RAM_Word5_INIT_13 : bit_vector(0 to 255) := x"933F932F2411920FB60F920F921F950891DF91CFBFCDBE0FBFDE94F8B60F962B";
constant PM_Inst_RAM_Word5_INIT_14 : bit_vector(0 to 255) := x"1DA1960103889130038791B0038691A0038591900384918093BF93AF939F938F";
constant PM_Inst_RAM_Word5_INIT_15 : bit_vector(0 to 255) := x"93A00385939003849380038893201DB11DA19601572DF020372D5F2D2F231DB1";
constant PM_Inst_RAM_Word5_INIT_16 : bit_vector(0 to 255) := x"038093801DB11DA19601038391B0038291A00381919003809180038793B00386";
constant PM_Inst_RAM_Word5_INIT_17 : bit_vector(0 to 255) := x"901F900FBE0F900F912F913F918F919F91AF91BF038393B0038293A003819390";
constant PM_Inst_RAM_Word5_INIT_18 : bit_vector(0 to 255) := x"2F952F842F732F62BF8F0387915003869140038591300384912094F8B78F9518";
constant PM_Inst_RAM_Word5_INIT_19 : bit_vector(0 to 255) := x"9160038591500384914094F8B78F2F192F082EF72EE6931F930F92FF92EF9508";
constant PM_Inst_RAM_Word5_INIT_1A : bit_vector(0 to 255) := x"1B84BF2F038791B0038691A0038591900384918094F8B72FBF8F038791700386";
constant PM_Inst_RAM_Word5_INIT_1B : bit_vector(0 to 255) := x"6084B7839478950890EF90FF910F911FF760071B070A06F916E80BB70BA60B95";
constant PM_Inst_RAM_Word5_INIT_1C : bit_vector(0 to 255) := x"BD856082B585BD8F6081B58FBD8E6081B58EBD8E6082B58EBF876081B787BF83";
constant PM_Inst_RAM_Word5_INIT_1D : bit_vector(0 to 255) := x"4F3F56262D9095C82FF92FE84F9F53862F932F82E0302F289508BD856081B585";
constant PM_Inst_RAM_Word5_INIT_1E : bit_vector(0 to 255) := x"95C896312DA095C84FFF59E01FFF0FEEE0F02FE8F0A923882D8095C82FF32FE2";
constant PM_Inst_RAM_Word5_INIT_1F : bit_vector(0 to 255) := x"2F952F84E0502F489508938C2B89918C9508938C23899590918CF42923662DB0";
constant PM_Inst_RAM_Word5_INIT_20 : bit_vector(0 to 255) := x"4F5F56462D9095C82FF92FE84F9F53862F952F842D2095C82FF92FE84F9F5086";
constant PM_Inst_RAM_Word5_INIT_21 : bit_vector(0 to 255) := x"B58FF4213024C004778FB58FF4193023F0B12322F16923332D3095C82FF52FE4";
constant PM_Inst_RAM_Word5_INIT_22 : bit_vector(0 to 255) := x"E0F02FE3BD857D8FB585F4193025C005BF837D8FB783F4213021C00BBD8F7D8F";
constant PM_Inst_RAM_Word5_INIT_23 : bit_vector(0 to 255) := x"9508938C23899590918CF42923662DB095C896312DA095C84FFF58E21FFF0FEE";
constant PM_Inst_RAM_Word5_INIT_24 : bit_vector(0 to 255) := x"91E0B12C93FF93EF939F938F932F2411920FB60F920F921F9508938C2B89918C";
constant PM_Inst_RAM_Word5_INIT_25 : bit_vector(0 to 255) := x"91FF0409939083204FFC57E7E0F0F0311798040A918050E1779F2F9E5FEF0409";
constant PM_Inst_RAM_Word5_INIT_26 : bit_vector(0 to 255) := x"2F242F192F08931F930F92FF92EF9518901F900FBE0F900F912F918F919F91EF";
constant PM_Inst_RAM_Word5_INIT_27 : bit_vector(0 to 255) := x"502118E4940EE090E18EE874E860971590FC90ED96142FB92FA82F572F462F35";
constant PM_Inst_RAM_Word5_INIT_28 : bit_vector(0 to 255) := x"83202DFF2DEE18E4940EE050E040E030E0222F622F732F842F95405040404030";
constant PM_Inst_RAM_Word5_INIT_29 : bit_vector(0 to 255) := x"0F88C002971C900C961C2F952F84E050E0418120971791FC91ED96162FB12FA0";
constant PM_Inst_RAM_Word5_INIT_2A : bit_vector(0 to 255) := x"C002971D900C961D2F952F848120971791FC91ED961683202B28F7E2940A1F99";
constant PM_Inst_RAM_Word5_INIT_2B : bit_vector(0 to 255) := x"1F550F44C002900C961E8180971791FC91ED961683202B28F7E2940A1F990F88";
constant PM_Inst_RAM_Word5_INIT_2C : bit_vector(0 to 255) := x"E090918C852785B185A02FF92FE8950890EF90FF910F911F83802B84F7E2940A";
constant PM_Inst_RAM_Word5_INIT_2D : bit_vector(0 to 255) := x"9390E091E08B950883602DE085F38402CFF6FF80F7E2940A95879595C0022E02";
constant PM_Inst_RAM_Word5_INIT_2E : bit_vector(0 to 255) := x"E28A040F938004109390E090E289040D9380040E9390E093E889040B9380040C";
constant PM_Inst_RAM_Word5_INIT_2F : bit_vector(0 to 255) := x"938004169390E090E28C0413938004149390E090E28B0411938004129390E090";
constant PM_Inst_RAM_Word5_INIT_30 : bit_vector(0 to 255) := x"15BD940E9508041A9380E08504199380E08704189380E08304179380E0840415";
constant PM_Inst_RAM_Word5_INIT_31 : bit_vector(0 to 255) := x"2FA09621C00B2FD72FC62F192F0893DF93CF931F930FCFFD139B940E11B8940E";
constant PM_Inst_RAM_Word5_INIT_32 : bit_vector(0 to 255) := x"910F911F91CF91DFF7912366816895092F912F802DE081F0900191FC91ED2FB1";
constant PM_Inst_RAM_Word5_INIT_33 : bit_vector(0 to 255) := x"2DBF2DAEC0102FD52FC42EF72EE62F192F0893DF93CF931F930F92FF92EF9508";
constant PM_Inst_RAM_Word5_INIT_34 : bit_vector(0 to 255) := x"F7719720972195092F912F802DE081F0900191FC91ED2FB12FA02EFB2EEA916D";
constant PM_Inst_RAM_Word5_INIT_35 : bit_vector(0 to 255) := x"950895092DE081F3800291FC91ED2FB92FA8950890EF90FF910F911F91CF91DF";
constant PM_Inst_RAM_Word5_INIT_36 : bit_vector(0 to 255) := x"931F930F92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922F";
constant PM_Inst_RAM_Word5_INIT_37 : bit_vector(0 to 255) := x"2EF72EE62ED52EC42E392E28BFCDBE0FBFDE94F8B60F97A0B7DEB7CD93CF93DF";
constant PM_Inst_RAM_Word5_INIT_38 : bit_vector(0 to 255) := x"24992488C06A1821940EE030E020E070E060E050E340F4490571056105511541";
constant PM_Inst_RAM_Word5_INIT_39 : bit_vector(0 to 255) := x"2D6C2D7D2D8E2D9F1D190D081F1D0F0CE010E0012477246624552E4224BB24AA";
constant PM_Inst_RAM_Word5_INIT_3A : bit_vector(0 to 255) := x"2D8E2D9F1CB11CA11C911C81940883602FF12FE018BD940E2D242D352D462D57";
constant PM_Inst_RAM_Word5_INIT_3B : bit_vector(0 to 255) := x"2EFB2EEA2ED92EC82FB52FA42F932F8218BD940E2D242D352D462D572D6C2D7D";
constant PM_Inst_RAM_Word5_INIT_3C : bit_vector(0 to 255) := x"1C6194082E7D2E6C1CF90CE81EFD0EEC2CF12EE8E081F68904F104E104D114C1";
constant PM_Inst_RAM_Word5_INIT_3D : bit_vector(0 to 255) := x"0DEE2DFD2DECC01808D918C82ED92EC809B109A197012D882D992DAA2DBB1C71";
constant PM_Inst_RAM_Word5_INIT_3E : bit_vector(0 to 255) := x"E030E0202D932D822F752F659550FD4727555C49C0015D40F410304A81401DFF";
constant PM_Inst_RAM_Word5_INIT_3F : bit_vector(0 to 255) := x"91DF91CFBFCDBE0FBFDE94F8B60F96A0F729047F146E08F108E194081821940E";
-- BRAM 0 in address space [0x00003000:0x000037FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word6 LOC = RAMB16_X0Y5;
constant PM_Inst_RAM_Word6_INIT_00 : bit_vector(0 to 255) := x"902F903F904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F";
constant PM_Inst_RAM_Word6_INIT_01 : bit_vector(0 to 255) := x"1760940E950895092F642DE081F0900191FC91EDF441053115212FB92FA89508";
constant PM_Inst_RAM_Word6_INIT_02 : bit_vector(0 to 255) := x"F441053115212F172F062EF52EE42FD92FC893DF93CF931F930F92FF92EF9508";
constant PM_Inst_RAM_Word6_INIT_03 : bit_vector(0 to 255) := x"E060E050E24DC010FF77F4C90531302AC01E95092F642DE081F0900181F981E8";
constant PM_Inst_RAM_Word6_INIT_04 : bit_vector(0 to 255) := x"2F712F9D2F8C1D111D011CF11CE194E094F0950095101821940EE030E020E070";
constant PM_Inst_RAM_Word6_INIT_05 : bit_vector(0 to 255) := x"2F08931F930F950890EF90FF910F911F91CF91DF1760940EE02A2D4E2D5F2F60";
constant PM_Inst_RAM_Word6_INIT_06 : bit_vector(0 to 255) := x"E020E070E060E050E04A2F912F801821940EE030E020E070E060E050E04D2F19";
constant PM_Inst_RAM_Word6_INIT_07 : bit_vector(0 to 255) := x"2F352F242F192F08931F930F92FF92EF92DF92CF9508910F911F1821940EE030";
constant PM_Inst_RAM_Word6_INIT_08 : bit_vector(0 to 255) := x"910F911F185D940E2F912F801811940E2D4C2D5D2D6E2D7F24FF24EE24DD2EC6";
constant PM_Inst_RAM_Word6_INIT_09 : bit_vector(0 to 255) := x"911F185D940E2F912F801757940E2F192F08931F930F950890CF90DF90EF90FF";
constant PM_Inst_RAM_Word6_INIT_0A : bit_vector(0 to 255) := x"1F551F441F330F221FF51FE41FB30FA2C004FF6027AA27BB27EE27FF9508910F";
constant PM_Inst_RAM_Word6_INIT_0B : bit_vector(0 to 255) := x"1BAA2E1AE2A195082F6A2F7B2F8E2F9FF77107769700F7899567957795879596";
constant PM_Inst_RAM_Word6_INIT_0C : bit_vector(0 to 255) := x"0BE40BB31BA2F02007F507E407B317A21FFF1FEE1FBB1FAAC00D2FFB2FEA1BBB";
constant PM_Inst_RAM_Word6_INIT_0D : bit_vector(0 to 255) := x"2F6A2F592F482F372F269590958095709560F769941A1F991F881F771F660BF5";
constant PM_Inst_RAM_Word6_INIT_0E : bit_vector(0 to 255) := x"95409550F4381C00D00ADFD2D004FD57D00E26052E09FB9795082F9F2F8E2F7B";
constant PM_Inst_RAM_Word6_INIT_0F : bit_vector(0 to 255) := x"0FEE95084F9F4F8F4F7F9561957095809590F7F695084F5F4F4F4F3F95219530";
constant PM_Inst_RAM_Word6_INIT_10 : bit_vector(0 to 255) := x"6944205241542073692073696854CFFF94F89508920F95C8920F963195C81FFF";
constant PM_Inst_RAM_Word6_INIT_11 : bit_vector(0 to 255) := x"50554B43414200656369766564207265746E756F63206C616E6769732065646F";
constant PM_Inst_RAM_Word6_INIT_12 : bit_vector(0 to 255) := x"632065746972570030005458542E50554B4341422064656E65704F005458542E";
constant PM_Inst_RAM_Word6_INIT_13 : bit_vector(0 to 255) := x"552D3770557265746E756F6320657469725700306E442D376E447265746E756F";
constant PM_Inst_RAM_Word6_INIT_14 : bit_vector(0 to 255) := x"63695420657469725700306E442D376E4472656B636954206574697257003070";
constant PM_Inst_RAM_Word6_INIT_15 : bit_vector(0 to 255) := x"1516C90000000017310AB20AC100000000FFFFFFFF003070552D37705572656B";
constant PM_Inst_RAM_Word6_INIT_16 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000173117";
constant PM_Inst_RAM_Word6_INIT_17 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_18 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_19 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_20 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_21 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_22 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_23 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_24 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_25 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_26 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_27 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_28 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_29 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_30 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_31 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_32 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_33 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_34 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_35 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_36 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_37 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_38 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_39 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
-- BRAM 0 in address space [0x00003800:0x00003FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word7 LOC = RAMB16_X0Y6;
constant PM_Inst_RAM_Word7_INIT_00 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_01 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_02 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_03 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_04 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_05 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_06 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_07 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_08 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_09 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_10 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_11 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_12 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_13 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_14 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_15 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_16 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_17 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_18 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_19 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_20 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_21 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_22 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_23 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_24 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_25 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_26 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_27 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_28 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_29 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_30 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_31 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_32 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_33 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_34 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_35 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_36 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_37 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_38 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_39 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
end prog_mem_init_pkg;

29
src/AVR8/Peripheral/SynchronizerCompPack.vhd Normal file
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@ -0,0 +1,29 @@
--************************************************************************************************
-- Component declaration for the synchronizer
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 10.08.2003
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package SynchronizerCompPack is
-- Transparent D latch
component SynchronizerLatch is port(
D : in std_logic;
G : in std_logic;
Q : out std_logic;
QN : out std_logic);
end component;
-- Falling edge triggered flip-flop
component SynchronizerDFF is port(
NRST : in std_logic;
CLK : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
end SynchronizerCompPack;

32
src/AVR8/Peripheral/SynchronizerDFF.vhd Normal file
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@ -0,0 +1,32 @@
--**********************************************************************************************
-- Falling edge triggered flip-flop for the synchronizer
-- Version 0.1
-- Modified 30.07.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity SynchronizerDFF is port(
NRST : in std_logic;
CLK : in std_logic;
D : in std_logic;
Q : out std_logic);
end SynchronizerDFF;
architecture RTL of SynchronizerDFF is
begin
DFF:process(CLK,NRST)
begin
if (NRST='0') then -- Reset
Q <= '0';
elsif (CLK='0' and CLK'event) then -- Clock (falling edge)
Q <= D;
end if;
end process;
end RTL;

32
src/AVR8/Peripheral/SynchronizerLatch.vhd Normal file
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@ -0,0 +1,32 @@
--**********************************************************************************************
-- Transparent latch(used in the synchronizer instead of the first DFF)
-- Version 0.2
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity SynchronizerLatch is port(
D : in std_logic;
G : in std_logic;
Q : out std_logic;
QN : out std_logic);
end SynchronizerLatch;
architecture RTL of SynchronizerLatch is
signal Q_Tmp : std_logic;
begin
TransparentLatch:process(G,D)
begin
if G='1' then -- Latch is transparent
Q_Tmp <= D;
end if;
end process;
Q <= Q_Tmp;
QN <= not Q_Tmp;
end RTL;

969
src/AVR8/Peripheral/Timer_Counter.vhd Normal file
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@ -0,0 +1,969 @@
--**********************************************************************************************
-- Timers/Counters Block Peripheral for the AVR Core
-- Version 1.37? (Special version for the JTAG OCD)
-- Modified 11.06.2004
-- Synchronizer for EXT1/EXT2 inputs was added
-- Designed by Ruslan Lepetenok
-- Note : Only T/C0 and T/C2 are implemented
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end Timer_Counter;
architecture RTL of Timer_Counter is
-- Copies of the external signals
signal OC0_PWM0_Int : std_logic;
signal OC2_PWM2_Int : std_logic;
-- Registers
signal TCCR0 : std_logic_vector(7 downto 0);
signal TCCR1A : std_logic_vector(7 downto 0);
signal TCCR1B : std_logic_vector(7 downto 0);
signal TCCR2 : std_logic_vector(7 downto 0);
signal ASSR : std_logic_vector(7 downto 0); -- Asynchronous status register (for TCNT0)
signal TIMSK : std_logic_vector(7 downto 0);
signal TIFR : std_logic_vector(7 downto 0);
signal TCNT0 : std_logic_vector(7 downto 0);
signal TCNT2 : std_logic_vector(7 downto 0);
signal OCR0 : std_logic_vector(7 downto 0);
signal OCR2 : std_logic_vector(7 downto 0);
signal TCNT1H : std_logic_vector(7 downto 0);
signal TCNT1L : std_logic_vector(7 downto 0);
signal OCR1AH : std_logic_vector(7 downto 0);
signal OCR1AL : std_logic_vector(7 downto 0);
signal OCR1BH : std_logic_vector(7 downto 0);
signal OCR1BL : std_logic_vector(7 downto 0);
signal ICR1AH : std_logic_vector(7 downto 0);
signal ICR1AL : std_logic_vector(7 downto 0);
-- TCCR0 Bits
alias CS00 : std_logic is TCCR0(0);
alias CS01 : std_logic is TCCR0(1);
alias CS02 : std_logic is TCCR0(2);
alias CTC0 : std_logic is TCCR0(3);
alias COM00 : std_logic is TCCR0(4);
alias COM01 : std_logic is TCCR0(5);
alias PWM0 : std_logic is TCCR0(6);
-- TCCR1A Bits
alias PWM10 : std_logic is TCCR1A(0);
alias PWM11 : std_logic is TCCR1A(1);
alias COM1B0 : std_logic is TCCR1A(4);
alias COM1B1 : std_logic is TCCR1A(5);
alias COM1A0 : std_logic is TCCR1A(4);
alias COM1A1 : std_logic is TCCR1A(5);
-- TCCR1B Bits
alias CS10 : std_logic is TCCR1A(0);
alias CS11 : std_logic is TCCR1A(1);
alias CS12 : std_logic is TCCR1A(2);
alias CTC1 : std_logic is TCCR1A(3);
alias ICES1 : std_logic is TCCR1A(6);
alias ICNC1 : std_logic is TCCR1A(7);
-- TCCR2 Bits
alias CS20 : std_logic is TCCR2(0);
alias CS21 : std_logic is TCCR2(1);
alias CS22 : std_logic is TCCR2(2);
alias CTC2 : std_logic is TCCR2(3);
alias COM20 : std_logic is TCCR2(4);
alias COM21 : std_logic is TCCR2(5);
alias PWM2 : std_logic is TCCR2(6);
-- ASSR bits
alias TCR0UB : std_logic is ASSR(0);
alias OCR0UB : std_logic is ASSR(1);
alias TCN0UB : std_logic is ASSR(2);
alias AS0 : std_logic is ASSR(3);
-- TIMSK bits
alias TOIE0 : std_logic is TIMSK(0);
alias OCIE0 : std_logic is TIMSK(1);
alias TOIE1 : std_logic is TIMSK(2);
alias OCIE1B : std_logic is TIMSK(3);
alias OCIE1A : std_logic is TIMSK(4);
alias TICIE1 : std_logic is TIMSK(5);
alias TOIE2 : std_logic is TIMSK(6);
alias OCIE2 : std_logic is TIMSK(7);
-- TIFR bits
alias TOV0 : std_logic is TIFR(0);
alias OCF0 : std_logic is TIFR(1);
alias TOV1 : std_logic is TIFR(2);
alias OCF1B : std_logic is TIFR(3);
alias OCF1A : std_logic is TIFR(4);
alias ICF1 : std_logic is TIFR(5);
alias TOV2 : std_logic is TIFR(6);
alias OCF2 : std_logic is TIFR(7);
-- Prescaler1 signals
signal CK8 : std_logic;
signal CK64 : std_logic;
signal CK256 : std_logic;
signal CK1024 : std_logic;
signal Pre1Cnt : std_logic_vector(9 downto 0); -- Prescaler 1 counter (10-bit)
signal EXT1RE : std_logic; -- Rising edge of external input EXT1 (for TCNT1 only)
signal EXT1FE : std_logic; -- Falling edge of external input EXT1 (for TCNT1 only)
signal EXT2RE : std_logic; -- Rising edge of external input EXT2 (for TCNT2 only)
signal EXT2FE : std_logic; -- Falling edge of external input EXT2 (for TCNT2 only)
-- Risign/falling edge detectors
signal EXT1Latched : std_logic;
signal EXT2Latched : std_logic;
-- Prescalers outputs
signal TCNT0_En : std_logic; -- Output of the prescaler 0
signal TCNT1_En : std_logic; -- Output of the prescaler 1
signal TCNT2_En : std_logic; -- Output of the prescaler 1
-- Prescaler0 signals
signal PCK08 : std_logic;
signal PCK032 : std_logic;
signal PCK064 : std_logic;
signal PCK0128 : std_logic;
signal PCK0256 : std_logic;
signal PCK01024 : std_logic;
signal Pre0Cnt : std_logic_vector(9 downto 0); -- Prescaler 0 counter (10-bit)
-- Synchronizer signals
signal EXT1SA : std_logic;
signal EXT1SB : std_logic; -- Output of the synchronizer for EXT1
signal EXT2SA : std_logic;
signal EXT2SB : std_logic; -- Output of the synchronizer for EXT1
-- Temporary registers
signal OCR0_Tmp : std_logic_vector(OCR0'range);
signal OCR2_Tmp : std_logic_vector(OCR2'range);
-- Counters control(Inc/Dec)
signal Cnt0Dir : std_logic;
signal Cnt2Dir : std_logic;
--
signal TCNT0WrFl : std_logic;
signal TCNT0CmpBl : std_logic;
signal TCNT2WrFl : std_logic;
signal TCNT2CmpBl : std_logic;
begin
-- Synchronizers
SyncDFFs:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
EXT1SA <= '0';
EXT1SB <= '0';
EXT2SA <= '0';
EXT2SB <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
EXT1SA <= EXT1;
EXT1SB <= EXT1SA;
EXT2SA <= EXT2;
EXT2SB <= EXT2SA;
end if;
end if;
end process;
-- -------------------------------------------------------------------------------------------
-- Prescalers
-- -------------------------------------------------------------------------------------------
-- Prescaler 1 for TCNT1 and TCNT2
Prescaler_1:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Pre1Cnt <= (others => '0');
CK8 <= '0';
CK64 <= '0';
CK256 <= '0';
CK1024 <= '0';
EXT1RE <= '0';
EXT1FE <= '0';
EXT2RE <= '0';
EXT2FE <= '0';
EXT1Latched <= '0';
EXT2Latched <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
Pre1Cnt <= Pre1Cnt+1;
CK8 <= not CK8 and(Pre1Cnt(0) and Pre1Cnt(1)and Pre1Cnt(2));
CK64 <= not CK64 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5));
CK256 <= not CK256 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7));
CK1024 <= not CK1024 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7) and Pre1Cnt(8) and Pre1Cnt(9));
EXT1RE <= not EXT1RE and (EXT1SB and not EXT1Latched);
EXT1FE <= not EXT1FE and (not EXT1SB and EXT1Latched);
EXT2RE <= not EXT2RE and (EXT2SB and not EXT2Latched);
EXT2FE <= not EXT2FE and (not EXT2SB and EXT2Latched);
EXT1Latched <= EXT1SB;
EXT2Latched <= EXT2SB;
end if;
end if;
end process;
TCNT1_En <= (not CS12 and not CS11 and CS10) or -- CK "001"
(CK8 and not CS12 and CS11 and not CS10) or -- CK/8 "010"
(CK64 and not CS12 and CS11 and CS10) or -- CK/64 "011"
(CK256 and CS12 and not CS11 and not CS10) or -- CK/256 "100"
(CK1024 and CS12 and not CS11 and CS10) or -- CK/1024 "101"
(EXT1FE and CS12 and CS11 and not CS10) or -- Falling edge "110"
(EXT1RE and CS12 and CS11 and CS10); -- Rising edge "111"
TCNT2_En <= (not CS22 and not CS21 and CS20) or -- CK "001"
(CK8 and not CS22 and CS21 and not CS20) or -- CK/8 "010"
(CK64 and not CS22 and CS21 and CS20) or -- CK/64 "011"
(CK256 and CS22 and not CS21 and not CS20) or -- CK/256 "100"
(CK1024 and CS22 and not CS21 and CS20) or -- CK/1024 "101"
(EXT2FE and CS22 and CS21 and not CS20) or -- Falling edge "110"
(EXT2RE and CS22 and CS21 and CS20); -- Rising edge "111"
Prescaler_0_Cnt:process(cp2,ireset)
begin
if(ireset='0') then -- Reset
Pre0Cnt <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
Pre0Cnt <= Pre0Cnt+1;
end if;
end if;
end process;
Prescaler_0:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
PCK08 <= '0';
PCK032 <= '0';
PCK064 <= '0';
PCK0128 <= '0';
PCK0256 <= '0';
PCK01024 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
PCK08 <= (not PCK08 and(Pre0Cnt(0) and Pre0Cnt(1)and Pre0Cnt(2)));
PCK032 <= (not PCK032 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4)));
PCK064 <= (not PCK064 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5)));
PCK0128 <= (not PCK0128 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6)));
PCK0256 <= (not PCK0256 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7)));
PCK01024 <= (not PCK01024 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7) and Pre0Cnt(8) and Pre0Cnt(9)));
end if;
end if;
end process;
TCNT0_En <= (not CS02 and not CS01 and CS00) or -- PCK "001"
(PCK08 and not CS02 and CS01 and not CS00) or -- PCK/8 "010"
(PCK032 and not CS02 and CS01 and CS00)or -- PCK/32 "011"
(PCK064 and CS02 and not CS01 and not CS00)or -- PCK/64 "100"
(PCK0128 and CS02 and not CS01 and CS00)or -- PCK/64 "101"
(PCK0256 and CS02 and CS01 and not CS00)or -- PCK/256 "110"
(PCK01024 and CS02 and CS01 and CS00); -- PCK/1024 "111"
-- -------------------------------------------------------------------------------------------
-- End of prescalers
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 0
-- -------------------------------------------------------------------------------------------
TimerCounter0Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT0_Address and iowe='1' and cp2en='1') then -- Write to TCNT0
TCNT0 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM0 is
when '0' => -- Non-PWM mode
if(CTC0='1' and TCNT0=OCR0) then -- Clear T/C on compare match
TCNT0 <= (others => '0');
elsif(TCNT0_En='1') then
TCNT0 <= TCNT0 + 1; -- Increment TCNT0
end if;
when '1' => -- PWM mode
if(TCNT0_En='1') then
case Cnt0Dir is
when '0' => -- Counts up
if(TCNT0=x"FF") then
TCNT0<=x"FE";
else
TCNT0 <= TCNT0 + 1; -- Increment TCNT0 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT0=x"00") then
TCNT0 <= x"01";
else
TCNT0 <= TCNT0 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt0DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt0Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
if (PWM0='1') then
case Cnt0Dir is
when '0' =>
if(TCNT0=x"FF") then
Cnt0Dir <= '1';
end if;
when '1' =>
if(TCNT0=x"00") then
Cnt0Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt0OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC0_PWM0_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
case PWM0 is
when '0' => -- Non PWM Mode
if(TCNT0=OCR0 and TCNT0CmpBl='0') then
if(COM01='0' and COM00='1') then -- Toggle
OC0_PWM0_Int <= not OC0_PWM0_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR0(5 downto 4) is -- -> COM01&COM00
when "10" => -- Non-inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '0'; -- Clear
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '1'; -- Set
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '0'; -- Clear
else -- Down-counting
OC0_PWM0_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '1'; -- Set
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '0'; -- Clear
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '1'; -- Set
else -- Down-counting
OC0_PWM0_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC0_PWM0 <= OC0_PWM0_Int;
TCnt0_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV0 <= '0';
OCF0 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV0 <= dbus_in(0); -- !!!
end if;
else
case TOV0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (PWM0='0') then -- Non PWM Mode
if (TCNT0=x"FF") then
TOV0 <= '1';
end if;
else -- PWM Mode
if(TCNT0=x"00") then
TOV0 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC0OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(0)='1')) and cp2en='1') then -- Clear TOV0 flag
TOV0 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF0 <= dbus_in(1); -- !!!
end if;
else
case OCF0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (TCNT0=OCR0 and TCNT0CmpBl='0') then
OCF0 <= '1';
end if;
end if;
when '1' =>
if((TC0CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(1)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF0 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR0(7) <= '0';
TCCR0_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR0(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR0_Address and iowe='1') then
TCCR0(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR0_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM0 is
when '0' => -- Non-PWM mode
if (adr=OCR0_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR0 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT0=x"FF" and tmr_cp2en='1' and TCNT0_En='1') then -- Load data from the temporary register
OCR0 <= OCR0_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR0_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR0_Address and iowe='1') then -- Load data from the data bus
OCR0_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT0WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT0WrFl is
when '0' =>
if (adr=TCNT0_Address and iowe='1' and TCNT0_En='0') then -- Load data from the data bus
TCNT0WrFl <= '1';
end if;
when '1' =>
if(TCNT0_En='0') then
TCNT0WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF0 and Toggling) disabled for TCNT0
TCNT0CmpBl <= '1' when (TCNT0WrFl='1' or (adr=TCNT0_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 2
-- -------------------------------------------------------------------------------------------
TimerCounter2Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT2_Address and iowe='1' and cp2en='1') then -- Write to TCNT2
TCNT2 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM2 is
when '0' => -- Non-PWM mode
if(CTC2='1' and TCNT2=OCR2) then -- Clear T/C on compare match
TCNT2 <= (others => '0');
elsif(TCNT2_En='1') then
TCNT2 <= TCNT2 + 1; -- Increment TCNT2
end if;
when '1' => -- PWM mode
if(TCNT2_En='1') then
case Cnt2Dir is
when '0' => -- Counts up
if(TCNT2=x"FF") then
TCNT2 <= x"FE";
else
TCNT2 <= TCNT2 + 1; -- Increment TCNT2 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT2=x"00") then
TCNT2 <= x"01";
else
TCNT2 <= TCNT2 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt2DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt2Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
if (PWM2='1') then
case Cnt2Dir is
when '0' =>
if(TCNT2=x"FF") then
Cnt2Dir <= '1';
end if;
when '1' =>
if(TCNT2=x"00") then
Cnt2Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt2OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC2_PWM2_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
case PWM2 is
when '0' => -- Non PWM Mode
if(TCNT2=OCR2 and TCNT2CmpBl='0') then
if(COM21='0' and COM20='1') then -- Toggle
OC2_PWM2_Int <= not OC2_PWM2_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR2(5 downto 4) is -- -> COM21&COM20
when "10" => -- Non-inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '0'; -- Clear
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '1'; -- Set
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '0'; -- Clear
else -- Down-counting
OC2_PWM2_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '1'; -- Set
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '0'; -- Clear
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '1'; -- Set
else -- Down-counting
OC2_PWM2_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC2_PWM2 <= OC2_PWM2_Int;
TCnt2_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV2 <= '0';
OCF2 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV2 <= dbus_in(6); -- !!!
end if;
else
case TOV2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (PWM2='0') then -- Non PWM Mode
if (TCNT2=x"FF") then
TOV2 <= '1';
end if;
else -- PWM Mode
if(TCNT2=x"00") then
TOV2 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC2OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(6)='1')) and cp2en='1') then -- Clear TOV2 flag
TOV2 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF2 <= dbus_in(7); -- !!!
end if;
else
case OCF2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (TCNT2=OCR2 and TCNT2CmpBl='0') then
OCF2 <= '1';
end if;
end if;
when '1' =>
if((TC2CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(7)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF2 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR2(7) <= '0';
TCCR2_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR2(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR2_Address and iowe='1') then
TCCR2(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR2_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM2 is
when '0' => -- Non-PWM mode
if (adr=OCR2_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR2 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT2=x"FF" and tmr_cp2en='1' and TCNT2_En='1') then -- Load data from the temporary register
OCR2 <= OCR2_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR2_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR2_Address and iowe='1') then -- Load data from the data bus
OCR2_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT2WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT2WrFl is
when '0' =>
if (adr=TCNT2_Address and iowe='1' and TCNT2_En='0') then -- Load data from the data bus
TCNT2WrFl <= '1';
end if;
when '1' =>
if(TCNT2_En='0') then
TCNT2WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF2 and Toggling) disabled for TCNT2
TCNT2CmpBl <= '1' when (TCNT2WrFl='1' or (adr=TCNT2_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
TIMSK_Bits:process(cp2,ireset)
begin
if (ireset='0') then
TIMSK <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock Enable
if (adr=TIMSK_Address and iowe='1') then
TIMSK <= dbus_in;
end if;
end if;
end if;
end process;
-- Interrupt flags of Timer/Counter0
TC0OvfIRQ <= TOV0 and TOIE0; -- Interrupt on overflow of TCNT0
TC0CmpIRQ <= OCF0 and OCIE0; -- Interrupt on compare match of TCNT0
-- Interrupt flags of Timer/Counter0
TC2OvfIRQ <= TOV2 and TOIE2; -- Interrupt on overflow of TCNT2
TC2CmpIRQ <= OCF2 and OCIE2; -- Interrupt on compare match of TCNT2
-- Unused interrupt requests(for T/C1)
TC1OvfIRQ <= TOV1 and TOIE1;
TC1CmpAIRQ <= OCF1A and OCIE1A;
TC1CmpBIRQ <= OCF1B and OCIE1B;
TC1ICIRQ <= ICF1 and TICIE1;
-- Unused TIFR flags(for T/C1)
TOV1 <= '0';
OCF1A <= '0';
OCF1B <= '0';
ICF1 <= '0';
-- -------------------------------------------------------------------------------------------
-- End of common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Bus interface
-- -------------------------------------------------------------------------------------------
out_en <= '1' when ((adr=TCCR0_Address or
adr=TCCR1A_Address or
adr=TCCR1B_Address or
adr=TCCR2_Address or
adr=ASSR_Address or
adr=TIMSK_Address or
adr=TIFR_Address or
adr=TCNT0_Address or
adr=TCNT2_Address or
adr=OCR0_Address or
adr=OCR2_Address or
adr=TCNT1H_Address or
adr=TCNT1L_Address or
adr=OCR1AH_Address or
adr=OCR1AL_Address or
adr=OCR1BH_Address or
adr=OCR1BL_Address or
adr=ICR1AH_Address or
adr=ICR1AL_Address) and iore='1') else '0';
-- Output multilexer
--Output_Mux:process(adr,TCCR0,OCR0,OCR0_Tmp,TCNT0,TCCR2,OCR2,OCR2_Tmp,TCNT2,TIFR,TIMSK) -- Combinatorial
--begin
-- case adr is
-- when TCCR0_Address => dbus_out <= TCCR0;
-- when OCR0_Address =>
-- if (PWM0='0') then
-- dbus_out <= OCR0;
-- else
-- dbus_out <= OCR0_Tmp;
-- end if;
-- when TCNT0_Address => dbus_out <= TCNT0;
-- when TCCR2_Address => dbus_out <= TCCR2;
-- when OCR2_Address =>
-- if (PWM2='0') then
-- dbus_out <= OCR2;
-- else
-- dbus_out <= OCR2_Tmp;
-- end if;
-- when TCNT2_Address => dbus_out <= TCNT2;
-- when TIFR_Address => dbus_out <= TIFR;
-- when TIMSK_Address => dbus_out <= TIMSK;
-- when others => dbus_out <= (others => '0');
-- end case;
--end process;
PWM0bit <= PWM0;
PWM10bit <= PWM10;
PWM11bit <= PWM11;
PWM2bit <= PWM2;
-- Synopsys version
dbus_out <= TCCR0 when (adr=TCCR0_Address) else
OCR0 when (adr=OCR0_Address and PWM0='0') else -- Non PWM mode of T/C0
OCR0_Tmp when (adr=OCR0_Address and PWM0='1') else -- PWM mode of T/C0
TCNT0 when (adr=TCNT0_Address) else
TCCR2 when (adr=TCCR2_Address) else
OCR2 when (adr=OCR2_Address and PWM2='0') else -- Non PWM mode of T/C2
OCR2_Tmp when (adr=OCR2_Address and PWM2='1') else -- PWM mode of T/C2
TCNT2 when (adr=TCNT2_Address) else
TIFR when (adr=TIFR_Address) else
TIMSK when (adr=TIMSK_Address) else
(others => '0');
-- -------------------------------------------------------------------------------------------
-- End of bus interface
-- -------------------------------------------------------------------------------------------
end RTL;

969
src/AVR8/Peripheral/Timer_Counter_old.vhd Normal file
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@ -0,0 +1,969 @@
--**********************************************************************************************
-- Timers/Counters Block Peripheral for the AVR Core
-- Version 1.37? (Special version for the JTAG OCD)
-- Modified 11.06.2004
-- Synchronizer for EXT1/EXT2 inputs was added
-- Designed by Ruslan Lepetenok
-- Note : Only T/C0 and T/C2 are implemented
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end Timer_Counter;
architecture RTL of Timer_Counter is
-- Copies of the external signals
signal OC0_PWM0_Int : std_logic;
signal OC2_PWM2_Int : std_logic;
-- Registers
signal TCCR0 : std_logic_vector(7 downto 0);
signal TCCR1A : std_logic_vector(7 downto 0);
signal TCCR1B : std_logic_vector(7 downto 0);
signal TCCR2 : std_logic_vector(7 downto 0);
signal ASSR : std_logic_vector(7 downto 0); -- Asynchronous status register (for TCNT0)
signal TIMSK : std_logic_vector(7 downto 0);
signal TIFR : std_logic_vector(7 downto 0);
signal TCNT0 : std_logic_vector(7 downto 0);
signal TCNT2 : std_logic_vector(7 downto 0);
signal OCR0 : std_logic_vector(7 downto 0);
signal OCR2 : std_logic_vector(7 downto 0);
signal TCNT1H : std_logic_vector(7 downto 0);
signal TCNT1L : std_logic_vector(7 downto 0);
signal OCR1AH : std_logic_vector(7 downto 0);
signal OCR1AL : std_logic_vector(7 downto 0);
signal OCR1BH : std_logic_vector(7 downto 0);
signal OCR1BL : std_logic_vector(7 downto 0);
signal ICR1AH : std_logic_vector(7 downto 0);
signal ICR1AL : std_logic_vector(7 downto 0);
-- TCCR0 Bits
alias CS00 : std_logic is TCCR0(0);
alias CS01 : std_logic is TCCR0(1);
alias CS02 : std_logic is TCCR0(2);
alias CTC0 : std_logic is TCCR0(3);
alias COM00 : std_logic is TCCR0(4);
alias COM01 : std_logic is TCCR0(5);
alias PWM0 : std_logic is TCCR0(6);
-- TCCR1A Bits
alias PWM10 : std_logic is TCCR1A(0);
alias PWM11 : std_logic is TCCR1A(1);
alias COM1B0 : std_logic is TCCR1A(4);
alias COM1B1 : std_logic is TCCR1A(5);
alias COM1A0 : std_logic is TCCR1A(4);
alias COM1A1 : std_logic is TCCR1A(5);
-- TCCR1B Bits
alias CS10 : std_logic is TCCR1A(0);
alias CS11 : std_logic is TCCR1A(1);
alias CS12 : std_logic is TCCR1A(2);
alias CTC1 : std_logic is TCCR1A(3);
alias ICES1 : std_logic is TCCR1A(6);
alias ICNC1 : std_logic is TCCR1A(7);
-- TCCR2 Bits
alias CS20 : std_logic is TCCR2(0);
alias CS21 : std_logic is TCCR2(1);
alias CS22 : std_logic is TCCR2(2);
alias CTC2 : std_logic is TCCR2(3);
alias COM20 : std_logic is TCCR2(4);
alias COM21 : std_logic is TCCR2(5);
alias PWM2 : std_logic is TCCR2(6);
-- ASSR bits
alias TCR0UB : std_logic is ASSR(0);
alias OCR0UB : std_logic is ASSR(1);
alias TCN0UB : std_logic is ASSR(2);
alias AS0 : std_logic is ASSR(3);
-- TIMSK bits
alias TOIE0 : std_logic is TIMSK(0);
alias OCIE0 : std_logic is TIMSK(1);
alias TOIE1 : std_logic is TIMSK(2);
alias OCIE1B : std_logic is TIMSK(3);
alias OCIE1A : std_logic is TIMSK(4);
alias TICIE1 : std_logic is TIMSK(5);
alias TOIE2 : std_logic is TIMSK(6);
alias OCIE2 : std_logic is TIMSK(7);
-- TIFR bits
alias TOV0 : std_logic is TIFR(0);
alias OCF0 : std_logic is TIFR(1);
alias TOV1 : std_logic is TIFR(2);
alias OCF1B : std_logic is TIFR(3);
alias OCF1A : std_logic is TIFR(4);
alias ICF1 : std_logic is TIFR(5);
alias TOV2 : std_logic is TIFR(6);
alias OCF2 : std_logic is TIFR(7);
-- Prescaler1 signals
signal CK8 : std_logic;
signal CK64 : std_logic;
signal CK256 : std_logic;
signal CK1024 : std_logic;
signal Pre1Cnt : std_logic_vector(9 downto 0); -- Prescaler 1 counter (10-bit)
signal EXT1RE : std_logic; -- Rising edge of external input EXT1 (for TCNT1 only)
signal EXT1FE : std_logic; -- Falling edge of external input EXT1 (for TCNT1 only)
signal EXT2RE : std_logic; -- Rising edge of external input EXT2 (for TCNT2 only)
signal EXT2FE : std_logic; -- Falling edge of external input EXT2 (for TCNT2 only)
-- Risign/falling edge detectors
signal EXT1Latched : std_logic;
signal EXT2Latched : std_logic;
-- Prescalers outputs
signal TCNT0_En : std_logic; -- Output of the prescaler 0
signal TCNT1_En : std_logic; -- Output of the prescaler 1
signal TCNT2_En : std_logic; -- Output of the prescaler 1
-- Prescaler0 signals
signal PCK08 : std_logic;
signal PCK032 : std_logic;
signal PCK064 : std_logic;
signal PCK0128 : std_logic;
signal PCK0256 : std_logic;
signal PCK01024 : std_logic;
signal Pre0Cnt : std_logic_vector(9 downto 0); -- Prescaler 0 counter (10-bit)
-- Synchronizer signals
signal EXT1SA : std_logic;
signal EXT1SB : std_logic; -- Output of the synchronizer for EXT1
signal EXT2SA : std_logic;
signal EXT2SB : std_logic; -- Output of the synchronizer for EXT1
-- Temporary registers
signal OCR0_Tmp : std_logic_vector(OCR0'range);
signal OCR2_Tmp : std_logic_vector(OCR2'range);
-- Counters control(Inc/Dec)
signal Cnt0Dir : std_logic;
signal Cnt2Dir : std_logic;
--
signal TCNT0WrFl : std_logic;
signal TCNT0CmpBl : std_logic;
signal TCNT2WrFl : std_logic;
signal TCNT2CmpBl : std_logic;
begin
-- Synchronizers
SyncDFFs:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
EXT1SA <= '0';
EXT1SB <= '0';
EXT2SA <= '0';
EXT2SB <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
EXT1SA <= EXT1;
EXT1SB <= EXT1SA;
EXT2SA <= EXT2;
EXT2SB <= EXT2SA;
end if;
end if;
end process;
-- -------------------------------------------------------------------------------------------
-- Prescalers
-- -------------------------------------------------------------------------------------------
-- Prescaler 1 for TCNT1 and TCNT2
Prescaler_1:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Pre1Cnt <= (others => '0');
CK8 <= '0';
CK64 <= '0';
CK256 <= '0';
CK1024 <= '0';
EXT1RE <= '0';
EXT1FE <= '0';
EXT2RE <= '0';
EXT2FE <= '0';
EXT1Latched <= '0';
EXT2Latched <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
Pre1Cnt <= Pre1Cnt+1;
CK8 <= not CK8 and(Pre1Cnt(0) and Pre1Cnt(1)and Pre1Cnt(2));
CK64 <= not CK64 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5));
CK256 <= not CK256 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7));
CK1024 <= not CK1024 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7) and Pre1Cnt(8) and Pre1Cnt(9));
EXT1RE <= not EXT1RE and (EXT1SB and not EXT1Latched);
EXT1FE <= not EXT1FE and (not EXT1SB and EXT1Latched);
EXT2RE <= not EXT2RE and (EXT2SB and not EXT2Latched);
EXT2FE <= not EXT2FE and (not EXT2SB and EXT2Latched);
EXT1Latched <= EXT1SB;
EXT2Latched <= EXT2SB;
end if;
end if;
end process;
TCNT1_En <= (not CS12 and not CS11 and CS10) or -- CK "001"
(CK8 and not CS12 and CS11 and not CS10) or -- CK/8 "010"
(CK64 and not CS12 and CS11 and CS10) or -- CK/64 "011"
(CK256 and CS12 and not CS11 and not CS10) or -- CK/256 "100"
(CK1024 and CS12 and not CS11 and CS10) or -- CK/1024 "101"
(EXT1FE and CS12 and CS11 and not CS10) or -- Falling edge "110"
(EXT1RE and CS12 and CS11 and CS10); -- Rising edge "111"
TCNT2_En <= (not CS22 and not CS21 and CS20) or -- CK "001"
(CK8 and not CS22 and CS21 and not CS20) or -- CK/8 "010"
(CK64 and not CS22 and CS21 and CS20) or -- CK/64 "011"
(CK256 and CS22 and not CS21 and not CS20) or -- CK/256 "100"
(CK1024 and CS22 and not CS21 and CS20) or -- CK/1024 "101"
(EXT2FE and CS22 and CS21 and not CS20) or -- Falling edge "110"
(EXT2RE and CS22 and CS21 and CS20); -- Rising edge "111"
Prescaler_0_Cnt:process(cp2,ireset)
begin
if(ireset='0') then -- Reset
Pre0Cnt <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable(Note 2)
Pre0Cnt <= Pre0Cnt+1;
end if;
end if;
end process;
Prescaler_0:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
PCK08 <= '0';
PCK032 <= '0';
PCK064 <= '0';
PCK0128 <= '0';
PCK0256 <= '0';
PCK01024 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (tmr_cp2en='1') then -- Clock Enable
PCK08 <= (not PCK08 and(Pre0Cnt(0) and Pre0Cnt(1)and Pre0Cnt(2)));
PCK032 <= (not PCK032 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4)));
PCK064 <= (not PCK064 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5)));
PCK0128 <= (not PCK0128 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6)));
PCK0256 <= (not PCK0256 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7)));
PCK01024 <= (not PCK01024 and(Pre0Cnt(0) and Pre0Cnt(1) and Pre0Cnt(2) and Pre0Cnt(3) and Pre0Cnt(4) and Pre0Cnt(5) and Pre0Cnt(6) and Pre0Cnt(7) and Pre0Cnt(8) and Pre0Cnt(9)));
end if;
end if;
end process;
TCNT0_En <= (not CS02 and not CS01 and CS00) or -- PCK "001"
(PCK08 and not CS02 and CS01 and not CS00) or -- PCK/8 "010"
(PCK032 and not CS02 and CS01 and CS00)or -- PCK/32 "011"
(PCK064 and CS02 and not CS01 and not CS00)or -- PCK/64 "100"
(PCK0128 and CS02 and not CS01 and CS00)or -- PCK/64 "101"
(PCK0256 and CS02 and CS01 and not CS00)or -- PCK/256 "110"
(PCK01024 and CS02 and CS01 and CS00); -- PCK/1024 "111"
-- -------------------------------------------------------------------------------------------
-- End of prescalers
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 0
-- -------------------------------------------------------------------------------------------
TimerCounter0Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT0_Address and iowe='1' and cp2en='1') then -- Write to TCNT0
TCNT0 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM0 is
when '0' => -- Non-PWM mode
if(CTC0='1' and TCNT0=OCR0) then -- Clear T/C on compare match
TCNT0 <= (others => '0');
elsif(TCNT0_En='1') then
TCNT0 <= TCNT0 + 1; -- Increment TCNT0
end if;
when '1' => -- PWM mode
if(TCNT0_En='1') then
case Cnt0Dir is
when '0' => -- Counts up
if(TCNT0=x"FF") then
TCNT0<=x"FE";
else
TCNT0 <= TCNT0 + 1; -- Increment TCNT0 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT0=x"00") then
TCNT0 <= x"01";
else
TCNT0 <= TCNT0 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt0DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt0Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
if (PWM0='1') then
case Cnt0Dir is
when '0' =>
if(TCNT0=x"FF") then
Cnt0Dir <= '1';
end if;
when '1' =>
if(TCNT0=x"00") then
Cnt0Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt0OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC0_PWM0_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT0_En='1') then
case PWM0 is
when '0' => -- Non PWM Mode
if(TCNT0=OCR0 and TCNT0CmpBl='0') then
if(COM01='0' and COM00='1') then -- Toggle
OC0_PWM0_Int <= not OC0_PWM0_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR0(5 downto 4) is -- -> COM01&COM00
when "10" => -- Non-inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '0'; -- Clear
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '1'; -- Set
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '0'; -- Clear
else -- Down-counting
OC0_PWM0_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT0=x"FF") then -- Update OCR0
if (OCR0_Tmp=x"00") then
OC0_PWM0_Int <= '1'; -- Set
elsif (OCR0_Tmp=x"FF") then
OC0_PWM0_Int <= '0'; -- Clear
end if;
elsif(TCNT0=OCR0 and OCR0/=x"00") then
if(Cnt0Dir='0') then -- Up-counting
OC0_PWM0_Int <= '1'; -- Set
else -- Down-counting
OC0_PWM0_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC0_PWM0 <= OC0_PWM0_Int;
TCnt0_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV0 <= '0';
OCF0 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV0 <= dbus_in(0); -- !!!
end if;
else
case TOV0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (PWM0='0') then -- Non PWM Mode
if (TCNT0=x"FF") then
TOV0 <= '1';
end if;
else -- PWM Mode
if(TCNT0=x"00") then
TOV0 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC0OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(0)='1')) and cp2en='1') then -- Clear TOV0 flag
TOV0 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF0
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF0 <= dbus_in(1); -- !!!
end if;
else
case OCF0 is
when '0' =>
if (tmr_cp2en='1' and TCNT0_En='1') then
if (TCNT0=OCR0 and TCNT0CmpBl='0') then
OCF0 <= '1';
end if;
end if;
when '1' =>
if((TC0CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(1)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF0 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR0(7) <= '0';
TCCR0_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR0(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR0_Address and iowe='1') then
TCCR0(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR0_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM0 is
when '0' => -- Non-PWM mode
if (adr=OCR0_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR0 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT0=x"FF" and tmr_cp2en='1' and TCNT0_En='1') then -- Load data from the temporary register
OCR0 <= OCR0_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR0_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR0_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR0_Address and iowe='1') then -- Load data from the data bus
OCR0_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT0WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT0WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT0WrFl is
when '0' =>
if (adr=TCNT0_Address and iowe='1' and TCNT0_En='0') then -- Load data from the data bus
TCNT0WrFl <= '1';
end if;
when '1' =>
if(TCNT0_En='0') then
TCNT0WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF0 and Toggling) disabled for TCNT0
TCNT0CmpBl <= '1' when (TCNT0WrFl='1' or (adr=TCNT0_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Timer/Counter 2
-- -------------------------------------------------------------------------------------------
TimerCounter2Cnt:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(adr=TCNT2_Address and iowe='1' and cp2en='1') then -- Write to TCNT2
TCNT2 <= dbus_in;
elsif(tmr_cp2en='1') then
case PWM2 is
when '0' => -- Non-PWM mode
if(CTC2='1' and TCNT2=OCR2) then -- Clear T/C on compare match
TCNT2 <= (others => '0');
elsif(TCNT2_En='1') then
TCNT2 <= TCNT2 + 1; -- Increment TCNT2
end if;
when '1' => -- PWM mode
if(TCNT2_En='1') then
case Cnt2Dir is
when '0' => -- Counts up
if(TCNT2=x"FF") then
TCNT2 <= x"FE";
else
TCNT2 <= TCNT2 + 1; -- Increment TCNT2 (0 to FF)
end if;
when '1' => -- Counts down
if(TCNT2=x"00") then
TCNT2 <= x"01";
else
TCNT2 <= TCNT2 - 1; -- Decrement TCNT0 (FF to 0)
end if;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
Cnt2DirectionControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Cnt2Dir <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
if (PWM2='1') then
case Cnt2Dir is
when '0' =>
if(TCNT2=x"FF") then
Cnt2Dir <= '1';
end if;
when '1' =>
if(TCNT2=x"00") then
Cnt2Dir <= '0';
end if;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
TCnt2OutputControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC2_PWM2_Int <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if(tmr_cp2en='1') then -- Clock enable
if(TCNT2_En='1') then
case PWM2 is
when '0' => -- Non PWM Mode
if(TCNT2=OCR2 and TCNT2CmpBl='0') then
if(COM21='0' and COM20='1') then -- Toggle
OC2_PWM2_Int <= not OC2_PWM2_Int;
end if;
end if;
when '1' => -- PWM Mode
case TCCR2(5 downto 4) is -- -> COM21&COM20
when "10" => -- Non-inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '0'; -- Clear
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '1'; -- Set
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '0'; -- Clear
else -- Down-counting
OC2_PWM2_Int <= '1'; -- Set
end if;
end if;
when "11" => -- Inverted PWM
if(TCNT2=x"FF") then -- Update OCR2
if (OCR2_Tmp=x"00") then
OC2_PWM2_Int <= '1'; -- Set
elsif (OCR2_Tmp=x"FF") then
OC2_PWM2_Int <= '0'; -- Clear
end if;
elsif(TCNT2=OCR2 and OCR2/=x"00") then
if(Cnt2Dir='0') then -- Up-counting
OC2_PWM2_Int <= '1'; -- Set
else -- Down-counting
OC2_PWM2_Int <= '0'; -- Clear
end if;
end if;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end process;
OC2_PWM2 <= OC2_PWM2_Int;
TCnt2_TIFR_Bits:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TOV2 <= '0';
OCF2 <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
-- TOV2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
TOV2 <= dbus_in(6); -- !!!
end if;
else
case TOV2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (PWM2='0') then -- Non PWM Mode
if (TCNT2=x"FF") then
TOV2 <= '1';
end if;
else -- PWM Mode
if(TCNT2=x"00") then
TOV2 <= '1';
end if;
end if;
end if;
when '1' =>
if((TC2OvfIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(6)='1')) and cp2en='1') then -- Clear TOV2 flag
TOV2 <= '0';
end if;
when others => null;
end case;
end if;
-- OCF2
if(stopped_mode='1' and tmr_running='0' and cp2en='1') then -- !!!Special mode!!!
if(adr=TIFR_Address and iowe='1') then
OCF2 <= dbus_in(7); -- !!!
end if;
else
case OCF2 is
when '0' =>
if (tmr_cp2en='1' and TCNT2_En='1') then
if (TCNT2=OCR2 and TCNT2CmpBl='0') then
OCF2 <= '1';
end if;
end if;
when '1' =>
if((TC2CmpIRQ_Ack='1' or (adr=TIFR_Address and iowe='1' and dbus_in(7)='1')) and cp2en='1') then -- Clear OCF2 flag
OCF2 <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
TCCR2(7) <= '0';
TCCR2_Reg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCCR2(6 downto 0) <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then -- Clock Enable
if (adr=TCCR2_Address and iowe='1') then
TCCR2(6 downto 0) <= dbus_in(6 downto 0);
end if;
end if;
end if;
end process;
OCR2_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2 <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
case PWM2 is
when '0' => -- Non-PWM mode
if (adr=OCR2_Address and iowe='1' and cp2en='1') then -- Load data from the data bus
OCR2 <= dbus_in;
end if;
when '1' => -- PWM mode
if(TCNT2=x"FF" and tmr_cp2en='1' and TCNT2_En='1') then -- Load data from the temporary register
OCR2 <= OCR2_Tmp;
end if;
when others => null;
end case;
end if;
end process;
OCR2_Tmp_Write:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OCR2_Tmp <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
if (adr=OCR2_Address and iowe='1') then -- Load data from the data bus
OCR2_Tmp <= dbus_in;
end if;
end if;
end if;
end process;
--
TCNT2WriteControl:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TCNT2WrFl <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (cp2en='1') then
case TCNT2WrFl is
when '0' =>
if (adr=TCNT2_Address and iowe='1' and TCNT2_En='0') then -- Load data from the data bus
TCNT2WrFl <= '1';
end if;
when '1' =>
if(TCNT2_En='0') then
TCNT2WrFl <= '0';
end if;
when others => null;
end case;
end if;
end if;
end process;
-- Operations on compare match(OCF2 and Toggling) disabled for TCNT2
TCNT2CmpBl <= '1' when (TCNT2WrFl='1' or (adr=TCNT2_Address and iowe='1')) else
'0';
-- -------------------------------------------------------------------------------------------
-- Common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
TIMSK_Bits:process(cp2,ireset)
begin
if (ireset='0') then
TIMSK <= (others => '0');
elsif (cp2='1' and cp2'event) then
if (cp2en='1') then -- Clock Enable
if (adr=TIMSK_Address and iowe='1') then
TIMSK <= dbus_in;
end if;
end if;
end if;
end process;
-- Interrupt flags of Timer/Counter0
TC0OvfIRQ <= TOV0 and TOIE0; -- Interrupt on overflow of TCNT0
TC0CmpIRQ <= OCF0 and OCIE0; -- Interrupt on compare match of TCNT0
-- Interrupt flags of Timer/Counter0
TC2OvfIRQ <= TOV2 and TOIE2; -- Interrupt on overflow of TCNT2
TC2CmpIRQ <= OCF2 and OCIE2; -- Interrupt on compare match of TCNT2
-- Unused interrupt requests(for T/C1)
TC1OvfIRQ <= TOV1 and TOIE1;
TC1CmpAIRQ <= OCF1A and OCIE1A;
TC1CmpBIRQ <= OCF1B and OCIE1B;
TC1ICIRQ <= ICF1 and TICIE1;
-- Unused TIFR flags(for T/C1)
TOV1 <= '0';
OCF1A <= '0';
OCF1B <= '0';
ICF1 <= '0';
-- -------------------------------------------------------------------------------------------
-- End of common (Control/Interrupt) bits
-- -------------------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Bus interface
-- -------------------------------------------------------------------------------------------
out_en <= '1' when ((adr=TCCR0_Address or
adr=TCCR1A_Address or
adr=TCCR1B_Address or
adr=TCCR2_Address or
adr=ASSR_Address or
adr=TIMSK_Address or
adr=TIFR_Address or
adr=TCNT0_Address or
adr=TCNT2_Address or
adr=OCR0_Address or
adr=OCR2_Address or
adr=TCNT1H_Address or
adr=TCNT1L_Address or
adr=OCR1AH_Address or
adr=OCR1AL_Address or
adr=OCR1BH_Address or
adr=OCR1BL_Address or
adr=ICR1AH_Address or
adr=ICR1AL_Address) and iore='1') else '0';
-- Output multilexer
--Output_Mux:process(adr,TCCR0,OCR0,OCR0_Tmp,TCNT0,TCCR2,OCR2,OCR2_Tmp,TCNT2,TIFR,TIMSK) -- Combinatorial
--begin
-- case adr is
-- when TCCR0_Address => dbus_out <= TCCR0;
-- when OCR0_Address =>
-- if (PWM0='0') then
-- dbus_out <= OCR0;
-- else
-- dbus_out <= OCR0_Tmp;
-- end if;
-- when TCNT0_Address => dbus_out <= TCNT0;
-- when TCCR2_Address => dbus_out <= TCCR2;
-- when OCR2_Address =>
-- if (PWM2='0') then
-- dbus_out <= OCR2;
-- else
-- dbus_out <= OCR2_Tmp;
-- end if;
-- when TCNT2_Address => dbus_out <= TCNT2;
-- when TIFR_Address => dbus_out <= TIFR;
-- when TIMSK_Address => dbus_out <= TIMSK;
-- when others => dbus_out <= (others => '0');
-- end case;
--end process;
PWM0bit <= PWM0;
PWM10bit <= PWM10;
PWM11bit <= PWM11;
PWM2bit <= PWM2;
-- Synopsys version
dbus_out <= TCCR0 when (adr=TCCR0_Address) else
OCR0 when (adr=OCR0_Address and PWM0='0') else -- Non PWM mode of T/C0
OCR0_Tmp when (adr=OCR0_Address and PWM0='1') else -- PWM mode of T/C0
TCNT0 when (adr=TCNT0_Address) else
TCCR2 when (adr=TCCR2_Address) else
OCR2 when (adr=OCR2_Address and PWM2='0') else -- Non PWM mode of T/C2
OCR2_Tmp when (adr=OCR2_Address and PWM2='1') else -- PWM mode of T/C2
TCNT2 when (adr=TCNT2_Address) else
TIFR when (adr=TIFR_Address) else
TIMSK when (adr=TIMSK_Address) else
(others => '0');
-- -------------------------------------------------------------------------------------------
-- End of bus interface
-- -------------------------------------------------------------------------------------------
end RTL;

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--**********************************************************************************************
-- Parallel Port Peripheral for the AVR Core
-- Version 0.7
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok.
--
-- The possibility of implementing level sensitive LATCH instead of edge sensitive DFF
-- (for the first stage of the synchronizer) is added.
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.SynchronizerCompPack.all; -- Component declarations for the synchronizers
entity pport is generic(PPortNum : natural);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- --Info
-- miso_LOC : in integer;
-- spi_spe : in std_logic;
-- External connection
-- spi_misoi : out std_logic;
portx : out std_logic_vector(7 downto 0);
ddrx : out std_logic_vector(7 downto 0);
pinx : in std_logic_vector(7 downto 0);
irqlines : out std_logic_vector(7 downto 0));
end pport;
architecture RTL of pport is
signal PORTx_Int : std_logic_vector(portx'range);
signal DDRx_Int : std_logic_vector(ddrx'range);
signal PINx_Tmp : std_logic_vector(pinx'range);
signal PINx_Resync : std_logic_vector(pinx'range);
signal PORTx_Sel : std_logic;
signal DDRx_Sel : std_logic;
signal PINx_Sel : std_logic;
begin
PORTx_Sel <= '1' when adr=PPortAdrArray(PPortNum).Port_Adr else '0';
DDRx_Sel <= '1' when adr=PPortAdrArray(PPortNum).DDR_Adr else '0';
PINx_Sel <= '1' when adr=PPortAdrArray(PPortNum).Pin_Adr else '0';
--spi_misoi_Sel <= '1' when adr=PPortAdrArray(PPortNum).Pin_Adr else '0';
out_en <= (PORTx_Sel or DDRx_Sel or PINx_Sel) and iore;
PORTx_DFF:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
PORTx_Int <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if PORTx_Sel='1' and iowe='1' then -- Clock enable
PORTx_Int <= dbus_in;
end if;
end if;
end process;
DDRx_DFF:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
DDRx_Int <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if DDRx_Sel='1' and iowe='1' then -- Clock enable
DDRx_Int <= dbus_in;
end if;
end if;
end process;
-- The first stage of the resynchronizer : DFF or Latch
SynchDFF:if not CSynchLatchUsed generate
PINxDFFSynchronizer:for i in pinx'range generate
PINxDFFSynchronizer_Inst:component SynchronizerDFF port map(
NRST => ireset,
CLK => cp2,
D => pinx(i),
Q => PINx_Tmp(i));
end generate;
end generate;
SynchLatch:if CSynchLatchUsed generate
PINxLatchSynchronizer:for i in pinx'range generate
PINxLatchSynchronizer_Inst:component SynchronizerLatch port map(
D => pinx(i),
G => cp2,
Q => PINx_Tmp(i),
QN => open);
end generate;
end generate;
-- End of the first stage of the resynchronizer
PINXInputReg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
PINx_Resync <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
PINx_Resync <= PINx_Tmp;
end if;
end process;
DBusOutMux:for i in pinx'range generate
dbus_out(i) <= (PORTx_Int(i) and PORTx_Sel)or(DDRx_Int(i) and DDRx_Sel)or(PINx_Resync(i) and PINx_Sel);
irqlines(i) <= PINx_Resync(i);
--spi_misoi <= pinx(i) when miso_Loc = i and spi_spe = '1';
end generate;
-- Outputs
portx <= PORTx_Int;
ddrx <= DDRx_Int;
end RTL;

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--**********************************************************************************************
-- Quick and Dirty peripheral to connect pins for PWM etc to external pins
-- Version 1.5 "Original" (Mega103) version
-- Modified 14.06.20010
-- MOdified by Jack Gassett
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity swap_pins is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
-- External connection
OC0_PWM0_Loc : out integer;
OC1A_PWM1A_Loc : out integer;
OC1B_PWM1B_Loc : out integer;
OC2_PWM2_Loc : out integer;
mosi_Loc : out integer;
miso_Loc : out integer;
sck_Loc : out integer;
spi_cs_n_Loc : out integer
);
end swap_pins;
architecture RTL of swap_pins is
--PWM signals
signal OC0_PWM0_Int : std_logic_vector(7 downto 0);
signal OC0_PWM0_En : std_logic;
signal OC1A_PWM1A_Int : std_logic_vector(7 downto 0);
signal OC1A_PWM1A_En : std_logic;
signal OC1B_PWM1B_Int : std_logic_vector(7 downto 0);
signal OC1B_PWM1B_En : std_logic;
signal OC2_PWM2_Int : std_logic_vector(7 downto 0);
signal OC2_PWM2_En : std_logic;
signal mosi_Int : std_logic_vector(7 downto 0);
signal mosi_En : std_logic;
signal miso_Int : std_logic_vector(7 downto 0);
signal miso_En : std_logic;
signal sck_Int : std_logic_vector(7 downto 0);
signal sck_En : std_logic;
signal spi_cs_n_Int : std_logic_vector(7 downto 0);
signal spi_cs_n_En : std_logic;
begin
OC0_PWM0_En <= '1' when (adr=x"1000" and iowe='1') else '0'; -- Hijacks unused external SRAM space
OC1A_PWM1A_En <= '1' when (adr=x"1001" and iowe='1') else '0'; -- Hijacks unused external SRAM space
OC1B_PWM1B_En <= '1' when (adr=x"1002" and iowe='1') else '0'; -- Hijacks unused external SRAM space
OC2_PWM2_En <= '1' when (adr=x"1003" and iowe='1') else '0'; -- Hijacks unused external SRAM space
mosi_En <= '1' when (adr=x"1004" and iowe='1') else '0'; -- Hijacks unused external SRAM space
miso_En <= '1' when (adr=x"1005" and iowe='1') else '0'; -- Hijacks unused external SRAM space
sck_En <= '1' when (adr=x"1006" and iowe='1') else '0'; -- Hijacks unused external SRAM space
spi_cs_n_En <= '1' when (adr=x"1007" and iowe='1') else '0'; -- Hijacks unused external SRAM space
process(cp2,ireset)
begin
if (ireset='0') then -- Reset
OC0_PWM0_Int <= (others => '0');
OC1A_PWM1A_Int <= (others => '0');
OC1B_PWM1B_Int <= (others => '0');
OC2_PWM2_Int <= (others => '0');
mosi_Int <= (others => '0');
miso_Int <= (others => '0');
sck_Int <= (others => '0');
spi_cs_n_Int <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if OC0_PWM0_En='1' and iowe='1' then -- Clock enable
OC0_PWM0_Int <= dbus_in;
elsif OC1A_PWM1A_En='1' and iowe='1' then -- Clock enable
OC1A_PWM1A_Int <= dbus_in;
elsif OC1B_PWM1B_En='1' and iowe='1' then -- Clock enable
OC1B_PWM1B_Int <= dbus_in;
elsif OC2_PWM2_En='1' and iowe='1' then -- Clock enable
OC2_PWM2_Int <= dbus_in;
elsif mosi_En='1' and iowe='1' then -- Clock enable
mosi_Int <= dbus_in;
elsif miso_En='1' and iowe='1' then -- Clock enable
miso_Int <= dbus_in;
elsif sck_En='1' and iowe='1' then -- Clock enable
sck_Int <= dbus_in;
elsif spi_cs_n_En='1' and iowe='1' then -- Clock enable
spi_cs_n_Int <= dbus_in;
end if;
end if;
end process;
OC0_PWM0_Loc <= conv_integer(OC0_PWM0_Int);
OC1A_PWM1A_Loc <= conv_integer(OC1A_PWM1A_Int);
OC1B_PWM1B_Loc <= conv_integer(OC1B_PWM1B_Int);
OC2_PWM2_Loc <= conv_integer(OC2_PWM2_Int);
mosi_Loc <= conv_integer(mosi_Int);
miso_Loc <= conv_integer(miso_Int);
sck_Loc <= conv_integer(sck_Int);
spi_cs_n_Loc <= conv_integer(spi_cs_n_Int);
end RTL;

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--**********************************************************************************************
-- UART Peripheral for the AVR Core
-- Version 1.5 "Original" (Mega103) version
-- Modified 14.06.2006
-- Designed by Ruslan Lepetenok
-- UDRE bug found
-- Transmitter bug (for 9 bit transmission) was found
-- Bug in UART_RcDel_St state machine was fixed
-- Bug in UART_RcDel_St state machine was fixed(2) (!!!simulation only!!!)
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity uart is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External connection
rxd : in std_logic;
rx_en : out std_logic;
txd : out std_logic;
tx_en : out std_logic;
-- IRQ
txcirq : out std_logic;
txc_irqack : in std_logic;
udreirq : out std_logic;
rxcirq : out std_logic
);
end uart;
architecture RTL of uart is
signal UDR_Tx : std_logic_vector(7 downto 0);
signal UDR_Rx : std_logic_vector(7 downto 0);
signal UBRR : std_logic_vector(7 downto 0);
-- USR Bits
signal USR : std_logic_vector(7 downto 0);
signal USR_Wr_En : std_logic;
alias RXC : std_logic is USR(7);
alias TXC : std_logic is USR(6);
alias UDRE : std_logic is USR(5);
alias FE : std_logic is USR(4);
alias DOR : std_logic is USR(3); -- OR in Atmel documents
-- UCR Bits
signal UCR : std_logic_vector(7 downto 0);
signal UCR_Wr_En : std_logic;
alias RXCIE : std_logic is UCR(7);
alias TXCIE : std_logic is UCR(6);
alias UDRIE : std_logic is UCR(5);
alias RXEN : std_logic is UCR(4);
alias TXEN : std_logic is UCR(3);
alias CHR9 : std_logic is UCR(2);
alias RXB8 : std_logic is UCR(1);
alias TXB8 : std_logic is UCR(0);
signal CHR9_Latched : std_logic;
signal TXB8_Latched : std_logic;
-- Common internal signals
signal UART_Clk_En : std_logic;
-- Internal signals for transmitter
signal SR_Tx : std_logic_vector (7 downto 0); -- UART transmit shift register
signal SR_Tx_In : std_logic_vector (7 downto 0);
signal Tx_In : std_logic;
-- Transmitter state machine
signal nUART_Tr_St0 : std_logic;
signal UART_Tr_St1 : std_logic;
signal UART_Tr_St2 : std_logic;
signal UART_Tr_St3 : std_logic;
signal UART_Tr_St4 : std_logic;
signal UART_Tr_St5 : std_logic;
signal UART_Tr_St6 : std_logic;
signal UART_Tr_St7 : std_logic;
signal UART_Tr_St8 : std_logic;
signal UART_Tr_St9 : std_logic;
signal UART_Tr_St10 : std_logic;
signal UART_Tr_St11 : std_logic;
signal Flag_A : std_logic;
signal Flag_B : std_logic;
signal UDR_Wr_En : std_logic;
signal UDR_Rd : std_logic;
signal USR_Rd : std_logic;
signal UCR_Rd : std_logic;
signal UBRR_Rd : std_logic;
-- Frequence divider signals
signal Div16_Cnt : std_logic_vector (3 downto 0);
signal Div16_In : std_logic_vector (Div16_Cnt'range); -- Counter Input
signal Div16_Eq : std_logic; -- Combinatorial output of the comparator
-- Baud generator signals
signal UBRR_Wr_En : std_logic;
signal Baud_Gen_Cnt : std_logic_vector (7 downto 0); -- Counter
signal Baud_Gen_In : std_logic_vector (Baud_Gen_Cnt'range); -- Counter Input
signal Baud_Gen_Eq : std_logic; -- Combinatorial output of the comparator
signal Baud_Gen_Out : std_logic;
-- Receiver signals
signal nUART_RcDel_St0 : std_logic;
signal UART_RcDel_St1 : std_logic;
signal UART_RcDel_St2 : std_logic;
signal UART_RcDel_St3 : std_logic;
signal UART_RcDel_St4 : std_logic;
signal UART_RcDel_St5 : std_logic;
signal UART_RcDel_St6 : std_logic;
signal UART_RcDel_St7 : std_logic;
signal UART_RcDel_St8 : std_logic;
signal UART_RcDel_St9 : std_logic;
signal UART_RcDel_St10 : std_logic;
signal UART_RcDel_St11 : std_logic;
signal UART_RcDel_St12 : std_logic;
signal UART_RcDel_St13 : std_logic;
signal UART_RcDel_St14 : std_logic;
signal UART_RcDel_St15 : std_logic;
signal UART_RcDel_St16 : std_logic;
signal nUART_Rc_St0 : std_logic;
signal UART_Rc_St1 : std_logic;
signal UART_Rc_St2 : std_logic;
signal UART_Rc_St3 : std_logic;
signal UART_Rc_St4 : std_logic;
signal UART_Rc_St5 : std_logic;
signal UART_Rc_St6 : std_logic;
signal UART_Rc_St7 : std_logic;
signal UART_Rc_St8 : std_logic;
signal UART_Rc_St9 : std_logic;
signal UART_Rc_St10 : std_logic;
signal RXD_ResyncA : std_logic;
signal RXD_ResyncB : std_logic;
signal Detector_Out : std_logic;
signal Detector_A : std_logic;
signal Detector_B : std_logic;
signal UART_Rc_SR : std_logic_vector(9 downto 0);
signal UART_Rc_SR7_In : std_logic;
signal UART_Rc_Delay : std_logic;
begin
-- Baud generator (First divider)
Baud_Generator :process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Baud_Gen_Cnt <= (others => '0');
Baud_Gen_Out <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
Baud_Gen_Cnt <= Baud_Gen_In;
Baud_Gen_Out <= Baud_Gen_Eq;
end if;
end process;
Baud_Gen_Eq <= '1' when UBRR=Baud_Gen_Cnt else '0';
Baud_Gen_In <= Baud_Gen_Cnt+1 when Baud_Gen_Eq='0' else (others=>'0');
--Divide by 16 (Second divider)
Divide_By_16:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Div16_Cnt <= (others => '0');
-- UART_Clk_En <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if Baud_Gen_Out='1' then -- Clock enable
Div16_Cnt <= Div16_In;
-- UART_Clk_En <= Div16_Eq;
end if;
end if;
end process;
Div16_Eq <= '1' when Div16_Cnt="1111" else '0';
Div16_In <= Div16_Cnt+1 when Div16_Eq='0' else (others=>'0');
Global_Clock_Enable:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
UART_Clk_En <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
UART_Clk_En <= Div16_Eq and Baud_Gen_Out;
end if;
end process;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- UBRR
UBRR_Wr_En <= '1' when (adr=UBRR_Address and iowe='1') else '0'; -- UBRR write enable
UBRR_Load:process(cp2,ireset)
begin
if ireset='0' then -- Reset
UBRR <= ( others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if UBRR_Wr_En='1' then -- Clock enable
UBRR <= dbus_in;
end if;
end if;
end process;
UDR_Rd <= '1' when (adr=UDR_Address and iore='1') else '0'; -- UDR read enable
-- UDR for transmitter
UDR_Wr_En <= '1' when (adr=UDR_Address and iowe='1' and TXEN ='1') else '0'; -- UDR write enable
UDR_Tx_Load:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
UDR_Tx <= ( others => '0');
CHR9_Latched <= '0';
TXB8_Latched <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (UDR_Wr_En and (Flag_A or nUART_Tr_St0))='1' then -- Clock enable
UDR_Tx <= dbus_in;
CHR9_Latched <= CHR9;
TXB8_Latched <= TXB8;
end if;
end if;
end process;
-- Load flags
Load_Flags:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
Flag_A <= '0';
Flag_B <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
Flag_A <= (not Flag_A and UDR_Wr_En and not nUART_Tr_St0)or
(Flag_A and not (UART_Tr_St1 and UART_Clk_En));
Flag_B <= (not Flag_B and (UDR_Wr_En and (Flag_A or (nUART_Tr_St0 and not(UART_Tr_St11 and UART_Clk_En)))))or
(Flag_B and not (UART_Clk_En and UART_Tr_St11));
end if;
end process;
Transmitter_Shifter:for i in 6 downto 0 generate
SR_Tx_In(i) <= (dbus_in(i) and UDR_Wr_En and((not Flag_A and not nUART_Tr_St0)or(not Flag_B and UART_Tr_St11 and UART_Clk_En)))or -- Direct load from data bus
(UDR_Tx(i) and UART_Tr_St11 and Flag_B)or -- Load from UDR(TX)
(SR_Tx(i+1) and nUART_Tr_St0 and not UART_Tr_St11); -- Shift
end generate;
SR_Tx_In(7) <= (dbus_in(7) and UDR_Wr_En and((not Flag_A and not nUART_Tr_St0)or(not Flag_B and UART_Tr_St11 and UART_Clk_En)))or -- Direct load from data bus
(UDR_Tx(7) and UART_Tr_St11 and Flag_B)or -- Load from UDR(TX)
(TXB8_Latched and (UART_Tr_St2 and CHR9_Latched))or -- Shift first
('1' and not((not Flag_A and not nUART_Tr_St0 and UDR_Wr_En)or UART_Tr_St11 or(UART_Tr_St2 and CHR9_Latched))); -- All other cases
TX_In <= ('0' and UART_Tr_St1)or -- Start bit
(SR_Tx(0) and (nUART_Tr_St0 and not UART_Tr_St1))or -- Shift
('1' and not nUART_Tr_St0); -- Idle
-- Transmitter shift register
SR_Tx_Load_Sift:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
SR_Tx <= ( others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if ((not Flag_A and not nUART_Tr_St0 and UDR_Wr_En)or(UART_Tr_St11 and UART_Clk_En)or (nUART_Tr_St0 and UART_Clk_En and not UART_Tr_St1))='1' then -- Clock enable
SR_Tx <= SR_Tx_In;
end if;
end if;
end process;
-- Transmitter output register
Tx_Out:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
txd <= '1';
elsif (cp2='1' and cp2'event) then -- Clock
if (UART_Clk_En and (nUART_Tr_St0 or Flag_A))='1' then -- Clock enable
txd <= TX_In;
end if;
end if;
end process;
Transmit_State_Machine:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
nUART_Tr_St0 <='0';
UART_Tr_St1 <='0';
UART_Tr_St2 <='0';
UART_Tr_St3 <='0';
UART_Tr_St4 <='0';
UART_Tr_St5 <='0';
UART_Tr_St6 <='0';
UART_Tr_St7 <='0';
UART_Tr_St8 <='0';
UART_Tr_St9 <='0';
UART_Tr_St10 <='0';
UART_Tr_St11 <='0';
elsif (cp2='1' and cp2'event) then -- Clock
if (UART_Clk_En = '1') then -- Clock enable
nUART_Tr_St0 <= (not nUART_Tr_St0 and Flag_A) or (nUART_Tr_St0 and not(UART_Tr_St11 and not Flag_B and not UDR_Wr_En));
UART_Tr_St1 <= not UART_Tr_St1 and ((not nUART_Tr_St0 and Flag_A)or(UART_Tr_St11 and (Flag_B or UDR_Wr_En))); -- Start bit
UART_Tr_St2 <= UART_Tr_St1; -- Bit 0
UART_Tr_St3 <= UART_Tr_St2; -- Bit 1
UART_Tr_St4 <= UART_Tr_St3; -- Bit 2
UART_Tr_St5 <= UART_Tr_St4; -- Bit 3
UART_Tr_St6 <= UART_Tr_St5; -- Bit 4
UART_Tr_St7 <= UART_Tr_St6; -- Bit 5
UART_Tr_St8 <= UART_Tr_St7; -- Bit 6
UART_Tr_St9 <= UART_Tr_St8; -- Bit 7
UART_Tr_St10 <= UART_Tr_St9 and CHR9_Latched; -- Bit 8 (if enabled)
UART_Tr_St11 <= (UART_Tr_St9 and not CHR9_Latched) or UART_Tr_St10; -- Stop bit
end if;
end if;
end process;
-- USR bits
USR_UDRE:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
UDRE <= '1'; -- !!
elsif (cp2='1' and cp2'event) then -- Clock
UDRE <= (UDRE and not(UDR_Wr_En and (Flag_A or (nUART_Tr_St0 and not(UART_Tr_St11 and UART_Clk_En))))) or (not UDRE and (UART_Tr_St11 and Flag_B and UART_Clk_En));
end if;
end process;
USR_Wr_En <= '1' when (adr=USR_Address and iowe='1') else '0';
USR_TXC:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
TXC <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
TXC <= (not TXC and(UART_Tr_St11 and not Flag_B and UART_Clk_En and not UDR_Wr_En))or -- TXC set ???
(TXC and not(UDR_Wr_En or txc_irqack or (USR_Wr_En and dbus_in(6)))); -- TXC reset
end if;
end process;
-- Transmitter IRQ
txcirq <= TXC and TXCIE;
udreirq <= UDRE and UDRIE;
-- Output enable signal(for external multiplexer control)
out_en <= '1' when ((adr=UDR_Address or adr=UBRR_Address or adr=USR_Address or adr=UCR_Address) and
iore='1') else '0';
UCR_Wr_En <= '1' when (adr=UCR_Address and iowe='1') else '0';
UCR_Bits:process(cp2,ireset)
begin
if ireset='0' then -- Reset
UCR(7 downto 2) <= (others => '0');
UCR(0) <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if UCR_Wr_En='1' then -- Clock enable
UCR(7 downto 2) <= dbus_in(7 downto 2);
UCR(0) <= dbus_in(0);
end if;
end if;
end process;
--*********************************** Receiver **************************************
Receiver:process(cp2,ireset)
begin
if ireset='0' then -- Reset
nUART_RcDel_St0 <='0';
UART_RcDel_St1 <='0';
UART_RcDel_St2 <='0';
UART_RcDel_St3 <='0';
UART_RcDel_St4 <='0';
UART_RcDel_St5 <='0';
UART_RcDel_St6 <='0';
UART_RcDel_St7 <='0';
UART_RcDel_St8 <='0';
UART_RcDel_St9 <='0';
UART_RcDel_St10 <='0';
UART_RcDel_St11 <='0';
UART_RcDel_St12 <='0';
UART_RcDel_St13 <='0';
UART_RcDel_St14 <='0';
UART_RcDel_St15 <='0';
UART_RcDel_St16 <='0';
elsif (cp2='1' and cp2'event) then -- Clock
if Baud_Gen_Out='1' then -- Clock enable
nUART_RcDel_St0 <=
(not nUART_RcDel_St0 and not RXD_ResyncB)or
-- Was :(nUART_RcDel_St0 and not((UART_RcDel_St10 and(Detector_Out and not nUART_Rc_St0))or -- Noise instead of start bit
(nUART_RcDel_St0 and not((UART_RcDel_St9 and(Detector_Out and not nUART_Rc_St0))or -- Noise instead of start bit
(UART_RcDel_St9 and UART_Rc_St10)or -- Stop bit was detected
(UART_RcDel_St16 and not nUART_Rc_St0))); -- ?bug?
UART_RcDel_St1 <=
not UART_RcDel_St1 and((not nUART_RcDel_St0 and not RXD_ResyncB)or(UART_RcDel_St16 and nUART_Rc_St0));
UART_RcDel_St2 <= UART_RcDel_St1;
UART_RcDel_St3 <= UART_RcDel_St2;
UART_RcDel_St4 <= UART_RcDel_St3;
UART_RcDel_St5 <= UART_RcDel_St4;
UART_RcDel_St6 <= UART_RcDel_St5;
UART_RcDel_St7 <= UART_RcDel_St6;
UART_RcDel_St8 <= UART_RcDel_St7;
UART_RcDel_St9 <= UART_RcDel_St8;
UART_RcDel_St10 <= not UART_RcDel_St10 and UART_RcDel_St9 and
((not Detector_Out and not nUART_Rc_St0)or(nUART_Rc_St0 and not UART_Rc_St10));
UART_RcDel_St11 <= UART_RcDel_St10;
UART_RcDel_St12 <= UART_RcDel_St11;
UART_RcDel_St13 <= UART_RcDel_St12;
UART_RcDel_St14 <= UART_RcDel_St13;
UART_RcDel_St15 <= UART_RcDel_St14;
UART_RcDel_St16 <= UART_RcDel_St15;
end if;
end if;
end process;
UART_Rc_SR7_In <= UART_Rc_SR(8) when CHR9='1' else UART_Rc_SR(9);
Receiver_Shift:process(cp2,ireset)
begin
if ireset='0' then -- Reset
nUART_Rc_St0 <='0';
UART_Rc_St1 <='0';
UART_Rc_St2 <='0';
UART_Rc_St3 <='0';
UART_Rc_St4 <='0';
UART_Rc_St5 <='0';
UART_Rc_St6 <='0';
UART_Rc_St7 <='0';
UART_Rc_St8 <='0';
UART_Rc_St9 <='0';
UART_Rc_St10 <='0';
UART_Rc_SR <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if (Baud_Gen_Out and UART_RcDel_St9)='1' then -- Clock enable
nUART_Rc_St0 <= (not nUART_Rc_St0 and not RXD_ResyncB)or
(nUART_Rc_St0 and not UART_Rc_St10);
UART_Rc_St1 <= not UART_Rc_St1 and (not nUART_Rc_St0 and not RXD_ResyncB); -- D0
UART_Rc_St2 <= UART_Rc_St1; -- D1
UART_Rc_St3 <= UART_Rc_St2; -- D2
UART_Rc_St4 <= UART_Rc_St3; -- D3
UART_Rc_St5 <= UART_Rc_St4; -- D4
UART_Rc_St6 <= UART_Rc_St5; -- D5
UART_Rc_St7 <= UART_Rc_St6; -- D6
UART_Rc_St8 <= UART_Rc_St7; -- D7
UART_Rc_St9 <= UART_Rc_St8 and CHR9; -- D8
UART_Rc_St10 <= (UART_Rc_St8 and not CHR9) or UART_Rc_St9; -- Stop bit
UART_Rc_SR(6 downto 0) <= UART_Rc_SR(7 downto 1);
UART_Rc_SR(7) <= UART_Rc_SR7_In;
UART_Rc_SR(8) <= UART_Rc_SR(9);
UART_Rc_SR(9) <= Detector_Out;
end if;
end if;
end process;
RXD_Resinc:process(cp2,ireset)
begin
if ireset='0' then -- Reset
RXD_ResyncA <= '1';
RXD_ResyncB <= '1';
elsif (cp2='1' and cp2'event) then -- Clock
RXD_ResyncA <= rxd;
RXD_ResyncB <= RXD_ResyncA;
end if;
end process;
Receiver_Detect_A:process(cp2,ireset)
begin
if ireset='0' then -- Reset
Detector_A <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (Baud_Gen_Out and UART_RcDel_St7)='1' then -- Clock enable
Detector_A <= RXD_ResyncB;
end if;
end if;
end process;
Receiver_Detect_B:process(cp2,ireset)
begin
if ireset='0' then -- Reset
Detector_B <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
if (Baud_Gen_Out and UART_RcDel_St8)='1' then -- Clock enable
Detector_B <= RXD_ResyncB;
end if;
end if;
end process;
Detector_Out <= (Detector_A and Detector_B)or(Detector_B and RXD_ResyncB)or(Detector_A and RXD_ResyncB);
UDR_Rx_Reg:process(cp2,ireset)
begin
if ireset='0' then -- Reset
UDR_Rx <= (others => '0');
FE <= '0'; -- Framing error
elsif (cp2='1' and cp2'event) then -- Clock
if (UART_Rc_Delay and RXEN and not RXC)='1' then -- Clock enable ??? TBD
UDR_Rx <= UART_Rc_SR(7 downto 0);
FE <= not UART_Rc_SR(9); -- Framing error
end if;
end if;
end process;
UCR_RXB8:process(cp2,ireset)
begin
if ireset='0' then -- Reset
RXB8 <= '1'; -- ??? Check the papers again
elsif (cp2='1' and cp2'event) then -- Clock
if (UART_Rc_Delay and RXEN and not RXC and CHR9)='1' then -- Clock enable ??? TBD
RXB8 <= UART_Rc_SR(8); -- RXB8
end if;
end if;
end process;
USR_Bits:process(cp2,ireset)
begin
if ireset='0' then -- Reset
RXC <= '0';
DOR <= '0';
UART_Rc_Delay <='0';
elsif (cp2='1' and cp2'event) then -- Clock
RXC <= (not RXC and (UART_Rc_Delay and RXEN))or(RXC and not UDR_Rd);
DOR <= (not DOR and (UART_Rc_Delay and RXEN and RXC))or
(DOR and not (UART_Rc_Delay and RXEN and not RXC));
UART_Rc_Delay <= not UART_Rc_Delay and (Baud_Gen_Out and UART_Rc_St10 and UART_RcDel_St9);
end if;
end process;
-- Reserved USR bits
USR(2 downto 0) <= (others => '0');
USR_Rd <= '1' when (adr=USR_Address and iore='1') else '0';
UCR_Rd <= '1' when (adr=UCR_Address and iore='1') else '0';
UBRR_Rd <= '1' when (adr=UBRR_Address and iore='1') else '0';
-- Output multiplexer
Out_Mux: for i in dbus_out'range generate
dbus_out(i) <= (UDR_Rx(i) and UDR_Rd)or
(USR(i) and USR_Rd)or
(UCR(i) and UCR_Rd)or
(UBRR(i) and UBRR_Rd);
end generate;
-- Reciever IRQ
rxcirq <= RXC and RXCIE;
-- External lines
rx_en <= RXEN;
tx_en <= TXEN;
end RTL;

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--**********************************************************************************************
-- Resynchronizer (for bit)
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_bit is generic(
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic;
do : out std_logic
);
end rsnc_bit;
architecture rtl of rsnc_bit is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic;
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
inverted_first_stg:if (inv_f_stgs/=0) generate
seq_f_fe_prc:process(clk)
begin
if(clk='0' and clk'event) then -- Clock (falling edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
norm_first_stg:if (inv_f_stgs=0) generate
seq_f_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;

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--**********************************************************************************************
-- Resynchronizers
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package rsnc_comp_pack is
component rsnc_vect is generic(
width : integer := 8;
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end component;
component rsnc_bit is generic(
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic;
do : out std_logic
);
end component;
component rsnc_l_vect is generic(
tech : integer := 0;
width : integer := 8;
add_stgs_num : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end component;
component rsnc_l_bit is generic(
tech : integer := 0;
add_stgs_num : integer := 0
);
port(
clk : in std_logic;
di : in std_logic;
do : out std_logic
);
end component;
end rsnc_comp_pack;

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--**********************************************************************************************
-- Resynchronizer (for bit) with latch
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_l_bit is generic(
tech : integer := 0;
add_stgs_num : integer := 0
);
port(
clk : in std_logic;
di : in std_logic;
do : out std_logic
);
end rsnc_l_bit;
architecture rtl of rsnc_l_bit is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic;
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
-- Latch
latch_prc:process(clk)
begin
if(clk='0') then -- Clock (falling edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
-- Latch
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;

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--**********************************************************************************************
-- Resynchronizer (for n-bit vector) with latch
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_l_vect is generic(
tech : integer := 0;
width : integer := 8;
add_stgs_num : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end rsnc_l_vect;
architecture rtl of rsnc_l_vect is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic_vector(width-1 downto 0);
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
-- Latch
latch_prc:process(clk)
begin
if(clk='0') then
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
-- Latch
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;

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--**********************************************************************************************
-- Resynchronizer (for n-bit vector)
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_vect is generic(
width : integer := 8;
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end rsnc_vect;
architecture rtl of rsnc_vect is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic_vector(width-1 downto 0);
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
inverted_first_stg:if (inv_f_stgs/=0) generate
seq_f_fe_prc:process(clk)
begin
if(clk='0' and clk'event) then -- Clock (falling edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
norm_first_stg:if (inv_f_stgs=0) generate
seq_f_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;

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--**********************************************************************************************
-- SPI Peripheral for the AVR Core
-- Version 1.2
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
-- Internal resynchronizers for scki and ss_b inputs were added
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.std_library.all;
use WORK.avr_adr_pack.all;
use WORK.rsnc_comp_pack.all;
entity spi_mod is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- SPI i/f
misoi : in std_logic;
mosii : in std_logic;
scki : in std_logic; -- Resynch
ss_b : in std_logic; -- Resynch
misoo : out std_logic;
mosio : out std_logic;
scko : out std_logic;
spe : out std_logic;
spimaster : out std_logic;
-- IRQ
spiirq : out std_logic;
spiack : in std_logic;
-- Slave Programming Mode
por : in std_logic;
spiextload : in std_logic;
spidwrite : out std_logic;
spiload : out std_logic
);
end spi_mod;
architecture RTL of spi_mod is
-- Resynch
signal scki_resync : std_logic;
signal ss_b_resync : std_logic;
-- Registers
signal SPCR : std_logic_vector(7 downto 0);
alias SPIE : std_logic is SPCR(7);
alias SPEB : std_logic is SPCR(6); -- SPE in Atmel's doc
alias DORD : std_logic is SPCR(5);
alias MSTR : std_logic is SPCR(4);
alias CPOL : std_logic is SPCR(3);
alias CPHA : std_logic is SPCR(2);
alias SPR : std_logic_vector(1 downto 0) is SPCR(1 downto 0);
signal SPSR : std_logic_vector(7 downto 0);
alias SPIF : std_logic is SPSR(7);
alias WCOL : std_logic is SPSR(6);
alias SPI2X : std_logic is SPSR(0);
signal SPIE_Next : std_logic;
signal SPEB_Next : std_logic;
signal DORD_Next : std_logic;
signal CPOL_Next : std_logic;
signal CPHA_Next : std_logic;
signal SPR_Next : std_logic_vector(SPR'range);
signal SPI2X_Next : std_logic;
signal SPDR_Rc : std_logic_vector(7 downto 0);
signal SPDR_Rc_Next : std_logic_vector(7 downto 0);
signal SPDR_Sh_Current : std_logic_vector(7 downto 0);
signal SPDR_Sh_Next : std_logic_vector(7 downto 0);
signal Div_Next : std_logic_vector(5 downto 0);
signal Div_Current : std_logic_vector(5 downto 0);
signal Div_Toggle : std_logic;
signal DivCntMsb_Current : std_logic;
signal DivCntMsb_Next : std_logic;
type MstSMSt_Type is (MstSt_Idle,MstSt_B0,MstSt_B1,MstSt_B2,MstSt_B3,MstSt_B4,MstSt_B5,MstSt_B6,MstSt_B7);
signal MstSMSt_Current : MstSMSt_Type;
signal MstSMSt_Next : MstSMSt_Type;
signal TrStart : std_logic;
signal scko_Next : std_logic;
signal scko_Current : std_logic; --!!!
signal UpdRcDataRg_Current : std_logic;
signal UpdRcDataRg_Next : std_logic;
signal TmpIn_Current : std_logic;
signal TmpIn_Next : std_logic;
-- Slave
signal sck_EdgeDetDFF : std_logic;
signal SlvSampleSt : std_logic;
signal SlvSMChangeSt : std_logic;
type SlvSMSt_Type is (SlvSt_Idle,SlvSt_B0I,SlvSt_B0,SlvSt_B1,SlvSt_B2,SlvSt_B3,SlvSt_B4,SlvSt_B5,SlvSt_B6,SlvSt_B6W);
signal SlvSMSt_Current : SlvSMSt_Type;
signal SlvSMSt_Next : SlvSMSt_Type;
-- SIF clear SM
signal SPIFClrSt_Current : std_logic;
signal SPIFClrSt_Next : std_logic;
-- WCOL clear SM
signal WCOLClrSt_Current : std_logic;
signal WCOLClrSt_Next : std_logic;
signal MSTR_Next : std_logic;
signal SPIF_Next : std_logic;
signal WCOL_Next : std_logic;
signal MstDSamp_Next : std_logic;
signal MstDSamp_Current : std_logic;
function Fn_RevBitVector(InVector : std_logic_vector) return std_logic_vector is
variable TmpVect : std_logic_vector(InVector'range);
begin
for i in TmpVect'range loop
TmpVect(i) := InVector(InVector'high-i);
end loop;
return TmpVect;
end Fn_RevBitVector;
begin
-- ******************** Resynchronizers ************************************
scki_resync_inst:component rsnc_bit generic map(
add_stgs_num => 0,
inv_f_stgs => 0
)
port map(
clk => cp2,
di => scki,
do => scki_resync
);
ss_b_resync_inst:component rsnc_bit generic map(
add_stgs_num => 0,
inv_f_stgs => 0
)
port map(
clk => cp2,
di => ss_b,
do => ss_b_resync
);
-- ******************** Resynchronizers ************************************
SeqPrc:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
SPCR <= (others => '0');
SPIF <= '0';
WCOL <= '0';
SPI2X <= '0';
Div_Current <= (others => '0');
DivCntMsb_Current <= '0';
MstSMSt_Current <= MstSt_Idle;
SlvSMSt_Current <= SlvSt_Idle;
SPDR_Sh_Current <= (others => '1');
SPDR_Rc <= (others => '0');
sck_EdgeDetDFF <= '0';
SPIFClrSt_Current <= '0';
WCOLClrSt_Current <= '0';
scko <= '0';
scko_Current <= '0';
misoo <= '0';
mosio <= '0';
TmpIn_Current <= '0';
UpdRcDataRg_Current <= '0';
MstDSamp_Current <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
SPIE <= SPIE_Next;
SPEB <= SPEB_Next;
DORD <= DORD_Next;
CPOL <= CPOL_Next;
CPHA <= CPHA_Next;
SPR <= SPR_Next;
MSTR <= MSTR_Next;
SPIF <= SPIF_Next;
SPI2X <= SPI2X_Next;
WCOL <= WCOL_Next;
Div_Current <= Div_Next;
DivCntMsb_Current <= DivCntMsb_Next;
MstSMSt_Current <= MstSMSt_Next;
SlvSMSt_Current <= SlvSMSt_Next;
SPDR_Sh_Current <= SPDR_Sh_Next;
SPDR_Rc <= SPDR_Rc_Next;
sck_EdgeDetDFF <= scki_resync;
SPIFClrSt_Current <= SPIFClrSt_Next;
WCOLClrSt_Current <= WCOLClrSt_Next;
scko_Current <= scko_Next;
scko <= scko_Next;
misoo <= SPDR_Sh_Next(SPDR_Sh_Next'high);
mosio <= SPDR_Sh_Next(SPDR_Sh_Next'high);
TmpIn_Current <= TmpIn_Next;
UpdRcDataRg_Current <= UpdRcDataRg_Next;
MstDSamp_Current <= MstDSamp_Next;
end if;
end process;
IORegWriteComb:process(adr,iowe,SPCR,SPSR,dbus_in)
begin
SPIE_Next <= SPIE;
SPEB_Next <= SPEB;
DORD_Next <= DORD;
CPOL_Next <= CPOL;
CPHA_Next <= CPHA;
SPR_Next <= SPR;
SPI2X_Next <= SPI2X;
if(fn_to_integer(adr)=SPCR_Address and iowe='1') then
SPIE_Next <= dbus_in(7);
SPEB_Next <= dbus_in(6);
DORD_Next <= dbus_in(5);
CPOL_Next <= dbus_in(3);
CPHA_Next <= dbus_in(2);
SPR_Next <= dbus_in(1 downto 0);
end if;
if(fn_to_integer(adr)=SPSR_Address and iowe='1') then
SPI2X_Next <= dbus_in(0);
end if;
end process;
SPSR(5 downto 1) <= (others => '0');
-- Divider
-- SPI2X | SPR1 | SPR0 | SCK Frequency
-- 0 | 0 | 0 | fosc /4 (2)
-- 0 | 0 | 1 | fosc /16 (8)
-- 0 | 1 | 0 | fosc /64 (32)
-- 0 | 1 | 1 | fosc /128 (64)
-- ------+------+------+-------------
-- 1 | 0 | 0 | fosc /2 (1)
-- 1 | 0 | 1 | fosc /8 (4)
-- 1 | 1 | 0 | fosc /32 (16)
-- 1 | 1 | 1 | fosc /64 (32)
DividerToggleComb:process(MstSMSt_Current,Div_Current,SPCR,SPSR)
begin
Div_Toggle <= '0';
if(MstSMSt_Current /= MstSt_Idle) then
if(SPI2X='1') then -- Extended mode
case SPR is
when "00" => if (Div_Current="000001") then Div_Toggle <= '1'; end if; -- fosc /2
when "01" => if (Div_Current="000011") then Div_Toggle <= '1'; end if; -- fosc /8
when "10" => if (Div_Current="001111") then Div_Toggle <= '1'; end if; -- fosc /32
when "11" => if (Div_Current="011111") then Div_Toggle <= '1'; end if; -- fosc /64
when others => Div_Toggle <= '0';
end case;
else -- Normal mode
case SPR is
when "00" => if (Div_Current="000001") then Div_Toggle <= '1'; end if; -- fosc /4
when "01" => if (Div_Current="000111") then Div_Toggle <= '1'; end if; -- fosc /16
when "10" => if (Div_Current="011111") then Div_Toggle <= '1'; end if; -- fosc /64
when "11" => if (Div_Current="111111") then Div_Toggle <= '1'; end if; -- fosc /128
when others => Div_Toggle <= '0';
end case;
end if;
end if;
end process;
DividerNextComb:process(MstSMSt_Current,Div_Current,DivCntMsb_Current,Div_Toggle)
begin
Div_Next <= Div_Current;
DivCntMsb_Next <= DivCntMsb_Current;
if(MstSMSt_Current /= MstSt_Idle) then
if(Div_Toggle='1') then
Div_Next <= (others => '0');
DivCntMsb_Next <= not DivCntMsb_Current;
else
Div_Next <= Div_Current + 1;
end if;
end if;
end process;
TrStart <= '1' when (fn_to_integer(adr)=SPDR_Address and iowe='1' and SPEB='1') else '0';
-- Transmitter Master Mode Shift Control SM
MstSmNextComb:process(MstSMSt_Current,DivCntMsb_Current,Div_Toggle,TrStart,SPCR)
begin
MstSMSt_Next <= MstSMSt_Current;
case MstSMSt_Current is
when MstSt_Idle =>
if(TrStart='1' and MSTR='1') then
MstSMSt_Next <= MstSt_B0;
end if;
when MstSt_B0 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B1;
end if;
when MstSt_B1 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B2;
end if;
when MstSt_B2 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B3;
end if;
when MstSt_B3 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B4;
end if;
when MstSt_B4 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B5;
end if;
when MstSt_B5 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B6;
end if;
when MstSt_B6 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B7;
end if;
when MstSt_B7 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_Idle;
end if;
when others => MstSMSt_Next <= MstSt_Idle;
end case;
end process;
SPIFClrCombProc:process(SPIFClrSt_Current,SPCR,SPSR,adr,iore,iowe)
begin
SPIFClrSt_Next <= SPIFClrSt_Current;
case SPIFClrSt_Current is
when '0' =>
if(fn_to_integer(adr)=SPSR_Address and iore='1' and SPIF='1' and SPEB='1') then
SPIFClrSt_Next <= '1';
end if;
when '1' =>
if(fn_to_integer(adr)=SPDR_Address and (iore='1' or iowe='1')) then
SPIFClrSt_Next <= '0';
end if;
when others => SPIFClrSt_Next <= SPIFClrSt_Current;
end case;
end process; --SPIFClrCombProc
WCOLClrCombProc:process(WCOLClrSt_Current,SPSR,adr,iore,iowe)
begin
WCOLClrSt_Next <= WCOLClrSt_Current;
case WCOLClrSt_Current is
when '0' =>
if(fn_to_integer(adr)=SPSR_Address and iore='1' and WCOL='1') then
WCOLClrSt_Next <= '1';
end if;
when '1' =>
if(fn_to_integer(adr)=SPDR_Address and (iore='1' or iowe='1')) then
WCOLClrSt_Next <= '0';
end if;
when others => WCOLClrSt_Next <= WCOLClrSt_Current;
end case;
end process; --WCOLClrCombProc
MstDataSamplingComb:process(SPCR,scko_Current,scko_Next,MstDSamp_Current,MstSMSt_Current)
begin
MstDSamp_Next <= '0';
case MstDSamp_Current is
when '0' =>
if(MstSMSt_Current/=MstSt_Idle) then
if(CPHA=CPOL) then
if(scko_Next='1' and scko_Current='0') then -- Rising edge
MstDSamp_Next <= '1';
end if;
else -- CPHA/=CPOL
if(scko_Next='0' and scko_Current='1') then -- Falling edge
MstDSamp_Next <= '1';
end if;
end if;
end if;
when '1' => MstDSamp_Next <= '0';
when others => MstDSamp_Next <= '0';
end case;
end process; -- MstDataSamplingComb
--
DRLatchComb:process(UpdRcDataRg_Current,MstSMSt_Current,MstSMSt_Next,SlvSMSt_Current,SlvSMSt_Next,SPCR)
begin
UpdRcDataRg_Next <= '0';
case UpdRcDataRg_Current is
when '0' =>
if((MSTR='1' and MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle)or
(MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMSt_Next=SlvSt_Idle)) then
UpdRcDataRg_Next <= '1';
end if;
when '1' => UpdRcDataRg_Next <= '0';
when others => UpdRcDataRg_Next <= '0';
end case;
end process;
TmpInComb:process(TmpIn_Current,mosii,misoi,MstDSamp_Current,SlvSampleSt,SPCR,ss_b_resync)
begin
TmpIn_Next <= TmpIn_Current;
if(MSTR='1' and MstDSamp_Current='1') then -- Master mode
TmpIn_Next <= misoi;
elsif(MSTR='0' and SlvSampleSt='1' and ss_b_resync='0') then -- Slave mode ???
TmpIn_Next <= mosii;
end if;
end process;
ShiftRgComb:process(MstSMSt_Current,SlvSMSt_Current,SPDR_Sh_Current,SPCR,DivCntMsb_Current,Div_Toggle,TrStart,dbus_in,ss_b_resync,TmpIn_Current,SlvSMChangeSt,SlvSampleSt,UpdRcDataRg_Current)
begin
SPDR_Sh_Next <= SPDR_Sh_Current;
if(TrStart='1' and (MstSMSt_Current=MstSt_Idle and SlvSMSt_Current = SlvSt_Idle and not(MSTR='0' and SlvSampleSt='1' and ss_b_resync='0') )) then -- Load
if (DORD='1') then -- the LSB of the data word is transmitted first
SPDR_Sh_Next <= Fn_RevBitVector(dbus_in);
else -- the MSB of the data word is transmitted first
SPDR_Sh_Next <= dbus_in;
end if;
elsif(MSTR='1' and UpdRcDataRg_Current='1') then -- ???
SPDR_Sh_Next(SPDR_Sh_Next'high) <= '1';
elsif((MSTR='1' and MstSMSt_Current/=MstSt_Idle and DivCntMsb_Current='1' and Div_Toggle='1') or
(MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMChangeSt='1' and ss_b_resync='0')) then
-- Shift
SPDR_Sh_Next <= SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto SPDR_Sh_Current'low)&TmpIn_Current;
end if;
end process; --ShiftRgComb
sckoGenComb:process(scko_Current,SPCR,adr,iowe,dbus_in,DivCntMsb_Next,DivCntMsb_Current,TrStart,MstSMSt_Current,MstSMSt_Next)
begin
scko_Next <= scko_Current;
if(fn_to_integer(adr)=SPCR_Address and iowe='1') then -- Write to SPCR
scko_Next <= dbus_in(3); -- CPOL
elsif(TrStart='1' and CPHA='1' and MstSMSt_Current=MstSt_Idle) then
scko_Next <= not CPOL;
elsif(MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle) then -- "Parking"
scko_Next <= CPOL;
elsif(MstSMSt_Current/=MstSt_Idle and DivCntMsb_Current/=DivCntMsb_Next) then
scko_Next <= not scko_Current;
end if;
end process;
-- Receiver data register
SPDRRcComb:process(SPDR_Rc,SPCR,SPDR_Sh_Current,UpdRcDataRg_Current,TmpIn_Current)
begin
SPDR_Rc_Next <= SPDR_Rc;
if(UpdRcDataRg_Current='1') then
if(MSTR='0' and CPHA='1') then
if (DORD='1') then -- the LSB of the data word is transmitted first
SPDR_Rc_Next <= Fn_RevBitVector(SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto 0)&TmpIn_Current);
else -- the MSB of the data word is transmitted first
SPDR_Rc_Next <= SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto 0)&TmpIn_Current;
end if;
else
if (DORD='1') then -- the LSB of the data word is transmitted first
SPDR_Rc_Next <= Fn_RevBitVector(SPDR_Sh_Current);
else -- the MSB of the data word is transmitted first
SPDR_Rc_Next <= SPDR_Sh_Current;
end if;
end if;
end if;
end process;
--****************************************************************************************
-- Slave
--****************************************************************************************
SlvSampleSt <= '1' when ((sck_EdgeDetDFF='0' and scki_resync='1' and CPOL=CPHA)or -- Rising edge
(sck_EdgeDetDFF='1' and scki_resync='0' and CPOL/=CPHA))else '0'; -- Falling edge
SlvSMChangeSt <= '1' when ((sck_EdgeDetDFF='1' and scki_resync='0' and CPOL=CPHA)or -- Falling edge
(sck_EdgeDetDFF='0' and scki_resync='1' and CPOL/=CPHA))else '0'; -- Rising edge
-- Slave Master Mode Shift Control SM
SlvSMNextComb:process(SlvSMSt_Current,SPCR,SlvSampleSt,SlvSMChangeSt,ss_b_resync)
begin
SlvSMSt_Next <= SlvSMSt_Current;
if(ss_b_resync='0') then
case SlvSMSt_Current is
when SlvSt_Idle =>
if(MSTR='0') then
if(CPHA='1') then
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B0;
end if;
else -- CPHA='0'
if(SlvSampleSt='1') then
SlvSMSt_Next <= SlvSt_B0I;
end if;
end if;
end if;
when SlvSt_B0I =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B0;
end if;
when SlvSt_B0 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B1;
end if;
when SlvSt_B1 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B2;
end if;
when SlvSt_B2 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B3;
end if;
when SlvSt_B3 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B4;
end if;
when SlvSt_B4 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B5;
end if;
when SlvSt_B5 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B6;
end if;
when SlvSt_B6 =>
if(SlvSMChangeSt='1') then
if(CPHA='0') then
SlvSMSt_Next <= SlvSt_Idle;
else -- CPHA='1'
SlvSMSt_Next <= SlvSt_B6W;
end if;
end if;
when SlvSt_B6W =>
if(SlvSampleSt='1')then
SlvSMSt_Next <= SlvSt_Idle;
end if;
when others => SlvSMSt_Next <= SlvSt_Idle;
end case;
end if;
end process;
MSTRGenComb:process(adr,iowe,dbus_in,ss_b_resync,SPCR)
begin
MSTR_Next <= MSTR;
case MSTR is
when '0' =>
if(fn_to_integer(adr)=SPCR_Address and iowe='1' and dbus_in(4)='1') then -- TBD (ss_b_resync='0')
MSTR_Next <= '1';
end if;
when '1' =>
if((fn_to_integer(adr)=SPCR_Address and iowe='1' and dbus_in(4)='0') or
(ss_b_resync='0')) then
MSTR_Next <= '0';
end if;
when others => MSTR_Next <= MSTR;
end case;
end process;
WCOLGenComb:process(WCOLClrSt_Current,SlvSMSt_Current,MstSMSt_Current,adr,iowe,iore,SPCR,SPSR,SlvSampleSt,ss_b_resync)
begin
WCOL_Next <= WCOL;
case WCOL is
when '0' =>
if(fn_to_integer(adr)=SPDR_Address and iowe='1' and
((MSTR='0' and (SlvSMSt_Current/=SlvSt_Idle or (SlvSampleSt='1' and ss_b_resync='0'))) or
(MSTR='1' and MstSMSt_Current/=MstSt_Idle))) then
WCOL_Next <= '1';
end if;
when '1' =>
if(((fn_to_integer(adr)=SPDR_Address and (iowe='1' or iore='1')) and WCOLClrSt_Current='1') and
not (fn_to_integer(adr)=SPDR_Address and iowe='1' and
((MSTR='0' and (SlvSMSt_Current/=SlvSt_Idle or (SlvSampleSt='1' and ss_b_resync='0'))) or
(MSTR='1' and MstSMSt_Current/=MstSt_Idle)))) then
WCOL_Next <= '0';
end if;
when others => WCOL_Next <= WCOL;
end case;
end process;
SPIFGenComb:process(SPIFClrSt_Current,adr,iowe,iore,SPCR,SPSR,SlvSMSt_Current,SlvSMSt_Next,MstSMSt_Current,MstSMSt_Next,spiack)
begin
SPIF_Next <= SPIF;
case SPIF is
when '0' =>
if((MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMSt_Next=SlvSt_Idle) or
(MSTR='1' and MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle))then
SPIF_Next <= '1';
end if;
when '1' =>
if((fn_to_integer(adr)=SPDR_Address and (iowe='1' or iore='1') and SPIFClrSt_Current='1') or spiack='1') then
SPIF_Next <= '0';
end if;
when others => SPIF_Next <= SPIF;
end case;
end process;
--*************************************************************************************
spimaster <= MSTR;
spe <= SPEB;
-- IRQ
spiirq <= SPIE and SPIF;
OutMuxComb:process(adr,iore,SPDR_Rc,SPSR,SPCR)
begin
case(fn_to_integer(adr)) is
when SPDR_Address => dbus_out <= SPDR_Rc; out_en <= iore;
when SPSR_Address => dbus_out <= SPSR; out_en <= iore;
when SPCR_Address => dbus_out <= SPCR; out_en <= iore;
when others => dbus_out <= (others => '0'); out_en <= '0';
end case;
end process; -- OutMuxComb
--
spidwrite <= '0';
spiload <= '0';
end RTL;

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--**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package spi_mod_comp_pack is
component spi_mod is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- SPI i/f
misoi : in std_logic;
mosii : in std_logic;
scki : in std_logic; -- Resynch
ss_b : in std_logic; -- Resynch
misoo : out std_logic;
mosio : out std_logic;
scko : out std_logic;
spe : out std_logic;
spimaster : out std_logic;
-- IRQ
spiirq : out std_logic;
spiack : in std_logic;
-- Slave Programming Mode
por : in std_logic;
spiextload : in std_logic;
spidwrite : out std_logic;
spiload : out std_logic
);
end component;
end spi_mod_comp_pack;

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--**********************************************************************************************
-- SPI Peripheral for the AVR Core
-- Version 1.2
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.std_library.all;
use WORK.avr_adr_pack.all;
entity spi_slv_sel is generic(num_of_slvs : integer := 7);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- Output
slv_sel_n : out std_logic_vector(num_of_slvs-1 downto 0)
);
end spi_slv_sel;
architecture RTL of spi_slv_sel is
constant SPISlvDcd_Address : integer := PINF_Address;
signal SlvSelRg_Current : std_logic_vector(num_of_slvs-1 downto 0);
signal SlvSelRg_Next : std_logic_vector(num_of_slvs-1 downto 0);
begin
RegWrSeqPrc:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
SlvSelRg_Current <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
SlvSelRg_Current <= SlvSelRg_Next;
end if;
end process;
RegWrComb:process(adr,iowe,dbus_in,SlvSelRg_Current)
begin
SlvSelRg_Next <= SlvSelRg_Current;
if(fn_to_integer(adr)=SPISlvDcd_Address and iowe='1') then
SlvSelRg_Next <= dbus_in(num_of_slvs-1 downto 0);
end if;
end process;
slv_sel_n <= not SlvSelRg_Current(slv_sel_n'range);
out_en <= '1' when (fn_to_integer(adr)=SPISlvDcd_Address and iore='1') else '0';
dbus_out(num_of_slvs-1 downto 0) <= SlvSelRg_Current;
UnusedBits:if(num_of_slvs<8) generate
dbus_out(dbus_out'high downto num_of_slvs) <= (others => '0');
end generate;
end RTL;

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--**********************************************************************************************
--
-- Version 0.2
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package spi_slv_sel_comp_pack is
component spi_slv_sel is generic(num_of_slvs : integer := 7);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- Output
slv_sel_n : out std_logic_vector(num_of_slvs-1 downto 0)
);
end component;
end spi_slv_sel_comp_pack;

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--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
package AVR_uC_CompPack is
component pport is generic(PPortNum : natural);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External connection
portx : out std_logic_vector(7 downto 0);
ddrx : out std_logic_vector(7 downto 0);
pinx : in std_logic_vector(7 downto 0);
irqlines : out std_logic_vector(7 downto 0));
end component;
component external_mux is port (
ramre : in std_logic;
dbus_out : out std_logic_vector (7 downto 0);
ram_data_out : in std_logic_vector (7 downto 0);
io_port_bus : in ext_mux_din_type;
io_port_en_bus : in ext_mux_en_type;
irqack : in std_logic;
irqackad : in std_logic_vector(4 downto 0);
ind_irq_ack : out std_logic_vector(22 downto 0)
);
end component;
component RAMDataReg is port(
ireset : in std_logic;
cp2 : in std_logic;
cpuwait : in std_logic;
RAMDataIn : in std_logic_vector(7 downto 0);
RAMDataOut : out std_logic_vector(7 downto 0)
);
end component;
component Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end component;
COMPONENT ExtIRQ_Controller
PORT(
-- begin Signals required by AVR8 for this core, do not modify.
nReset : in STD_LOGIC;
clk : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (15 downto 0);
dbus_in : in STD_LOGIC_VECTOR (7 downto 0);
dbus_out : out STD_LOGIC_VECTOR (7 downto 0);
iore : in STD_LOGIC;
iowe : in STD_LOGIC;
out_en : out STD_LOGIC;
-- end Signals required by AVR8 for this core, do not modify.
clken : in STD_LOGIC;
irq_clken : in STD_LOGIC;
extpins : in STD_LOGIC_VECTOR(7 downto 0);
INTx : out STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
----*************** UART ***************************
--component uart is port(
-- -- AVR Control
-- ireset : in std_logic;
-- cp2 : in std_logic;
-- adr : in std_logic_vector(15 downto 0);
-- dbus_in : in std_logic_vector(7 downto 0);
-- dbus_out : out std_logic_vector(7 downto 0);
-- iore : in std_logic;
-- iowe : in std_logic;
-- out_en : out std_logic;
--
-- --UART
-- rxd : in std_logic;
-- rx_en : out std_logic;
-- txd : out std_logic;
-- tx_en : out std_logic;
--
-- --IRQ
-- txcirq : out std_logic;
-- txc_irqack : in std_logic;
-- udreirq : out std_logic;
-- rxcirq : out std_logic);
--end component;
-- Core itself
component AVR_Core is port(
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
-- JTAG OCD support
valid_instr : out std_logic;
insert_nop : in std_logic;
block_irq : in std_logic;
change_flow : out std_logic;
-- Program Memory
pc : out std_logic_vector (15 downto 0);
inst : in std_logic_vector (15 downto 0);
-- I/O control
adr : out std_logic_vector (15 downto 0);
iore : out std_logic;
iowe : out std_logic;
-- Data memory control
ramadr : out std_logic_vector (15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic;
-- Data paths
dbusin : in std_logic_vector (7 downto 0);
dbusout : out std_logic_vector (7 downto 0);
-- Interrupt
irqlines : in std_logic_vector (22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
--Sleep Control
sleepi : out std_logic;
irqok : out std_logic;
globint : out std_logic;
--Watchdog
wdri : out std_logic);
end component;
-- Reset generator
component ResetGenerator is port(
-- Clock inputs
cp2 : in std_logic;
cp64m : in std_logic;
-- Reset inputs
nrst : in std_logic;
npwrrst : in std_logic;
wdovf : in std_logic;
jtagrst : in std_logic;
-- Reset outputs
nrst_cp2 : out std_logic;
nrst_cp64m : out std_logic;
nrst_clksw : out std_logic
);
end component;
-- Components for the simulation only
component PROM is port(
address_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0));
end component;
component DataRAM is
generic(RAMSize :positive);
port (
cp2 : in std_logic;
address : in std_logic_vector (LOG2(RAMSize)-1 downto 0);
ramwe : in std_logic;
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0));
end component;
component CPUWaitGenerator is port(
ireset : in std_logic;
cp2 : in std_logic;
ramre : in std_logic;
ramwe : in std_logic;
cpuwait : out std_logic
);
end component;
component ClockSwitch is port(
-- Reset
ireset : in std_logic;
-- Clock input and output
cp2_In : in std_logic;
cp2_Out : out std_logic;
-- Control inputs
sleepi : in std_logic;
irqok : in std_logic;
globint : in std_logic;
sleep_en : in std_logic
);
end component;
-- JTAG
component JTAGOCDPrgTop is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic;
-- CPU reset
jtag_rst : out std_logic
);
end component;
component uart is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- UART
rxd : in std_logic;
rx_en : out std_logic;
txd : out std_logic;
tx_en : out std_logic;
-- IRQ
txcirq : out std_logic;
txc_irqack : in std_logic;
udreirq : out std_logic;
rxcirq : out std_logic
);
end component;
-- SMBus
--component SMBusMod is port(
-- -- AVR Control
-- ireset : in std_logic;
-- cp2 : in std_logic;
-- adr : in std_logic_vector(15 downto 0);
-- dbus_in : in std_logic_vector(7 downto 0);
-- dbus_out : out std_logic_vector(7 downto 0);
-- iore : in std_logic;
-- iowe : in std_logic;
-- out_en : out std_logic;
-- -- Slave IRQ
-- twiirq : out std_logic;
-- -- Master IRQ
-- msmbirq : out std_logic;
-- -- "Off state" timer IRQ
-- offstirq : out std_logic;
-- offstirq_ack : in std_logic;
-- -- TRI control and data for the slave channel
-- sdain : in std_logic;
-- sdaout : out std_logic;
-- sdaen : out std_logic;
-- sclin : in std_logic;
-- sclout : out std_logic;
-- sclen : out std_logic;
-- -- TRI control and data for the master channel
-- msdain : in std_logic;
-- msdaout : out std_logic;
-- msdaen : out std_logic;
-- msclin : in std_logic;
-- msclout : out std_logic;
-- msclen : out std_logic
-- );
--
--end component;
component FrqDiv is port(
clk_in : in std_logic;
clk_out : out std_logic
);
end component;
end AVR_uC_CompPack;

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--************************************************************************************************
-- Component declarations for AVR core (Bus Masters)
-- Version 0.3
-- Designed by Ruslan Lepetenok
-- Modified 04.08.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package BusMastCompPack is
component uart_dma_top is port(
-- Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Data memory i/f (Slave part)
stb_IO : in std_logic; -- SE
stb_module : in std_logic; -- SE
sramadr : in std_logic_vector(3 downto 0); -- ??
sramre : in std_logic;
sramwe : in std_logic;
sram_dbus_out : out std_logic_vector(7 downto 0);
sram_dbus_in : in std_logic_vector(7 downto 0);
sram_dbus_out_en : out std_logic;
-- Data memory i/f (Master part)
mramadr : out std_logic_vector(15 downto 0);
mramre : out std_logic;
mramwe : out std_logic;
mram_dbus_out : in std_logic_vector(7 downto 0);
mram_dbus_in : out std_logic_vector(7 downto 0);
mack : in std_logic;
-- UART related ports
adr : in std_logic_vector(5 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- Interrupts
txcirq : out std_logic;
txc_irqack : in std_logic;
udreirq : out std_logic;
udreirq_ack : in std_logic;
rxcirq : out std_logic;
rxcirq_ack : in std_logic;
-- Wake up IRQ
wupirq : out std_logic;
wup_irqack : in std_logic;
-- External connections
rxd : in std_logic;
txd : out std_logic;
rx_en : out std_logic;
tx_en : out std_logic;
-- IE status
ie_stat : out std_logic_vector(4 downto 0)
);
end component;
component aescmdi_top is port(
-- Clock and reset
cp2 : in std_logic;
ireset : in std_logic;
-- RAM interface (Slave part)
--ssel : in std_logic;
stb_IO : in std_logic;
stb_module : in std_logic;
sramadr : in std_logic_vector(3 downto 0); -- ??
sramre : in std_logic;
sramwe : in std_logic;
sram_dbus_out : out std_logic_vector(7 downto 0);
sram_dbus_in : in std_logic_vector(7 downto 0);
sram_dbus_out_en : out std_logic;
-- RAM interface (Master part)
mramadr : out std_logic_vector(15 downto 0);
mramre : out std_logic;
mramwe : out std_logic;
mram_dbus_out : in std_logic_vector(7 downto 0);
mram_dbus_in : out std_logic_vector(7 downto 0);
mack : in std_logic;
-- Interrupt support
aes_irq : out std_logic;
aes_irqack : in std_logic
);
end component;
end BusMastCompPack;

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--**********************************************************************************************
-- External Interrupt Controller Block Peripheral for the AVR Core
-- Version 1.00
-- Created 01.26.2013
-- Designed by Rob Brown
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity ExtIRQ_Controller is Port(
-- begin Signals required by AVR8 for this core, do not modify.
nReset : in STD_LOGIC;
clk : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (15 downto 0);
dbus_in : in STD_LOGIC_VECTOR (7 downto 0);
dbus_out : out STD_LOGIC_VECTOR (7 downto 0);
iore : in STD_LOGIC;
iowe : in STD_LOGIC;
out_en : out STD_LOGIC;
-- end Signals required by AVR8 for this core, do not modify.
clken : in STD_LOGIC;
irq_clken : in STD_LOGIC;
extpins : in STD_LOGIC_VECTOR(7 downto 0);
INTx : out STD_LOGIC_VECTOR(7 downto 0)
);
end ExtIRQ_Controller;
-----------------------------------------------------------------------
architecture Behavioral of ExtIRQ_Controller is
-- Registers
signal EIMSK : std_logic_vector(7 downto 0);
signal EIFR : std_logic_vector(7 downto 0);
signal EICR : std_logic_vector(7 downto 0);
-- EIMSK Bits
alias INT0 : std_logic is EIMSK(0);
alias INT1 : std_logic is EIMSK(1);
alias INT2 : std_logic is EIMSK(2);
alias INT3 : std_logic is EIMSK(3);
alias INT4 : std_logic is EIMSK(4);
alias INT5 : std_logic is EIMSK(5);
alias INT6 : std_logic is EIMSK(6);
alias INT7 : std_logic is EIMSK(7);
-- EIFR Bits
alias INTF0 : std_logic is EIFR(0);
alias INTF1 : std_logic is EIFR(1);
alias INTF2 : std_logic is EIFR(2);
alias INTF3 : std_logic is EIFR(3);
alias INTF4 : std_logic is EIFR(4);
alias INTF5 : std_logic is EIFR(5);
alias INTF6 : std_logic is EIFR(6);
alias INTF7 : std_logic is EIFR(7);
-- EICR Bits
alias ISC40 : std_logic is EICR(0);
alias ISC41 : std_logic is EICR(1);
alias ISC50 : std_logic is EICR(2);
alias ISC51 : std_logic is EICR(3);
alias ISC60 : std_logic is EICR(4);
alias ISC61 : std_logic is EICR(5);
alias ISC70 : std_logic is EICR(6);
alias ISC71 : std_logic is EICR(7);
-- Risign/falling edge detectors
signal INTxRE : std_logic_vector (7 downto 0); -- Rising edge of external input INTx
signal INTxFE : std_logic_vector (7 downto 0); -- Falling edge of external input INT0
signal INTxLatched : std_logic_vector (7 downto 0);
-- Synchronizer signals
signal INTxSA : std_logic_vector (7 downto 0);
signal INTxSB : std_logic_vector (7 downto 0); -- Output of the synchronizer for INTx
signal TRGR : std_logic_vector(7 downto 0);
--constant EIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#39#);
--constant EIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#38#);
--constant EICR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3A#);
begin
-- Synchronizers
SyncDFFs:process(clk,nReset)
begin
if (nReset='0') then -- Reset
INTxSA <= (others => '0');
INTxSB <= (others => '0');
elsif (clk='1' and clk'event) then -- Clock
if (irq_clken='1') then -- Clock Enable(Note 2)
INTxSA <= extpins;
INTxSB <= INTxSA;
end if;
end if;
end process;
-- Edge Detector
edge_detect:for i in INTxSB'range generate
INTxRE(i) <= (not INTxSB(i) and extpins(i));
INTxFE(i) <= (INTxSB(i) and not extpins(i));
INTxLatched(i) <= INTxSB(i);
end generate;
-- Interrupt Process
INT_Proc:process(clk,nReset)
begin
if (nReset='0') then
INTx(3 downto 0) <= (others => '0');
elsif (clk='1' and clk'event) then
if (clken='1') then -- Clock Enable
-- interrupts 0 through 3 do not set their corresponding EIFR flag! See Atmega103 Data Sheet top of page 31.
-- these four interrupts also do not use EICR bits. They are always level triggered, active low.
TRGR(0) <= (INT0 and not INTxLatched(0));
TRGR(1) <= (INT1 and not INTxLatched(1));
TRGR(2) <= (INT2 and not INTxLatched(2));
TRGR(3) <= (INT3 and not INTxLatched(3));
-- interrupts 4 through 7's triggers are sensitive to EICR bits
-- 00 low level trigger, 10 falling edge trigger, 11 rising edge trigger, 01 is reserved.
-- See Atmega103 Data Sheet page 30 and 31.
TRGR(4) <= (INT4 and ((not ISC41 and not ISC40 and not INTxLatched(4)) or (ISC41 and not ISC40 and INTxFE(4)) or (ISC41 and ISC40 and INTxRE(4))));
TRGR(5) <= (INT5 and ((not ISC51 and not ISC50 and not INTxLatched(5)) or (ISC51 and not ISC50 and INTxFE(5)) or (ISC51 and ISC50 and INTxRE(5))));
TRGR(6) <= (INT6 and ((not ISC61 and not ISC60 and not INTxLatched(6)) or (ISC61 and not ISC60 and INTxFE(6)) or (ISC61 and ISC60 and INTxRE(6))));
TRGR(7) <= (INT7 and ((not ISC71 and not ISC70 and not INTxLatched(7)) or (ISC71 and not ISC70 and INTxFE(7)) or (ISC71 and ISC70 and INTxRE(7))));
INTx <= TRGR;
end if;
end if;
end process;
-- Write EIMSK bits
EIMSK_Bits:process(clk,nReset)
begin
if (nReset='0') then
EIMSK <= (others => '0');
elsif (clk='1' and clk'event) then
if (clken='1') then -- Clock Enable
if (adr=EIMSK_Address and iowe='1') then
EIMSK <= dbus_in;
end if;
end if;
end if;
end process;
-- Write EIFR bits
EIFR_Bits:process(clk,nReset)
begin
if (nReset='0') then
EIFR <= (others => '0');
elsif (clk='1' and clk'event) then
if (clken='1') then -- Clock Enable
if (adr=EIFR_Address and iowe='1') then
EIFR(7 downto 4) <= EIFR(7 downto 4) and not dbus_in(7 downto 4);
EIFR(3 downto 0) <= "0000"; -- in Atmega103, these bits are reserved and always read '0', See Atmega103 Data Sheet top of page 31.
else
EIFR(7 downto 4) <= EIFR(7 downto 4) or TRGR(7 downto 4);
EIFR(3 downto 0) <= "0000"; -- in Atmega103, these bits are reserved and always read '0', See Atmega103 Data Sheet top of page 31.
end if;
end if;
end if;
end process;
-- Write EICR bits
EICR_Bits:process(clk,nReset)
begin
if (nReset='0') then
EICR <= (others => '0');
elsif (clk='1' and clk'event) then
if (clken='1') then -- Clock Enable
if (adr=EICR_Address and iowe='1') then
EICR <= dbus_in;
end if;
end if;
end if;
end process;
-- Output Enable
out_en <= '1' when ((adr=EIMSK_Address or adr=EIFR_Address or adr=EICR_Address) and iore='1') else '0';
-- Read register
dbus_out <= EIMSK when (adr=EIMSK_Address) else
EIFR when (adr=EIFR_Address) else
EICR when (adr=EICR_Address) else
"ZZZZZZZZ";
end Behavioral;

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--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity RAMDataReg is port(
ireset : in std_logic;
cp2 : in std_logic;
cpuwait : in std_logic;
RAMDataIn : in std_logic_vector(7 downto 0);
RAMDataOut : out std_logic_vector(7 downto 0)
);
end RAMDataReg;
architecture RTL of RAMDataReg is
begin
RAMDataReg:process(cp2,ireset)
begin
if ireset='0' then -- Reset
RAMDataOut <= (others => '0');
elsif cp2='1' and cp2'event then -- Clock
if cpuwait='0' then -- Clock enable
RAMDataOut <= RAMDataIn;
end if;
end if;
end process;
end RTL;

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--**********************************************************************************************
-- Reset generator for the AVR Core
-- Version 0.7
-- Modified 23.07.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.SynthCtrlPack.all;
entity ResetGenerator is port(
-- Clock inputs
cp2 : in std_logic;
cp64m : in std_logic;
-- Reset inputs
nrst : in std_logic;
npwrrst : in std_logic;
wdovf : in std_logic;
jtagrst : in std_logic;
-- Reset outputs
nrst_cp2 : out std_logic;
nrst_cp64m : out std_logic;
nrst_clksw : out std_logic
);
end ResetGenerator;
architecture RTL of ResetGenerator is
signal cp2RstA : std_logic;
signal cp2RstB : std_logic;
signal cp2RstC : std_logic;
signal cp64mRstA : std_logic;
signal cp64mRstB : std_logic;
signal nrst_ResyncA : std_logic;
signal nrst_ResyncB : std_logic;
signal ClrRstDFF : std_logic;
signal ClrRstDFF_Tmp : std_logic;
signal RstDelayA : std_logic;
signal RstDelayB : std_logic;
begin
nrst_Resync_DFFs:process(cp2)
begin
if cp2='1' and cp2'event then -- Clock
nrst_ResyncA <= nrst;
nrst_ResyncB <= nrst_ResyncA;
end if;
end process;
ResetDFF:process(cp2)
begin
if cp2='1' and cp2'event then -- Clock
if wdovf='1' or jtagrst='1' or nrst_ResyncB='0' or npwrrst='0' then
ClrRstDFF_Tmp <= '0'; -- Reset
else
ClrRstDFF_Tmp <= '1'; -- Normal state
end if;
end if;
end process;
ClrRstDFF <= ClrRstDFF_Tmp; -- !!!TBD!!! GLOBAL primitive may be used !!!
-- High speed clock domain reset(if exists)
SecondClock:if CSecondClockUsed generate
Reset_cp64m_DFFs:process(ClrRstDFF,cp64m)
begin
if ClrRstDFF='0' then -- Reset
cp64mRstA <= '0';
cp64mRstB <= '0';
elsif cp64m='1' and cp64m'event then -- Clock
cp64mRstA <= '1';
cp64mRstB <= cp64mRstA;
end if;
end process;
-- Reset signal for 64 MHz clock domain
nrst_cp64m <= cp64mRstB;
end generate;
-- High speed clock domain doesn't exist
NoSecondClock:if not CSecondClockUsed generate
cp64mRstB <= '1';
nrst_cp64m <= '0';
end generate;
-- Low speed clock domain reset
Reset_cp2_DFFs:process(ClrRstDFF,cp2)
begin
if ClrRstDFF='0' then -- Reset
cp2RstA <= '0';
cp2RstB <= '0';
cp2RstC <= '0';
elsif cp2='1' and cp2'event then -- Clock
-- cp2RstA <= cp64mRstB;
cp2RstA <= RstDelayB;
cp2RstB <= cp2RstA;
cp2RstC <= cp2RstB;
end if;
end process;
-- Reset delay line
Reset_Delay_DFFs:process(ClrRstDFF,cp2)
begin
if ClrRstDFF='0' then -- Reset
RstDelayA <= '0';
RstDelayB <= '0';
elsif cp2='1' and cp2'event then -- Clock
RstDelayA <= cp64mRstB;
RstDelayB <= RstDelayA;
end if;
end process;
-- Reset signal for cp2 clock domain
nrst_cp2 <= cp2RstC;
-- Separate reset for clock enable module
nrst_clksw <= RstDelayB;
end RTL;

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--************************************************************************************************
-- External multeplexer for AVR core
-- Version 2.2
-- Designed by Ruslan Lepetenok 05.11.2001
-- Modified 29.08.2003
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity external_mux is port(
ramre : in std_logic;
dbus_out : out std_logic_vector(7 downto 0);
ram_data_out : in std_logic_vector(7 downto 0);
io_port_bus : in ext_mux_din_type;
io_port_en_bus : in ext_mux_en_type;
irqack : in std_logic;
irqackad : in std_logic_vector(4 downto 0);
ind_irq_ack : out std_logic_vector(22 downto 0)
);
end external_mux;
architecture RTL of external_mux is
signal ext_mux_out : ext_mux_din_type;
begin
ext_mux_out(0) <= io_port_bus(0) when io_port_en_bus(0)='1' else (others => '0');
data_mux_for_read:for i in 1 to ext_mux_out'high generate
ext_mux_out(i) <= io_port_bus(i) when io_port_en_bus(i)='1' else ext_mux_out(i-1);
end generate;
dbus_out <= ram_data_out when ramre='1' else ext_mux_out(ext_mux_out'high);
interrupt_ack:for i in ind_irq_ack'range generate
ind_irq_ack(i) <= '1' when (irqackad=i+1 and irqack='1') else '0';
end generate;
end RTL;

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ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
Inst_AVR8/PM_Inst/RAM_Word1 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
Inst_AVR8/PM_Inst/RAM_Word2 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
Inst_AVR8/PM_Inst/RAM_Word3 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
Inst_AVR8/PM_Inst/RAM_Word4 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
Inst_AVR8/PM_Inst/RAM_Word5 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
Inst_AVR8/PM_Inst/RAM_Word6 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

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--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomBusMon.vhd
-- /___/ /\ Timestamp : 30/05/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomBusMon
--Device: XC3S250E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.OhoPack.all ;
entity AtomBusMon is
port (clock49 : in std_logic;
nreset : in std_logic;
-- 6502 Signals
Addr : in std_logic_vector(15 downto 0);
Phi2 : in std_logic;
RNW : in std_logic;
Sync : in std_logic;
Rdy : out std_logic;
-- HD44780 LCD
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic;
lcd_db : inout std_logic_vector(7 downto 4);
-- AVR Serial Port
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- GODIL Switches
sw1 : in std_logic;
nsw2 : in std_logic;
-- GODIL LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end AtomBusMon;
architecture behavioral of AtomBusMon is
signal clock_avr : std_logic;
signal lcd_rw_int : std_logic;
signal lcd_db_in : std_logic_vector(7 downto 4);
signal lcd_db_out : std_logic_vector(7 downto 4);
signal nrst : std_logic;
signal dy_counter : std_logic_vector(31 downto 0);
signal dy_data : y2d_type ;
signal addr_sync : std_logic_vector(15 downto 0);
signal addr_inst : std_logic_vector(15 downto 0);
signal single : std_logic;
signal step : std_logic;
signal step1 : std_logic;
signal step2 : std_logic;
begin
inst_dcm5 : entity work.DCM0 port map(
CLKIN_IN => clock49,
CLK0_OUT => clock_avr,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
inst_oho_dy1 : entity work.Oho_Dy1 port map (
dy_clock => clock49,
dy_rst_n => '1',
dy_data => dy_data,
dy_update => '1',
dy_frame => open,
dy_frameend => open,
dy_frameend_c => open,
dy_pwm => "1010",
dy_counter => dy_counter,
dy_sclk => tdin,
dy_ser => tcclk,
dy_rclk => tmosi
);
Inst_AVR8: entity work.AVR8 port map(
clk16M => clock_avr,
nrst => nrst,
portain(0) => '0',
portain(1) => '0',
portain(2) => '0',
portain(3) => '0',
portain(4) => lcd_db_in(4),
portain(5) => lcd_db_in(5),
portain(6) => lcd_db_in(6),
portain(7) => lcd_db_in(7),
portaout(0) => lcd_rs,
portaout(1) => lcd_rw_int,
portaout(2) => lcd_e,
portaout(3) => open,
portaout(4) => lcd_db_out(4),
portaout(5) => lcd_db_out(5),
portaout(6) => lcd_db_out(6),
portaout(7) => lcd_db_out(7),
portbin => (others => '0'),
portbout(0) => step,
portbout(1) => single,
portbout(7 downto 2) => open,
portdin => addr_inst(7 downto 0),
portdout => open,
portein => addr_inst(15 downto 8),
porteout => open,
spi_mosio => open,
spi_scko => open,
spi_misoi => '0',
rxd => avr_RxD,
txd => avr_TxD
);
lcd_rw <= lcd_rw_int;
lcd_db <= lcd_db_out when lcd_rw_int = '0' else (others => 'Z');
lcd_db_in <= lcd_db;
led3 <= dy_counter(24); -- red
led6 <= dy_counter(24); -- red
led8 <= not sw1; -- green
nrst <= nsw2;
-- OHO DY1 Display for Testing
dy_data(0) <= hex & "0000" & Addr(3 downto 0);
dy_data(1) <= hex & "0000" & Addr(7 downto 4);
dy_data(2) <= hex & "0000" & "00" & (not nsw2) & sw1;
-- 6502 Control
syncProcess: process (Phi2)
begin
if rising_edge(Phi2) then
step1 <= step;
step2 <= step1;
if ((single = '0') or (step2 = '0' and step1 = '1')) then
Rdy <= '1';
else
Rdy <= not Sync;
end if;
addr_sync <= Addr;
if (Sync = '1') then
addr_inst <= Addr;
end if;
end if;
end process;
end behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM0 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end DCM0;
architecture BEHAVIORAL of DCM0 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 15.855 =49.152 * 10 / 31
CLKFX_DIVIDE => 31,
CLKFX_MULTIPLY => 10,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;

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NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
NET "lcd_rs" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6847 pin 2
NET "lcd_rw" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6847 pin 3
NET "lcd_e" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6847 pin 4
NET "lcd_db<4>" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6847 pin 5
NET "lcd_db<5>" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6847 pin 6
NET "lcd_db<6>" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6847 pin 7
NET "lcd_db<7>" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6847 pin 8
NET "avr_RxD" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6847 pin 9
NET "avr_TxD" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6847 pin 10
NET "nreset" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6847 pin 11
NET "Addr<0>" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6847 pin 21
NET "Addr<1>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6847 pin 22
NET "Addr<2>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6847 pin 23
NET "Addr<3>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6847 pin 24
NET "Addr<4>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6847 pin 25
NET "Addr<5>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6847 pin 26
NET "Addr<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6847 pin 27
NET "Addr<7>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6847 pin 28
NET "Addr<8>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6847 pin 29
NET "Addr<9>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6847 pin 30
NET "Addr<10>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6847 pin 31
NET "Addr<11>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6847 pin 32
NET "Addr<12>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6847 pin 33
NET "Addr<13>" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6847 pin 34
NET "Addr<14>" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6847 pin 35
NET "Addr<15>" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6847 pin 36
NET "Phi2" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6847 pin 37
NET "RNW" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6847 pin 38
NET "Sync" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6847 pin 39
NET "Rdy" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6847 pin 40
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
NET "nsw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
# I/O's for test connector
#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
# NET "" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6847 pin 12
# NET "" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6847 pin 13
# NET "" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6847 pin 14
# NET "" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6847 pin 15
# NET "" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6847 pin 16
# NET "" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6847 pin 18
# NET "" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6847 pin 19
# NET "" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6847 pin 20
# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8

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----------------------------------------------------------------------------------
-- Company: OHO-Elektronik
-- Engineer: Michael Randelzhofer mr@oho-elektronik.de +491776116444
--
-- Create Date: 10.11.2008
-- Design Name:
-- Module Name: OhoPack.vhd
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.00 - File Created
-- Revision 1.01 - Brightness support
-- Revision 1.02 - Added display test
-- Revision 1.03 - display update support, new interface signal names
-- Additional Comments:
-- package for OHO_DY1 display module
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.NUMERIC_STD.ALL ;
package OhoPack is
type y2d_type is array(14 downto 0) of std_logic_vector(8 downto 0) ;
-- OHO_DY1 hex decodes for positions (7 downto 0) -> edgacpbf
constant seg_a: std_logic_vector(7 downto 0) := X"10" ;
constant seg_b: std_logic_vector(7 downto 0) := X"02" ;
constant seg_c: std_logic_vector(7 downto 0) := X"08" ;
constant seg_d: std_logic_vector(7 downto 0) := X"40" ;
constant seg_e: std_logic_vector(7 downto 0) := X"80" ;
constant seg_f: std_logic_vector(7 downto 0) := X"01" ;
constant seg_g: std_logic_vector(7 downto 0) := X"20" ;
constant seg_dp: std_logic_vector(7 downto 0) := X"04" ;
-- hex decoder shift values
constant H0x0: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_c or seg_d or seg_e or seg_f ;
constant H0x1: std_logic_vector(7 downto 0) := seg_b or seg_c ;
constant H0x2: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_g or seg_e or seg_d ;
constant H0x3: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_c or seg_d or seg_g ;
constant H0x4: std_logic_vector(7 downto 0) := seg_f or seg_g or seg_b or seg_c ;
constant H0x5: std_logic_vector(7 downto 0) := seg_a or seg_f or seg_g or seg_c or seg_d ;
constant H0x6: std_logic_vector(7 downto 0) := seg_a or seg_f or seg_g or seg_c or seg_d or seg_e ;
constant H0x7: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_c ;
constant H0x8: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_c or seg_d or seg_e or seg_f or seg_g ;
constant H0x9: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_c or seg_d or seg_f or seg_g ;
constant H0xa: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_c or seg_e or seg_f or seg_g ;
constant H0xb: std_logic_vector(7 downto 0) := seg_c or seg_d or seg_e or seg_f or seg_g ;
constant H0xc: std_logic_vector(7 downto 0) := seg_a or seg_f or seg_e or seg_d ;
constant H0xd: std_logic_vector(7 downto 0) := seg_b or seg_c or seg_d or seg_e or seg_g ;
constant H0xe: std_logic_vector(7 downto 0) := seg_a or seg_f or seg_g or seg_e or seg_d ;
constant H0xf: std_logic_vector(7 downto 0) := seg_a or seg_f or seg_g or seg_e ;
constant L_a: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_c or seg_e or seg_f or seg_g ;
constant L_b: std_logic_vector(7 downto 0) := seg_c or seg_d or seg_e or seg_f or seg_g ;
constant L_c: std_logic_vector(7 downto 0) := seg_a or seg_f or seg_e or seg_d ;
constant L_d: std_logic_vector(7 downto 0) := seg_b or seg_c or seg_d or seg_e or seg_g ;
constant L_e: std_logic_vector(7 downto 0) := seg_a or seg_g or seg_d or seg_e or seg_f ;
constant L_f: std_logic_vector(7 downto 0) := seg_a or seg_f or seg_g or seg_e ;
constant L_g: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_c or seg_d or seg_f or seg_g ;
constant L_h: std_logic_vector(7 downto 0) := seg_c or seg_e or seg_g or seg_f ;
constant L_hh: std_logic_vector(7 downto 0) := seg_b or seg_c or seg_e or seg_f or seg_g ;
constant L_i: std_logic_vector(7 downto 0) := seg_b or seg_c ;
constant L_j: std_logic_vector(7 downto 0) := seg_b or seg_c or seg_d ;
constant L_l: std_logic_vector(7 downto 0) := seg_d or seg_e or seg_f ;
constant L_n: std_logic_vector(7 downto 0) := seg_c or seg_e or seg_g ;
constant L_o: std_logic_vector(7 downto 0) := seg_c or seg_d or seg_e or seg_g ;
constant L_oo: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_c or seg_d or seg_e or seg_f ;
constant L_p: std_logic_vector(7 downto 0) := seg_a or seg_b or seg_g or seg_f or seg_e ;
constant L_r: std_logic_vector(7 downto 0) := seg_e or seg_g ;
constant L_s: std_logic_vector(7 downto 0) := seg_a or seg_f or seg_g or seg_c or seg_d ;
constant L_t: std_logic_vector(7 downto 0) := seg_f or seg_e or seg_g or seg_d ;
constant L_u: std_logic_vector(7 downto 0) := seg_b or seg_c or seg_d or seg_e or seg_f ;
constant L_v: std_logic_vector(7 downto 0) := seg_c or seg_d or seg_e ;
constant L_x: std_logic_vector(7 downto 0) := seg_c or seg_f or seg_g ;
constant L_y: std_logic_vector(7 downto 0) := seg_b or seg_c or seg_d or seg_g or seg_f ;
constant hex: std_logic := '1' ;
constant raw: std_logic := '0' ;
constant DupVal: std_logic_vector(11 DOWNTO 0) := X"001" ;
FUNCTION Rise(sig:std_logic; sigq:std_logic) return boolean ;
FUNCTION Fall(sig:std_logic; sigq:std_logic) return boolean ;
FUNCTION ShiftBit(bitshift:std_logic_vector(2 downto 0); shiftval:std_logic_vector(7 downto 0)) return std_logic ;
FUNCTION SerialHexDecode(bitpos:std_logic_vector(2 downto 0); ledcode:std_logic_vector(8 downto 0)) return std_logic ;
FUNCTION Mirror(slv:std_logic_vector) return std_logic_vector ;
end OhoPack ;
package body OhoPack is
-- generate one clock pulse on rising edge of signal sig
FUNCTION Rise(sig:std_logic; sigq:std_logic) return boolean is
VARIABLE Z : boolean ;
BEGIN
if (sig and not sigq) = '1' then
Z := true ;
else
Z := false ;
end if ;
RETURN Z ;
END Rise ;
-- generate one clock pulse on falling edge of signal sig
FUNCTION Fall(sig:std_logic; sigq:std_logic) return boolean is
VARIABLE Z : boolean ;
BEGIN
if (not sig and sigq) = '1' then
Z := true ;
else
Z := false ;
end if ;
RETURN Z ;
END Fall ;
-- serial bit decoder for bit positions
-- bitshiftposition=0 -> result=shiftval(7)
-- bitshiftposition=1 -> result=shiftval(6)
-- bitshiftposition=2 -> result=shiftval(5)
-- bitshiftposition=3 -> result=shiftval(4)
-- bitshiftposition=4 -> result=shiftval(3)
-- bitshiftposition=5 -> result=shiftval(2)
-- bitshiftposition=6 -> result=shiftval(1)
-- bitshiftposition=7 -> result=shiftval(0)
FUNCTION ShiftBit(bitshift:std_logic_vector(2 downto 0); shiftval:std_logic_vector(7 downto 0)) return std_logic is
VARIABLE Z : std_logic ;
VARIABLE mv : std_logic_vector(7 downto 0) ;
BEGIN
mv := Mirror(shiftval) ;
Z := mv(to_integer(unsigned(bitshift))) ;
RETURN Z ;
END ShiftBit ;
-- lookup table driven hex decoder, needs binary up counter on bitpos
-- input digit data is 9bits: ledcode(8 downto 0)
-- ledcode(8)=0 -> ledcode(7 downto 0)=LED raw data; use led constants defined in this package
-- ledcode(8)=1 -> ledcode(3 downto 0)=display hex nibble; ledcode(7)=decimal point
FUNCTION SerialHexDecode(bitpos:std_logic_vector(2 downto 0); ledcode:std_logic_vector(8 downto 0)) return std_logic is
VARIABLE Z : std_logic ;
VARIABLE hexval : std_logic_vector(3 downto 0) ;
VARIABLE dp : std_logic_vector(7 downto 0) ;
BEGIN
hexval := ledcode(3 downto 0) ;
if (ledcode(7)='0') then
dp := (others => '0') ;
else
dp := seg_dp ;
end if ;
if (ledcode(8)='0') then
Z := ShiftBit(bitpos,ledcode(7 downto 0)) ;
else
case hexval is
when X"0" => Z := ShiftBit(bitpos,H0x0 or dp) ;
when X"1" => Z := ShiftBit(bitpos,H0x1 or dp) ;
when X"2" => Z := ShiftBit(bitpos,H0x2 or dp) ;
when X"3" => Z := ShiftBit(bitpos,H0x3 or dp) ;
when X"4" => Z := ShiftBit(bitpos,H0x4 or dp) ;
when X"5" => Z := ShiftBit(bitpos,H0x5 or dp) ;
when X"6" => Z := ShiftBit(bitpos,H0x6 or dp) ;
when X"7" => Z := ShiftBit(bitpos,H0x7 or dp) ;
when X"8" => Z := ShiftBit(bitpos,H0x8 or dp) ;
when X"9" => Z := ShiftBit(bitpos,H0x9 or dp) ;
when X"a" => Z := ShiftBit(bitpos,H0xa or dp) ;
when X"b" => Z := ShiftBit(bitpos,H0xb or dp) ;
when X"c" => Z := ShiftBit(bitpos,H0xc or dp) ;
when X"d" => Z := ShiftBit(bitpos,H0xd or dp) ;
when X"e" => Z := ShiftBit(bitpos,H0xe or dp) ;
when X"f" => Z := ShiftBit(bitpos,H0xf or dp) ;
when others =>
end case ;
end if ;
RETURN Z ;
END SerialHexDecode ;
--this function mirrors all the bits of the input vector
FUNCTION Mirror(slv:std_logic_vector) return std_logic_vector is
VARIABLE MIR : std_logic_vector(slv'high downto slv'low);
BEGIN
FOR i IN (slv'low) to slv'high LOOP
MIR(i) := (slv(slv'high-i)) ;
END LOOP ;
RETURN MIR ;
END Mirror ;
end OHOPack ;

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----------------------------------------------------------------------------------
-- Company: OHO-Elektronik
-- Engineer: M.Randelzhofer
--
-- Create Date: 20:55:43 02/02/2009
-- Design Name:
-- Module Name: Oho_Dy1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.00 - File Created
-- Revision 1.01 - Brightness support
-- Revision 1.02 - Added display test
-- Revision 1.03 - display update support, new interface signal names
-- Additional Comments:
-- Dispay module OHO_DY1 core
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
use work.OhoPack.all ;
entity Oho_Dy1 is
Port (
dy_clock: in std_logic ;
dy_rst_n: in std_logic ;
dy_data: in y2d_type ;
dy_update: in std_logic ;
dy_frame: out std_logic ;
dy_frameend: out std_logic ;
dy_frameend_c: out std_logic ;
dy_pwm: in std_logic_vector(3 downto 0) ;
dy_counter: out std_logic_vector(31 downto 0) ;
dy_sclk: out std_logic ;
dy_ser: out std_logic ;
dy_rclk: out std_logic
) ;
end Oho_Dy1 ;
-- display core for OHO_DY1 module
architecture Behavioral of Oho_Dy1 is
signal sclk: std_logic ;
signal ser: std_logic ;
signal rclk: std_logic ;
signal frameend: std_logic ;
signal frameend_q: std_logic ;
signal frameend_c: std_logic ;
signal frame: std_logic ;
signal actualdigit: std_logic_vector (8 downto 0) ;
signal dupcnt: std_logic_vector (11 downto 0) ;
signal displaycounter: std_logic_vector (31 downto 0) ;
begin
-- display up to 15 digits on 5 stacked OHO_DY1 modules
Display_Proc: process(dy_clock,dy_rst_n)
begin
if (dy_rst_n = '0') then
-- init signals on reset
displaycounter <= (others => '0') ;
dupcnt <= (others => '0') ;
frame <= '0' ;
frameend <= '1' ;
frameend_q <= '1' ;
frameend_c <= '0' ;
sclk <= '0' ;
ser <= '0' ;
rclk <= '1' ;
elsif rising_edge(dy_clock) then
-- use a free running binary counter as a timing source
displaycounter <= std_logic_vector(unsigned(displaycounter) + 1) ;
-- start of display frame
-- generate frame and rising edge of rclk
if (displaycounter(15 downto 0) = X"0000") then
-- decrease display update counter dupcnt
if (dupcnt /= X"000") then
dupcnt <= std_logic_vector(unsigned(dupcnt) - 1) ;
frame <= '1' ; -- indicate start of display frame
frameend <= '0' ; -- inactivate frameend
else
frame <= '0' ; -- indicate end of sclk/ser, rclk still active
end if ;
-- generate rclk rising edge
if (frame = '1') then
rclk <= '1' ;
end if ;
else
-- remaining display frame
if (frame = '0') then
-- display frame end, set rclk low on next sclk rising
if (displaycounter(8) = '1') then
rclk <= '0' ;
frameend <= '1' ;
end if ;
else
-- display frame continues with PWM brightness control
if (displaycounter(15 downto 12) = not dy_pwm) and (displaycounter(8) = '1') then
rclk <= '0' ;
end if ;
end if ;
end if ;
-- setup display update counter (must be after dupcnt-1 statement)
if (dy_update = '1') then -- display update
dupcnt <= DupVal ;
end if ;
-- use dy_clock/256 as shift register clock
sclk <= frame and displaycounter(8) ;
-- feed display data from function SerialHexDecode in OhoPack.vhd
ser <= frame and not SerialHexDecode(displaycounter(11 downto 9),actualdigit) ;
-- digit data 16:1 mux
case displaycounter(15 downto 12) is
-- first shift out 16. digit, normally not used
when "0000" => actualdigit <= "000000000" ; -- blank
-- 15. digit is on the 5.th stacked module on the left side
when "0001" => actualdigit <= dy_data(14) ;
-- 14. digit is on the 5.th stacked module in the middle
when "0010" => actualdigit <= dy_data(13) ;
-- 13. digit is on the 5.th stacked module on the right side
when "0011" => actualdigit <= dy_data(12) ;
when "0100" => actualdigit <= dy_data(11) ;
when "0101" => actualdigit <= dy_data(10) ;
when "0110" => actualdigit <= dy_data(9) ;
when "0111" => actualdigit <= dy_data(8) ;
when "1000" => actualdigit <= dy_data(7) ;
when "1001" => actualdigit <= dy_data(6) ;
when "1010" => actualdigit <= dy_data(5) ;
when "1011" => actualdigit <= dy_data(4) ;
when "1100" => actualdigit <= dy_data(3) ;
when "1101" => actualdigit <= dy_data(2) ;
when "1110" => actualdigit <= dy_data(1) ;
-- first digit on the first module on the right side
when "1111" => actualdigit <= dy_data(0) ;
when others =>
end case ;
-- generate single frameend clock pulse
frameend_q <= frameend ;
if Rise(frameend,frameend_q) then
frameend_c <= '1' ;
else
frameend_c <= '0' ;
end if ;
-- use output registers for the display signals
dy_sclk <= sclk ;
dy_ser <= ser ;
dy_rclk <= rclk ;
end if ;
end process ;
-- making internal signals externally available
dy_counter <= displaycounter ;
dy_frame <= frame ;
dy_frameend <= frameend_q ;
dy_frameend_c <= frameend_c ;
end Behavioral;