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Fixed AlanD core 65C02 bugs: D was being set in IRQ/BRK; sync was inferring a latch

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Change-Id: Ia7163e996c403a1caae04df10de3d7a42a91b45c
This commit is contained in:
David Banks 2015-11-11 13:07:19 +00:00
parent 6aeb0c7b8a
commit 568fd2906d
1 changed files with 1 additions and 1 deletions
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src/AlanD/R65Cx2.vhd
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@ -658,7 +658,7 @@ processAluInput: process(clk, opcInfo, A, X, Y, T, S)
temp := temp and T;
end if;
if opcInfo(opcInBrk) = '1' then
temp := temp and "11101111";
temp := temp and "11100111"; -- also DMB clear D (bit 3)
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');