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6502: Hack, use an internal 1MHz signal instead of Phi0

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Change-Id: I4802cc19004795bbabc9f0e81053612b31affdfb
This commit is contained in:
David Banks 2020-01-27 20:37:05 +00:00
parent 50a86721e4
commit 85dbcb8732
1 changed files with 20 additions and 2 deletions
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22
src/MOS6502CpuMonALS.vhd
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@ -104,8 +104,26 @@ architecture behavioral of MOS6502CpuMonALS is
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal int_Phi0_div : unsigned(4 downto 0); -- internal Phi0 clock divider
signal int_Phi0 : std_logic; -- internal Phi0 clock
begin
-- Hack to use an internal 1MHz clock instead of Phi0
-- from the 50MHz clock on the EEPIZZA board
process(clock)
begin
if rising_edge(clock) then
if int_Phi0_div = 24 then
int_Phi0 <= not int_Phi0; -- toggle int_Phi2 every 25 cycles
int_Phi0_div <= (others => '0');
else
int_Phi0_div <= int_Phi0_div + 1;
end if;
end if;
end process;
sw_reset_cpu <= not sw1;
sw_reset_avr <= not sw2;
led1 <= led_bkpt;
@ -126,7 +144,7 @@ begin
clock => clock,
-- 6502 Signals
Phi0 => PhiIn,
Phi0 => int_Phi0, -- hack to use internal Phi0
Phi1 => Phi1Out,
Phi2 => Phi2Out,
IRQ_n => IRQ_n,
@ -175,7 +193,7 @@ begin
OERW_n <= not (BE);
OEAH_n <= not (BE);
OEAL_n <= not (BE);
OED_n <= not (BE and PhiIn); -- TODO: might need to use a slightly delayed version of Phi2 here
OED_n <= not (BE and int_Phi0); -- hack to use interal Phi0
DIRD <= R_W_n_int;
end behavioral;