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All: rename switches to represent their real function

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Change-Id: I6dd61b8b7165e617363d61df5194e35c1a9dcc92
This commit is contained in:
David Banks 2019-11-04 09:31:56 +00:00
parent 663aac5198
commit 8724119101
14 changed files with 76 additions and 76 deletions
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12
src/BusMonCore.vhd
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@ -85,8 +85,8 @@ entity BusMonCore is
avr_TxD : out std_logic;
-- Switches
sw_interrupt : in std_logic;
sw_reset : in std_logic;
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
@ -226,7 +226,7 @@ begin
portdin(3) => '0',
portdin(4) => '0',
portdin(5) => '0',
portdin(6) => '0', -- sw_interrupt,
portdin(6) => '0',
portdin(7) => fifo_empty_n,
portdout(0) => muxsel(0),
@ -275,12 +275,12 @@ begin
led_trig1 <= trig(1);
led_bkpt <= brkpt_active;
nrst_avr <= not sw_reset;
nrst_avr <= not sw_reset_avr;
-- OHO DY1 Display for Testing
dy_data(0) <= hex & "0000" & Addr(3 downto 0);
dy_data(1) <= hex & "0000" & Addr(7 downto 4);
dy_data(2) <= hex & "0000" & "00" & sw_reset & sw_interrupt;
dy_data(2) <= hex & "0000" & "00" & sw_reset_avr & sw_reset_cpu;
mux <= addr_inst(7 downto 0) when muxsel = 0 else
addr_inst(15 downto 8) when muxsel = 1 else
@ -568,7 +568,7 @@ begin
begin
if rising_edge(clock_avr) then
-- Syncronise nRSTin
nrst1 <= nRSTin and (not sw_interrupt);
nrst1 <= nRSTin and (not sw_reset_cpu);
-- De-glitch NRST
if nrst1 = '0' then
nrst_counter <= to_unsigned(0, nrst_counter'length);

8
src/MC6809CpuMon.vhd
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@ -67,8 +67,8 @@ entity MC6809CpuMon is
avr_TxD : out std_logic;
-- Switches
sw_interrupt : in std_logic;
sw_reset : in std_logic;
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
@ -190,8 +190,8 @@ begin
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,

12
src/MC6809CpuMonALS.vhd
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@ -83,16 +83,16 @@ architecture behavioral of MC6809CpuMonALS is
signal R_W_n_int : std_logic;
signal sw_interrupt : std_logic;
signal sw_reset : std_logic;
signal sw_reset_cpu : std_logic;
signal sw_reset_avr : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
begin
sw_interrupt <= not sw1;
sw_reset <= not sw2;
sw_reset_cpu <= not sw1;
sw_reset_avr <= not sw2;
led1 <= led_bkpt;
led2 <= led_trig0;
led3 <= led_trig1;
@ -144,8 +144,8 @@ begin
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,

12
src/MC6809CpuMonGODIL.vhd
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@ -95,8 +95,8 @@ architecture behavioral of MC6809CpuMonGODIL is
signal clock7_3728 : std_logic;
signal sw_reset : std_logic;
signal sw_interrupt : std_logic;
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
@ -116,8 +116,8 @@ architecture behavioral of MC6809CpuMonGODIL is
begin
-- Generics allows polarity of switches/LEDs to be tweaked from the project file
sw_interrupt <= sw1;
sw_reset <= not sw2;
sw_reset_cpu <= sw1;
sw_reset_avr <= not sw2;
led3 <= not led_trig0;
led6 <= not led_trig1;
led8 <= not led_bkpt;
@ -169,8 +169,8 @@ begin
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,

12
src/MC6809CpuMonLX9.vhd
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@ -95,8 +95,8 @@ architecture behavioral of MC6809CpuMonLX9 is
signal clock7_3728 : std_logic;
signal sw_reset : std_logic;
signal sw_interrupt : std_logic;
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
@ -115,8 +115,8 @@ architecture behavioral of MC6809CpuMonLX9 is
begin
sw_interrupt <= sw1;
sw_reset <= sw2;
sw_reset_cpu <= sw1;
sw_reset_avr <= sw2;
led3 <= led_trig0;
led6 <= led_trig1;
led8 <= led_bkpt;
@ -168,8 +168,8 @@ begin
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,

8
src/MOS6502CpuMon.vhd
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@ -58,8 +58,8 @@ entity MOS6502CpuMon is
avr_TxD : out std_logic;
-- Switches
sw_interrupt : in std_logic;
sw_reset : in std_logic;
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
@ -134,8 +134,8 @@ begin
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,

12
src/MOS6502CpuMonALS.vhd
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@ -98,16 +98,16 @@ architecture behavioral of MOS6502CpuMonALS is
signal R_W_n_int : std_logic;
signal sw_interrupt : std_logic;
signal sw_reset : std_logic;
signal sw_reset_cpu : std_logic;
signal sw_reset_avr : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
begin
sw_interrupt <= not sw1;
sw_reset <= not sw2;
sw_reset_cpu <= not sw1;
sw_reset_avr <= not sw2;
led1 <= led_bkpt;
led2 <= led_trig0;
led3 <= led_trig1;
@ -150,8 +150,8 @@ begin
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,

8
src/MOS6502CpuMonCore.vhd
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@ -56,8 +56,8 @@ entity MOS6502CpuMonCore is
avr_TxD : out std_logic;
-- Switches
sw_interrupt : in std_logic;
sw_reset : in std_logic;
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
@ -138,8 +138,8 @@ begin
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,

12
src/MOS6502CpuMonGODIL.vhd
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@ -74,16 +74,16 @@ end MOS6502CpuMonGODIL;
architecture behavioral of MOS6502CpuMonGODIL is
signal sw_interrupt : std_logic;
signal sw_reset : std_logic;
signal sw_reset_cpu : std_logic;
signal sw_reset_avr : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
begin
sw_interrupt <= sw1;
sw_reset <= not sw2;
sw_reset_cpu <= sw1;
sw_reset_avr <= not sw2;
led8 <= not led_bkpt;
led3 <= not led_trig0;
led6 <= not led_trig1;
@ -126,8 +126,8 @@ begin
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,

12
src/MOS6502CpuMonLX9.vhd
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@ -74,16 +74,16 @@ end MOS6502CpuMonLX9;
architecture behavioral of MOS6502CpuMonLX9 is
signal sw_interrupt : std_logic;
signal sw_reset : std_logic;
signal sw_reset_cpu : std_logic;
signal sw_reset_avr : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
begin
sw_interrupt <= sw1;
sw_reset <= sw2;
sw_reset_cpu <= sw1;
sw_reset_avr <= sw2;
led8 <= led_bkpt;
led3 <= led_trig0;
led6 <= led_trig1;
@ -126,8 +126,8 @@ begin
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,

8
src/Z80CpuMon.vhd
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@ -64,8 +64,8 @@ entity Z80CpuMon is
avr_TxD : out std_logic;
-- Switches
sw_interrupt : in std_logic;
sw_reset : in std_logic;
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
@ -231,8 +231,8 @@ begin
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD_int,
sw_interrupt => '0',
sw_reset => sw_reset,
sw_reset_cpu => '0',
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,

12
src/Z80CpuMonALS.vhd
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@ -96,16 +96,16 @@ architecture behavioral of Z80CpuMonALS is
signal BUSAK_n_int : std_logic;
signal tristate_n : std_logic;
signal sw_interrupt : std_logic;
signal sw_reset : std_logic;
signal sw_reset_cpu : std_logic;
signal sw_reset_avr : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
begin
sw_interrupt <= not sw1;
sw_reset <= not sw2;
sw_reset_cpu <= not sw1;
sw_reset_avr <= not sw2;
led1 <= led_bkpt;
led2 <= led_trig0;
led3 <= led_trig1;
@ -168,8 +168,8 @@ begin
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,

12
src/Z80CpuMonGODIL.vhd
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@ -81,8 +81,8 @@ end Z80CpuMonGODIL;
architecture behavioral of Z80CpuMonGODIL is
signal sw_reset : std_logic;
signal sw_interrupt : std_logic;
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
@ -96,8 +96,8 @@ architecture behavioral of Z80CpuMonGODIL is
signal tristate_n : std_logic;
begin
sw_interrupt <= sw1;
sw_reset <= not sw2;
sw_reset_cpu <= sw1;
sw_reset_avr <= not sw2;
led3 <= not led_trig0;
led6 <= not led_trig1;
led8 <= not led_bkpt;
@ -153,8 +153,8 @@ begin
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,

12
src/Z80CpuMonLX9.vhd
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@ -81,8 +81,8 @@ end Z80CpuMonLX9;
architecture behavioral of Z80CpuMonLX9 is
signal sw_reset : std_logic;
signal sw_interrupt : std_logic;
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
@ -97,8 +97,8 @@ architecture behavioral of Z80CpuMonLX9 is
begin
sw_interrupt <= sw1;
sw_reset <= sw2;
sw_reset_cpu <= sw1;
sw_reset_avr <= sw2;
led3 <= led_trig0;
led6 <= led_trig1;
led8 <= led_bkpt;
@ -154,8 +154,8 @@ begin
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,