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Experimental AtomFast6502 with a different clocking arrangement

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Change-Id: Ic6f5275bc0982254e9b5508ec79f0365712657de
This commit is contained in:
David Banks 2015-09-23 14:56:31 +01:00
parent d3224a651d
commit 92177196c0
4 changed files with 769 additions and 0 deletions
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<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomFast6502" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AtomFast6502" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-14T13:18:08" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="94463E018478C2B4E24AE2AD62D55F9D" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

78
src/AtomFast6502.ucf Normal file
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NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 4
#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 6
NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 | PERIOD = 500.0 ; # 6502 pin 37
NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
NET "nsw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
# I/O's for test connector
NET test<0> LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET test<1> LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET test<2> LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET test<3> LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET test<4> LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET test<5> LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET test<6> LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ;
# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8

254
src/AtomFast6502.vhd Normal file
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--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomBusMon.vhd
-- /___/ /\ Timestamp : 30/05/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomBusMon
--Device: XC3S250E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.OhoPack.all ;
entity AtomFast6502 is
generic (
UseT65Core : boolean := true;
UseAlanDCore : boolean := false
);
port (
clock49 : in std_logic;
-- 6502 Signals
Rdy : in std_logic;
Phi0 : in std_logic;
Phi1 : out std_logic;
Phi2 : out std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic;
Data : inout std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : inout std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Jumpers
fakeTube_n : in std_logic;
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- GODIL Switches
sw1 : in std_logic;
nsw2 : in std_logic;
-- GODIL LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
test : out std_logic_vector(6 downto 0)
);
end AtomFast6502;
architecture behavioral of AtomFast6502 is
signal Din : std_logic_vector(7 downto 0);
signal Dout : std_logic_vector(7 downto 0);
-- Signal from the internal core
signal Dout0 : std_logic_vector(7 downto 0);
signal Addr0 : std_logic_vector(15 downto 0);
signal R_W_n0 : std_logic;
signal Sync0 : std_logic;
-- Delayed signals for the outside world
signal Dout1 : std_logic_vector(7 downto 0);
signal Addr1 : std_logic_vector(15 downto 0);
signal R_W_n1 : std_logic;
signal Sync1 : std_logic;
signal cpu_addr_us: unsigned (15 downto 0);
signal cpu_dout_us: unsigned (7 downto 0);
signal clock_16x : std_logic;
signal cpu_clk : std_logic;
signal R_W_n_int : std_logic;
signal cpu_clken : std_logic;
signal cpu_dataen : std_logic;
signal clk_div : std_logic_vector(3 downto 0);
signal Phi1_int : std_logic;
signal Phi2_int : std_logic;
signal dcm_reset : std_logic;
signal dcm_count : std_logic_vector(9 downto 0);
signal dcm_locked : std_logic;
signal edge0 : std_logic;
signal edge1 : std_logic;
begin
GenT65Core: if UseT65Core generate
inst_t65: entity work.T65 port map (
mode => "00",
Abort_n => '1',
SO_n => SO_n,
Res_n => Res_n,
Enable => cpu_clken,
Clk => clock_16x,
Rdy => Rdy,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
R_W_n => R_W_n0,
Sync => Sync0,
A(23 downto 16) => open,
A(15 downto 0) => Addr0,
DI => Din,
DO => Dout0,
Regs => open
);
end generate;
GenAlanDCore: if UseAlanDCore generate
inst_r65c02: entity work.r65c02 port map (
reset => RES_n,
clk => clock_16x,
enable => cpu_clken,
nmi_n => NMI_n,
irq_n => IRQ_n,
di => unsigned(Din),
do => cpu_dout_us,
addr => cpu_addr_us,
nwe => R_W_n0,
sync => Sync0,
sync_irq => open,
Regs => open
);
Dout0 <= std_logic_vector(cpu_dout_us);
Addr0 <= std_logic_vector(cpu_addr_us);
end generate;
inst_dcm2 : entity work.DCM2 port map(
CLKIN_IN => Phi0,
CLKFX_OUT => clock_16x,
LOCKED => dcm_locked,
RESET => dcm_reset
);
process(clock49)
begin
if rising_edge(clock49) then
edge0 <= clk_div(0);
edge1 <= edge0;
-- Look for an edge on the clock
if (edge0 /= edge1) then
dcm_count <= (others => '0');
elsif (dcm_count = "1111001111") then
dcm_reset <= '0';
elsif (dcm_count = "1000000000") then
dcm_reset <= '1';
dcm_count <= dcm_count + 1;
else
dcm_count <= dcm_count + 1;
end if;
end if;
end process;
-- -- for some reason this did not work reliably....
-- process(clock49)
-- begin
-- if rising_edge(clock49) then
-- edge0 <= dcm_locked;
-- edge1 <= edge0;
-- if (dcm_count = "0000000000") then
-- dcm_reset <= '0';
-- if (edge0 = '0' and edge1 = '1') then
-- dcm_count <= dcm_count + 1;
-- end if;
-- else
-- dcm_reset <= '1';
-- dcm_count <= dcm_count + 1;
-- end if;
-- end if;
-- end process;
process(clock_16x)
begin
if rising_edge(clock_16x) then
-- internal clock running 16x Phi0
clk_div <= clk_div + 1;
-- clock the CPU on cycle 0
if (clk_div = "1111") then
cpu_clken <= '1';
else
cpu_clken <= '0';
end if;
-- toggle Phi1/2 on cycles 0 and 8
if (clk_div = "0000") then
Phi1_int <= '1';
Phi2_int <= '0';
elsif (clk_div = "1000") then
Phi1_int <= '0';
Phi2_int <= '1';
end if;
-- Skew address by one cycles, and hold for a complete cycle
if (clk_div = "0001") then
Addr1 <= Addr0;
R_W_n1 <= R_W_n0;
Sync1 <= Sync0;
end if;
-- Skew data by one cycle
if (clk_div = "1011") then
cpu_dataen <= not R_W_n0;
Dout1 <= Dout0;
elsif (clk_div = "0001") then
cpu_dataen <= '0';
Dout1 <= (others => '1');
end if;
end if;
end process;
Phi1 <= Phi1_int;
Phi2 <= Phi2_int;
Din <= Data;
Addr <= Addr1;
R_W_n <= R_W_n1;
Sync <= Sync1;
Data <= Dout1 when cpu_dataen = '1' else "ZZZZZZZZ";
led3 <= '1';
led6 <= '1';
led8 <= '1';
avr_TxD <= '1';
test(0) <= clock_16x;
test(1) <= Phi1_int;
test(2) <= Phi2_int;
test(3) <= dcm_locked;
test(4) <= dcm_reset;
test(5) <= R_W_n1;
test(6) <= '1';
end behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM2 is
port (CLKIN_IN : in std_logic;
RESET : in std_logic;
CLKFX_OUT : out std_logic;
LOCKED : out std_logic);
end DCM2;
architecture BEHAVIORAL of DCM2 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLKFX_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 16,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 1000.00,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => RESET,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => LOCKED,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;