6809: seperate top level for GODIL and old LX9

Change-Id: I4a7d2a67c8aeaabc25d2987edb4a9026e92b1efc

src/MC6809CpuMon.vhd

@@ -21,14 +21,13 @@ use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 use work.OhoPack.all ;
 
-entity MC6809CpuMonCore is
+entity MC6809CpuMon is
     generic (
-       UseCPU09Core      : boolean := true;
-       ClkMult           : integer := 10;       -- default value correct for GODIL
-       ClkDiv            : integer := 31;       -- default value correct for GODIL
-       ClkPer            : real    := 20.345;   -- default value correct for GODIL
-       num_comparators   : integer := 8;        -- default value correct for GODIL
-       avr_prog_mem_size : integer := 1024 * 9  -- default value correct for GODIL
+       ClkMult           : integer;
+       ClkDiv            : integer;
+       ClkPer            : real;
+       num_comparators   : integer;
+       avr_prog_mem_size : integer
        );
     port (
         -- Fast clock
@@ -86,9 +85,9 @@ entity MC6809CpuMonCore is
         test2           : out   std_logic
 
     );
-end MC6809CpuMonCore;
+end MC6809CpuMon;
 
-architecture behavioral of MC6809CpuMonCore is
+architecture behavioral of MC6809CpuMon is
 
     signal clock_avr      : std_logic;
 
@@ -251,28 +250,26 @@ begin
     Regs1(111 downto  96) <= Regs(111 downto  96);
     Regs1(255 downto 112) <= (others => '0');
 
-    GenCPU09Core: if UseCPU09Core generate
-        inst_cpu09: entity work.cpu09 port map (
-            clk      => cpu_clk,
-            rst      => not nRST_sync,
-            vma      => AVMA,
-            lic_out  => LIC_int,
-            ifetch   => ifetch,
-            opfetch  => open,
-            ba       => BA,
-            bs       => BS,
-            addr     => Addr_int,
-            rw       => R_W_n_int,
-            data_out => Dout,
-            data_in  => Din,
-            irq      => IRQ_sync,
-            firq     => FIRQ_sync,
-            nmi      => NMI_sync,
-            halt     => HALT_sync,
-            hold     => hold,
-            Regs     => Regs
+    inst_cpu09: entity work.cpu09 port map (
+        clk      => cpu_clk,
+        rst      => not nRST_sync,
+        vma      => AVMA,
+        lic_out  => LIC_int,
+        ifetch   => ifetch,
+        opfetch  => open,
+        ba       => BA,
+        bs       => BS,
+        addr     => Addr_int,
+        rw       => R_W_n_int,
+        data_out => Dout,
+        data_in  => Din,
+        irq      => IRQ_sync,
+        firq     => FIRQ_sync,
+        nmi      => NMI_sync,
+        halt     => HALT_sync,
+        hold     => hold,
+        Regs     => Regs
         );
-    end generate;
 
 
     -- Synchronize all external inputs, to avoid subtle bugs like missed interrupts

src/MC6809CpuMonALS.vhd

@@ -22,9 +22,6 @@ use ieee.numeric_std.all;
 
 entity MC6809CpuMonALS is
     generic (
-       ClkMult           : integer := 8;        -- default value correct for ALS
-       ClkDiv            : integer := 25;       -- default value correct for ALS
-       ClkPer            : real    := 20.0;     -- default value correct for ALS
        num_comparators   : integer := 8;        -- default value correct for ALS
        avr_prog_mem_size : integer := 1024 * 9  -- default value correct for ALS
        );
@@ -93,12 +90,11 @@ begin
     sw_reset <= not sw_reset_n;
     sw_interrupt <= not sw_interrupt_n;
 
-    wrapper : entity work.MC6809CpuMonCore
+    wrapper : entity work.MC6809CpuMon
       generic map (
-          UseCPU09Core      => true,
-          ClkMult           => ClkMult,
-          ClkDiv            => ClkDiv,
-          ClkPer            => ClkPer,
+          ClkMult           => 8,
+          ClkDiv            => 25,
+          ClkPer            => 20.000,
           num_comparators   => num_comparators,
           avr_prog_mem_size => avr_prog_mem_size
       )

src/MC6809CpuMonGODIL.vhd

@@ -22,12 +22,6 @@ use ieee.numeric_std.all;
 
 entity MC6809CpuMonGODIL is
     generic (
-       LEDsActiveHigh    : boolean := false;    -- default value correct for GODIL
-       SW1ActiveHigh     : boolean := true;     -- default value correct for GODIL
-       SW2ActiveHigh     : boolean := false;    -- default value correct for GODIL
-       ClkMult           : integer := 10;       -- default value correct for GODIL
-       ClkDiv            : integer := 31;       -- default value correct for GODIL
-       ClkPer            : real    := 20.345;   -- default value correct for GODIL
        num_comparators   : integer := 8;        -- default value correct for GODIL
        avr_prog_mem_size : integer := 1024 * 9  -- default value correct for GODIL
        );
@@ -122,18 +116,17 @@ architecture behavioral of MC6809CpuMonGODIL is
 begin
 
     -- Generics allows polarity of switches/LEDs to be tweaked from the project file
-    sw_interrupt <= sw1       when SW1ActiveHigh  else not sw1;
-    sw_reset     <= sw2       when SW2ActiveHigh  else not sw2;
-    led3         <= led_trig0 when LEDsActiveHigh else not led_trig0;
-    led6         <= led_trig1 when LEDsActiveHigh else not led_trig1;
-    led8         <= led_bkpt  when LEDsActiveHigh else not led_bkpt;
+    sw_interrupt <= sw1;
+    sw_reset     <= not sw2;
+    led3         <= not led_trig0;
+    led6         <= not led_trig1;
+    led8         <= not led_bkpt;
 
-    wrapper : entity work.MC6809CpuMonCore
+    wrapper : entity work.MC6809CpuMon
       generic map (
-          UseCPU09Core      => true,
-          ClkMult           => ClkMult,
-          ClkDiv            => ClkDiv,
-          ClkPer            => ClkPer,
+          ClkMult           => 10,
+          ClkDiv            => 31,
+          ClkPer            => 20.345,
           num_comparators   => num_comparators,
           avr_prog_mem_size => avr_prog_mem_size
       )

src/MC6809CpuMonLX9.vhd

@@ -0,0 +1,246 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : MC6808CpuMonLX9.vhd
+-- /___/   /\     Timestamp : 24/10/2019
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: MC6808CpuMonLX9
+--Device: XC3S250E/XC3S500E
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MC6809CpuMonLX9 is
+    generic (
+       num_comparators   : integer := 8;        -- default value correct for LX9
+       avr_prog_mem_size : integer := 1024 * 9  -- default value correct for LX9
+       );
+    port (
+        clock49         : in    std_logic;
+
+        -- A locally generated test clock
+        -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
+        -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
+        clock_test      : out   std_logic;
+
+        -- 6809/6809E mode selection
+        -- Jumper is between pins B1 and D1
+        -- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
+        -- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
+        EMode_n         : in   std_logic;
+
+        --6809 Signals
+        PIN33           : inout std_logic;
+        PIN34           : inout std_logic;
+        PIN35           : inout std_logic;
+        PIN36           : inout std_logic;
+        PIN38           : inout std_logic;
+        PIN39           : in    std_logic;
+
+        -- Signals common to both 6809 and 6809E
+        RES_n           : in    std_logic;
+        NMI_n           : in    std_logic;
+        IRQ_n           : in    std_logic;
+        FIRQ_n          : in    std_logic;
+        HALT_n          : in    std_logic;
+        BS              : out   std_logic;
+        BA              : out   std_logic;
+        R_W_n           : out   std_logic;
+
+        Addr            : out   std_logic_vector(15 downto 0);
+        Data            : inout std_logic_vector(7 downto 0);
+
+        -- External trigger inputs
+        trig            : in    std_logic_vector(1 downto 0);
+
+        -- Serial Console
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
+
+        -- LX9 Switches
+        sw1             : in    std_logic;
+        sw2             : in    std_logic;
+
+        -- LX9 LEDs
+        led3            : out   std_logic;
+        led6            : out   std_logic;
+        led8            : out   std_logic;
+
+        -- OHO_DY1 connected to test connector
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
+
+        -- Debugging signals
+        test1           : out   std_logic;
+        test2           : out   std_logic
+
+    );
+end MC6809CpuMonLX9;
+
+architecture behavioral of MC6809CpuMonLX9 is
+
+    signal clk_count      : std_logic_vector(1 downto 0);
+    signal quadrature     : std_logic_vector(1 downto 0);
+
+    signal clock7_3728    : std_logic;
+
+    signal sw_reset       : std_logic;
+    signal sw_interrupt   : std_logic;
+    signal led_bkpt       : std_logic;
+    signal led_trig0      : std_logic;
+    signal led_trig1      : std_logic;
+
+    signal E              : std_logic;
+    signal Q              : std_logic;
+    signal DMA_n_BREQ_n   : std_logic;
+    signal MRDY           : std_logic;
+    signal TSC            : std_logic;
+    signal LIC            : std_logic;
+    signal AVMA           : std_logic;
+    signal BUSY           : std_logic;
+
+    signal XTAL           : std_logic;
+    signal EXTAL          : std_logic;
+
+begin
+
+    sw_interrupt <= sw1;
+    sw_reset     <= sw2;
+    led3         <= led_trig0;
+    led6         <= led_trig1;
+    led8         <= led_bkpt;
+
+    wrapper : entity work.MC6809CpuMon
+      generic map (
+          ClkMult           => 8,
+          ClkDiv            => 25,
+          ClkPer            => 20.000,
+          num_comparators   => num_comparators,
+          avr_prog_mem_size => avr_prog_mem_size
+      )
+      port map (
+
+        -- Fast clock
+        clock           => clock49,
+
+        -- Quadrature clocks
+        E               => E,
+        Q               => Q,
+
+        --6809 Signals
+        DMA_n_BREQ_n    => DMA_n_BREQ_n,
+
+        -- 6809E Sig
+        TSC             => TSC,
+        LIC             => LIC,
+        AVMA            => AVMA,
+        BUSY            => BUSY,
+
+        -- Signals common to both 6809 and 6809E
+        RES_n           => RES_n,
+        NMI_n           => NMI_n,
+        IRQ_n           => IRQ_n,
+        FIRQ_n          => FIRQ_n,
+        HALT_n          => HALT_n,
+        BS              => BS,
+        BA              => BA,
+        R_W_n           => R_W_n,
+
+        Addr            => Addr,
+        Data            => Data,
+
+        -- External trigger inputs
+        trig            => trig,
+
+        -- Serial Console
+        avr_RxD         => avr_RxD,
+        avr_TxD         => avr_TxD,
+
+        -- Switches
+        sw_interrupt    => sw_interrupt,
+        sw_reset        => sw_reset,
+
+        -- LEDs
+        led_bkpt        => led_bkpt,
+        led_trig0       => led_trig0,
+        led_trig1       => led_trig1,
+
+        -- OHO_DY1 connected to test connector
+        tmosi           => tmosi,
+        tdin            => tdin,
+        tcclk           => tcclk,
+
+        -- Debugging signals
+        test1           => test1,
+        test2           => test2
+    );
+
+    -- Pins whose functions are dependent on "E" mode
+    PIN33        <= BUSY  when EMode_n = '0' else 'Z';
+    DMA_n_BREQ_n <= '1'   when EMode_n = '0' else PIN33;
+
+    PIN34        <= 'Z'   when EMode_n = '0' else E;
+    E            <= PIN34 when EMode_n = '0' else quadrature(1);
+
+    PIN35        <= 'Z'   when EMode_n = '0' else Q;
+    Q            <= PIN35 when EMode_n = '0' else quadrature(0);
+
+    PIN36        <= AVMA  when EMode_n = '0' else 'Z';
+    MRDY         <= '1'   when EMode_n = '0' else PIN36;
+
+    PIN38        <= LIC   when EMode_n = '0' else 'Z';
+    EXTAL        <= '0'   when EMode_n = '0' else PIN38;
+
+    TSC          <= PIN39 when EMode_n = '0' else '0';
+    XTAL         <= '0'   when EMode_n = '0' else PIN39;
+
+    -- A locally generated test clock
+    -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
+    -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
+    clock_test   <= clk_count(1) when EMode_n = '0' else clock7_3728;
+
+    -- Quadrature clock generator, unused in 6809E mode
+    quadrature_gen : process(EXTAL)
+    begin
+        if rising_edge(EXTAL) then
+            if (MRDY = '1') then
+                if (quadrature = "00") then
+                    quadrature <= "01";
+                elsif (quadrature = "01") then
+                    quadrature <= "11";
+                elsif (quadrature = "11") then
+                    quadrature <= "10";
+                else
+                    quadrature <= "00";
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Seperate piece of circuitry that emits a 7.3728MHz clock
+    inst_dcm1 : entity work.DCM1 port map(
+        CLKIN_IN          => clock49,
+        CLK0_OUT          => clock7_3728,
+        CLK0_OUT1         => open,
+        CLK2X_OUT         => open
+    );
+
+    clk_gen : process(clock7_3728)
+    begin
+        if rising_edge(clock7_3728) then
+            clk_count <= clk_count + 1;
+        end if;
+    end process;
+
+end behavioral;

target/common/Makefile.inc

@@ -56,4 +56,4 @@ clean:
 	rm -f $(TARGET).bit $(TARGET).mcs $(PROG).mem $(PROG).bin $(PROG).out $(PROG).map *.o
 
 clobber: clean
-	rm -rf $(BMM_FILE) working/ iceconfig/
+	rm -rf $(BMM_FILE) working/ iseconfig/

target/godil_250/ice6809/ice6809.xise

@@ -241,7 +241,7 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
     </file>
-    <file xil_pn:name="../../../src/MC6809CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../src/MC6809CpuMon.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
     </file>

target/godil_500/ice6809/ice6809.xise

@@ -237,7 +237,7 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     </file>
-    <file xil_pn:name="../../../src/MC6809CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../src/MC6809CpuMon.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
     </file>

target/lx9_dave/ice6809/ice6809.xise

@@ -237,7 +237,7 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     </file>
-    <file xil_pn:name="../../../src/MC6809CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../src/MC6809CpuMon.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
     </file>

target/lx9_jason/ice6809/Makefile

@@ -5,13 +5,13 @@ ROOT       = ../../..
 COMMON     = ../../common
 
 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = MC6809CpuMonGODIL
+PROJECT    = MC6809CpuMonLX9
 
 # The target .bit file to be generated including the monitor program
 TARGET     = ice6809
 
 # Frequuency that the AVR runs at
-F_CPU      = 19354838
+F_CPU      = 16000000
 
 # Common include files
 include $(COMMON)/Makefile_$(TARGET).inc

target/lx9_jason/ice6809/ice6809.xise

@@ -237,11 +237,11 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     </file>
-    <file xil_pn:name="../../../src/MC6809CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../src/MC6809CpuMon.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
     </file>
-    <file xil_pn:name="../../../src/MC6809CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../src/MC6809CpuMonLX9.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
     </file>
@@ -358,7 +358,7 @@
     <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
@@ -368,9 +368,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809CpuMonGODIL" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809CpuMonLX9|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809CpuMonLX9.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809CpuMonLX9" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>

target/lx9_jason_flipped/ice6809/Makefile

@@ -5,13 +5,13 @@ ROOT       = ../../..
 COMMON     = ../../common
 
 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = MC6809CpuMonGODIL
+PROJECT    = MC6809CpuMonLX9
 
 # The target .bit file to be generated including the monitor program
 TARGET     = ice6809
 
 # Frequuency that the AVR runs at
-F_CPU      = 19354838
+F_CPU      = 16000000
 
 # Common include files
 include $(COMMON)/Makefile_$(TARGET).inc

target/lx9_jason_flipped/ice6809/ice6809.xise

@@ -241,7 +241,7 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
     </file>
-    <file xil_pn:name="../../../src/MC6809CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../src/MC6809CpuMonLX9.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
     </file>
@@ -358,7 +358,7 @@
     <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
@@ -368,9 +368,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MC6809CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809CpuMonGODIL" xil_pn:valueState="non-default"/>
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