6502/AtomBusMon
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Added new top level generics to 6502 and 6809 designs

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Change-Id: I14d70471b97948c165210bebad88b60965531207
This commit is contained in:
David Banks 2017-08-01 09:25:12 +01:00
parent f2974d12df
commit a4aa6df31a
4 changed files with 56 additions and 20 deletions
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19
src/AtomBusMon.vhd
View File

@ -24,7 +24,10 @@ entity AtomBusMon is
generic ( generic (
LEDsActiveHigh : boolean := false; -- default value correct for GODIL LEDsActiveHigh : boolean := false; -- default value correct for GODIL
SW1ActiveHigh : boolean := true; -- default value correct for GODIL SW1ActiveHigh : boolean := true; -- default value correct for GODIL
SW2ActiveHigh : boolean := false -- default value correct for GODIL SW2ActiveHigh : boolean := false; -- default value correct for GODIL
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer : real := 20.345 -- default value correct for GODIL
); );
port ( port (
clock49 : in std_logic; clock49 : in std_logic;
@ -88,10 +91,16 @@ begin
led6 <= not led6_n when LEDsActiveHigh else led6_n; led6 <= not led6_n when LEDsActiveHigh else led6_n;
led8 <= not led8_n when LEDsActiveHigh else led8_n; led8 <= not led8_n when LEDsActiveHigh else led8_n;
inst_dcm0 : entity work.DCM0 port map( inst_dcm0 : entity work.DCM0
CLKIN_IN => clock49, generic map (
CLKFX_OUT => clock_avr ClkMult => ClkMult,
); ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock49,
CLKFX_OUT => clock_avr
);
mon : entity work.BusMonCore mon : entity work.BusMonCore
generic map ( generic map (

19
src/AtomCpuMon.vhd
View File

@ -28,7 +28,10 @@ entity AtomCpuMon is
UseAlanDCore : boolean := false; UseAlanDCore : boolean := false;
LEDsActiveHigh : boolean := false; -- default value correct for GODIL LEDsActiveHigh : boolean := false; -- default value correct for GODIL
SW1ActiveHigh : boolean := true; -- default value correct for GODIL SW1ActiveHigh : boolean := true; -- default value correct for GODIL
SW2ActiveHigh : boolean := false -- default value correct for GODIL SW2ActiveHigh : boolean := false; -- default value correct for GODIL
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer : real := 20.345 -- default value correct for GODIL
); );
port ( port (
clock49 : in std_logic; clock49 : in std_logic;
@ -111,10 +114,16 @@ begin
led6 <= not led6_n when LEDsActiveHigh else led6_n; led6 <= not led6_n when LEDsActiveHigh else led6_n;
led8 <= not led8_n when LEDsActiveHigh else led8_n; led8 <= not led8_n when LEDsActiveHigh else led8_n;
inst_dcm0 : entity work.DCM0 port map( inst_dcm0 : entity work.DCM0
CLKIN_IN => clock49, generic map (
CLKFX_OUT => clock_avr ClkMult => ClkMult,
); ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock49,
CLKFX_OUT => clock_avr
);
core : entity work.MOS6502CpuMonCore core : entity work.MOS6502CpuMonCore
generic map ( generic map (

19
src/AtomFast6502.vhd
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@ -43,7 +43,10 @@ entity AtomFast6502 is
UseAlanDCore : boolean := false; UseAlanDCore : boolean := false;
LEDsActiveHigh : boolean := false; -- default value correct for GODIL LEDsActiveHigh : boolean := false; -- default value correct for GODIL
SW1ActiveHigh : boolean := true; -- default value correct for GODIL SW1ActiveHigh : boolean := true; -- default value correct for GODIL
SW2ActiveHigh : boolean := false -- default value correct for GODIL SW2ActiveHigh : boolean := false; -- default value correct for GODIL
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer : real := 20.345 -- default value correct for GODIL
); );
port ( port (
clock49 : in std_logic; clock49 : in std_logic;
@ -136,10 +139,16 @@ begin
led6 <= not led6_n when LEDsActiveHigh else led6_n; led6 <= not led6_n when LEDsActiveHigh else led6_n;
led8 <= not led8_n when LEDsActiveHigh else led8_n; led8 <= not led8_n when LEDsActiveHigh else led8_n;
inst_dcm0 : entity work.DCM0 port map( inst_dcm0 : entity work.DCM0
CLKIN_IN => clock49, generic map (
CLKFX_OUT => clock_avr ClkMult => ClkMult,
); ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock49,
CLKFX_OUT => clock_avr
);
inst_dcm2 : entity work.DCM2 port map( inst_dcm2 : entity work.DCM2 port map(
CLKIN_IN => Phi0, CLKIN_IN => Phi0,

19
src/MC6809ECpuMon.vhd
View File

@ -26,7 +26,10 @@ entity MC6809ECpuMon is
UseCPU09Core : boolean := true; UseCPU09Core : boolean := true;
LEDsActiveHigh : boolean := false; -- default value correct for GODIL LEDsActiveHigh : boolean := false; -- default value correct for GODIL
SW1ActiveHigh : boolean := true; -- default value correct for GODIL SW1ActiveHigh : boolean := true; -- default value correct for GODIL
SW2ActiveHigh : boolean := false -- default value correct for GODIL SW2ActiveHigh : boolean := false; -- default value correct for GODIL
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer : real := 20.345 -- default value correct for GODIL
); );
port ( port (
clock49 : in std_logic; clock49 : in std_logic;
@ -168,10 +171,16 @@ begin
led6 <= not led6_n when LEDsActiveHigh else led6_n; led6 <= not led6_n when LEDsActiveHigh else led6_n;
led8 <= not led8_n when LEDsActiveHigh else led8_n; led8 <= not led8_n when LEDsActiveHigh else led8_n;
inst_dcm0 : entity work.DCM0 port map( inst_dcm0 : entity work.DCM0
CLKIN_IN => clock49, generic map (
CLKFX_OUT => clock_avr ClkMult => ClkMult,
); ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock49,
CLKFX_OUT => clock_avr
);
mon : entity work.BusMonCore mon : entity work.BusMonCore
generic map ( generic map (