diff --git a/src/MC6809CpuMonALS.vhd b/src/MC6809CpuMonALS.vhd
new file mode 100644
index 0000000..c065ff7
--- /dev/null
+++ b/src/MC6809CpuMonALS.vhd
@@ -0,0 +1,172 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ /
+-- \ \ \/
+-- \ \
+-- / / Filename : MC6809CpuMonALS.vhd
+-- /___/ /\ Timestamp : 24/10/2019
+-- \ \ / \
+-- \___\/\___\
+--
+--Design Name: MC6809CpuMonALS
+--Device: XC6SLX9
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MC6809CpuMonALS is
+ generic (
+ ClkMult : integer := 8; -- default value correct for ALS
+ ClkDiv : integer := 25; -- default value correct for ALS
+ ClkPer : real := 20.0; -- default value correct for ALS
+ num_comparators : integer := 8; -- default value correct for ALS
+ avr_prog_mem_size : integer := 1024 * 9 -- default value correct for ALS
+ );
+ port (
+ clock : in std_logic;
+
+ --6809 Signals
+ BUSY : out std_logic;
+ E : in std_logic;
+ Q : in std_logic;
+ AVMA : out std_logic;
+ LIC : out std_logic;
+ TSC : in std_logic;
+
+ -- Signals common to both 6809 and 6809E
+ RES_n : in std_logic;
+ NMI_n : in std_logic;
+ IRQ_n : in std_logic;
+ FIRQ_n : in std_logic;
+ HALT_n : in std_logic;
+ BS : out std_logic;
+ BA : out std_logic;
+ R_W_n : out std_logic_vector(1 downto 0);
+
+ Addr : out std_logic_vector(15 downto 0);
+ Data : inout std_logic_vector(7 downto 0);
+
+ -- Level Shifers Controls
+ OERW_n : out std_logic;
+ OEAL_n : out std_logic;
+ OEAH_n : out std_logic;
+ OED_n : out std_logic;
+ DIRD : out std_logic;
+
+ -- External trigger inputs
+ trig : in std_logic_vector(1 downto 0);
+
+ -- ID/mode inputs
+ mode : in std_logic;
+ id : in std_logic_vector(3 downto 0);
+
+ -- Serial Console
+ avr_RxD : in std_logic;
+ avr_TxD : out std_logic;
+
+ -- GODIL Switches
+ sw_reset_n : in std_logic;
+ sw_interrupt_n : in std_logic;
+
+ -- GODIL LEDs
+ led_bkpt : out std_logic;
+ led_trig0 : out std_logic;
+ led_trig1 : out std_logic
+
+ );
+end MC6809CpuMonALS;
+
+architecture behavioral of MC6809CpuMonALS is
+
+ signal sw_reset : std_logic;
+ signal sw_interrupt : std_logic;
+ signal R_W_n_int : std_logic;
+
+begin
+
+ sw_reset <= not sw_reset_n;
+ sw_interrupt <= not sw_interrupt_n;
+
+ wrapper : entity work.MC6809CpuMonCore
+ generic map (
+ UseCPU09Core => true,
+ ClkMult => ClkMult,
+ ClkDiv => ClkDiv,
+ ClkPer => ClkPer,
+ num_comparators => num_comparators,
+ avr_prog_mem_size => avr_prog_mem_size
+ )
+ port map (
+
+ -- Fast clock
+ clock => clock,
+
+ -- Quadrature clocks
+ E => E,
+ Q => Q,
+
+ --6809 Signals
+ DMA_n_BREQ_n => '1',
+
+ -- 6809E Signals
+ TSC => TSC,
+ LIC => LIC,
+ AVMA => AVMA,
+ BUSY => BUSY,
+
+ -- Signals common to both 6809 and 6809E
+ RES_n => RES_n,
+ NMI_n => NMI_n,
+ IRQ_n => IRQ_n,
+ FIRQ_n => FIRQ_n,
+ HALT_n => HALT_n,
+ BS => BS,
+ BA => BA,
+ R_W_n => R_W_n_int,
+
+ Addr => Addr,
+ Data => Data,
+
+ -- External trigger inputs
+ trig => trig,
+
+ -- Serial Console
+ avr_RxD => avr_RxD,
+ avr_TxD => avr_TxD,
+
+ -- Switches
+ sw_interrupt => sw_interrupt,
+ sw_reset => sw_reset,
+
+ -- LEDs
+ led_bkpt => led_bkpt,
+ led_trig0 => led_trig0,
+ led_trig1 => led_trig1,
+
+ -- OHO_DY1 connected to test connector
+ tmosi => open,
+ tdin => open,
+ tcclk => open,
+
+ -- Debugging signals
+ test1 => open,
+ test2 => open
+ );
+
+ -- 6809 Outputs
+ R_W_n <= R_W_n_int & R_W_n_int;
+
+ -- Level Shifter Controls
+ OERW_n <= TSC;
+ OEAH_n <= TSC;
+ OEAL_n <= TSC;
+ OED_n <= TSC or not (Q or E);
+ DIRD <= R_W_n_int;
+
+end behavioral;
diff --git a/src/MC6809ECpuMon.vhd b/src/MC6809CpuMonCore.vhd
similarity index 66%
rename from src/MC6809ECpuMon.vhd
rename to src/MC6809CpuMonCore.vhd
index 37ffbc4..fed340e 100644
--- a/src/MC6809ECpuMon.vhd
+++ b/src/MC6809CpuMonCore.vhd
@@ -1,5 +1,5 @@
---------------------------------------------------------------------------------
--- Copyright (c) 2015 David Banks
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
@@ -7,12 +7,12 @@
-- /___/ \ /
-- \ \ \/
-- \ \
--- / / Filename : MC6808ECpuMon.vhd
--- /___/ /\ Timestamp : 02/07/2015
+-- / / Filename : MC6808CpuMonCore.vhd
+-- /___/ /\ Timestamp : 24/010/2019
-- \ \ / \
-- \___\/\___\
--
---Design Name: MC6808ECpuMon
+--Design Name: MC6808CpuMonCore
--Device: XC3S250E
library ieee;
@@ -21,37 +21,31 @@ use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.OhoPack.all ;
-entity MC6809ECpuMon is
+entity MC6809CpuMonCore is
generic (
- UseCPU09Core : boolean := true;
- LEDsActiveHigh : boolean := false; -- default value correct for GODIL
- SW1ActiveHigh : boolean := true; -- default value correct for GODIL
- SW2ActiveHigh : boolean := false; -- default value correct for GODIL
- ClkMult : integer := 10; -- default value correct for GODIL
- ClkDiv : integer := 31; -- default value correct for GODIL
- ClkPer : real := 20.345 -- default value correct for GODIL
+ UseCPU09Core : boolean := true;
+ ClkMult : integer := 10; -- default value correct for GODIL
+ ClkDiv : integer := 31; -- default value correct for GODIL
+ ClkPer : real := 20.345; -- default value correct for GODIL
+ num_comparators : integer := 8; -- default value correct for GODIL
+ avr_prog_mem_size : integer := 1024 * 9 -- default value correct for GODIL
);
port (
- clock49 : in std_logic;
+ -- Fast clock
+ clock : in std_logic;
- -- A locally generated test clock
- -- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
- -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
- clock_test : out std_logic;
-
- -- 6809/6809E mode selection
- -- Jumper is between pins B1 and D1
- -- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
- -- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
- EMode_n : in std_logic;
+ -- Quadrature clocks
+ E : in std_logic;
+ Q : in std_logic;
--6809 Signals
- PIN33 : inout std_logic;
- PIN34 : inout std_logic;
- PIN35 : inout std_logic;
- PIN36 : inout std_logic;
- PIN38 : inout std_logic;
- PIN39 : in std_logic;
+ DMA_n_BREQ_n : in std_logic;
+
+ -- 6809E Sig
+ TSC : in std_logic;
+ LIC : out std_logic;
+ AVMA : out std_logic;
+ BUSY : out std_logic;
-- Signals common to both 6809 and 6809E
RES_n : in std_logic;
@@ -73,14 +67,14 @@ entity MC6809ECpuMon is
avr_RxD : in std_logic;
avr_TxD : out std_logic;
- -- GODIL Switches
- sw1 : in std_logic;
- sw2 : in std_logic;
+ -- Switches
+ sw_interrupt : in std_logic;
+ sw_reset : in std_logic;
- -- GODIL LEDs
- led3 : out std_logic;
- led6 : out std_logic;
- led8 : out std_logic;
+ -- LEDs
+ led_bkpt : out std_logic;
+ led_trig0 : out std_logic;
+ led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
@@ -92,9 +86,9 @@ entity MC6809ECpuMon is
test2 : out std_logic
);
-end MC6809ECpuMon;
+end MC6809CpuMonCore;
-architecture behavioral of MC6809ECpuMon is
+architecture behavioral of MC6809CpuMonCore is
signal clock_avr : std_logic;
@@ -132,22 +126,9 @@ architecture behavioral of MC6809ECpuMon is
signal SS_Single : std_logic;
signal SS_Step : std_logic;
signal CountCycle : std_logic;
- signal special : std_logic_vector(1 downto 0);
+ signal special : std_logic_vector(1 downto 0);
- signal clk_count : std_logic_vector(1 downto 0);
- signal quadrature : std_logic_vector(1 downto 0);
- signal LIC : std_logic;
- signal AVMA : std_logic;
- signal XTAL : std_logic;
- signal EXTAL : std_logic;
- signal MRDY : std_logic;
- signal TSC : std_logic;
- signal BUSY : std_logic;
- signal Q : std_logic;
- signal E : std_logic;
- signal DMA_n_BREQ_n : std_logic;
-
- signal clock7_3728 : std_logic;
+ signal LIC_int : std_logic;
signal E_a : std_logic; -- E delayed by 0..20ns
signal E_b : std_logic; -- E delayed by 20..40ns
@@ -161,24 +142,27 @@ architecture behavioral of MC6809ECpuMon is
signal data_wr : std_logic;
signal nRSTout : std_logic;
- signal led3_n : std_logic; -- led to indicate ext trig 0 is active
- signal led6_n : std_logic; -- led to indicate ext trig 1 is active
- signal led8_n : std_logic; -- led to indicate CPU has hit a breakpoint (and is stopped)
- signal sw_interrupt_n : std_logic; -- switch to pause the CPU
- signal sw_reset_n : std_logic; -- switch to reset the CPU
-
signal NMI_n_masked : std_logic;
signal IRQ_n_masked : std_logic;
signal FIRQ_n_masked : std_logic;
+ signal led_trig0_n : std_logic;
+ signal led_trig1_n : std_logic;
+ signal led_bkpt_n : std_logic;
+
begin
- -- Generics allows polarity of switches/LEDs to be tweaked from the project file
- sw_interrupt_n <= not sw1 when SW1ActiveHigh else sw1;
- sw_reset_n <= not sw2 when SW2ActiveHigh else sw2;
- led3 <= not led3_n when LEDsActiveHigh else led3_n;
- led6 <= not led6_n when LEDsActiveHigh else led6_n;
- led8 <= not led8_n when LEDsActiveHigh else led8_n;
+ LIC <= LIC_int;
+ -- The following outputs are not implemented
+ -- BUSY (6809E mode)
+ BUSY <= '0';
+
+ -- The following inputs are not implemented
+ -- DMA_n_BREQ_n (6809 mode)
+
+ led_trig0 <= not led_trig0_n;
+ led_trig1 <= not led_trig1_n;
+ led_bkpt <= not led_bkpt_n;
inst_dcm0 : entity work.DCM0
generic map (
@@ -187,14 +171,14 @@ begin
ClkPer => ClkPer
)
port map(
- CLKIN_IN => clock49,
+ CLKIN_IN => clock,
CLKFX_OUT => clock_avr
);
mon : entity work.BusMonCore
generic map (
- num_comparators => 8,
- avr_prog_mem_size => 1024 * 9
+ num_comparators => num_comparators,
+ avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock_avr => clock_avr,
@@ -220,11 +204,11 @@ begin
lcd_db => open,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
- sw1 => not sw_interrupt_n,
- nsw2 => sw_reset_n,
- led3 => led3_n,
- led6 => led6_n,
- led8 => led8_n,
+ sw1 => sw_interrupt,
+ nsw2 => not sw_reset,
+ led3 => led_trig0_n,
+ led6 => led_trig1_n,
+ led8 => led_bkpt_n,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
@@ -277,7 +261,7 @@ begin
clk => cpu_clk,
rst => not nRST_sync,
vma => AVMA,
- lic_out => LIC,
+ lic_out => LIC_int,
ifetch => ifetch,
opfetch => open,
ba => BA,
@@ -315,7 +299,7 @@ begin
begin
if rising_edge(cpu_clk) then
if (hold = '0') then
- ifetch1 <= ifetch and not LIC;
+ ifetch1 <= ifetch and not LIC_int;
end if;
end if;
end process;
@@ -375,41 +359,10 @@ begin
memory_done <= memory_rd1 or memory_wr1;
- -- The following outputs are not implemented
- -- BUSY (6809E mode)
- BUSY <= '0';
-
- -- The following inputs are not implemented
- -- DMA_n_BREQ_n (6809 mode)
-
- -- Pins whose functions are dependent on "E" mode
- PIN33 <= BUSY when EMode_n = '0' else 'Z';
- DMA_n_BREQ_n <= '1' when EMode_n = '0' else PIN33;
-
- PIN34 <= 'Z' when EMode_n = '0' else E;
- E <= PIN34 when EMode_n = '0' else quadrature(1);
-
- PIN35 <= 'Z' when EMode_n = '0' else Q;
- Q <= PIN35 when EMode_n = '0' else quadrature(0);
-
- PIN36 <= AVMA when EMode_n = '0' else 'Z';
- MRDY <= '1' when EMode_n = '0' else PIN36;
-
- PIN38 <= LIC when EMode_n = '0' else 'Z';
- EXTAL <= '0' when EMode_n = '0' else PIN38;
-
- TSC <= PIN39 when EMode_n = '0' else '0';
- XTAL <= '0' when EMode_n = '0' else PIN39;
-
- -- A locally generated test clock
- -- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
- -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
- clock_test <= clk_count(1) when EMode_n = '0' else clock7_3728;
-
-- Delayed/Deglitched version of the E clock
- e_gen : process(clock49)
+ e_gen : process(clock)
begin
- if rising_edge(clock49) then
+ if rising_edge(clock) then
E_a <= E;
E_b <= E_a;
if E_b /= E_i then
@@ -440,42 +393,9 @@ begin
-- Note: on the dragon this is not critical; setting to '1' seemed to work
data_wr <= Q or E;
- -- Quadrature clock generator, unused in 6809E mode
- quadrature_gen : process(EXTAL)
- begin
- if rising_edge(EXTAL) then
- if (MRDY = '1') then
- if (quadrature = "00") then
- quadrature <= "01";
- elsif (quadrature = "01") then
- quadrature <= "11";
- elsif (quadrature = "11") then
- quadrature <= "10";
- else
- quadrature <= "00";
- end if;
- end if;
- end if;
- end process;
-
- -- Seperate piece of circuitry that emits a 7.3728MHz clock
-
- inst_dcm1 : entity work.DCM1 port map(
- CLKIN_IN => clock49,
- CLK0_OUT => clock7_3728,
- CLK0_OUT1 => open,
- CLK2X_OUT => open
- );
-
- clk_gen : process(clock7_3728)
- begin
- if rising_edge(clock7_3728) then
- clk_count <= clk_count + 1;
- end if;
- end process;
-
-- Spare pins used for testing
test1 <= E_a;
test2 <= E_c;
+
end behavioral;
diff --git a/src/MC6809CpuMonGODIL.vhd b/src/MC6809CpuMonGODIL.vhd
new file mode 100644
index 0000000..5abf6df
--- /dev/null
+++ b/src/MC6809CpuMonGODIL.vhd
@@ -0,0 +1,254 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ /
+-- \ \ \/
+-- \ \
+-- / / Filename : MC6808CpuMonGODIL.vhd
+-- /___/ /\ Timestamp : 24/10/2019
+-- \ \ / \
+-- \___\/\___\
+--
+--Design Name: MC6808CpuMonGODIL
+--Device: XC3S250E/XC3S500E
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MC6809CpuMonGODIL is
+ generic (
+ LEDsActiveHigh : boolean := false; -- default value correct for GODIL
+ SW1ActiveHigh : boolean := true; -- default value correct for GODIL
+ SW2ActiveHigh : boolean := false; -- default value correct for GODIL
+ ClkMult : integer := 10; -- default value correct for GODIL
+ ClkDiv : integer := 31; -- default value correct for GODIL
+ ClkPer : real := 20.345; -- default value correct for GODIL
+ num_comparators : integer := 8; -- default value correct for GODIL
+ avr_prog_mem_size : integer := 1024 * 9 -- default value correct for GODIL
+ );
+ port (
+ clock49 : in std_logic;
+
+ -- A locally generated test clock
+ -- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
+ -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
+ clock_test : out std_logic;
+
+ -- 6809/6809E mode selection
+ -- Jumper is between pins B1 and D1
+ -- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
+ -- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
+ EMode_n : in std_logic;
+
+ --6809 Signals
+ PIN33 : inout std_logic;
+ PIN34 : inout std_logic;
+ PIN35 : inout std_logic;
+ PIN36 : inout std_logic;
+ PIN38 : inout std_logic;
+ PIN39 : in std_logic;
+
+ -- Signals common to both 6809 and 6809E
+ RES_n : in std_logic;
+ NMI_n : in std_logic;
+ IRQ_n : in std_logic;
+ FIRQ_n : in std_logic;
+ HALT_n : in std_logic;
+ BS : out std_logic;
+ BA : out std_logic;
+ R_W_n : out std_logic;
+
+ Addr : out std_logic_vector(15 downto 0);
+ Data : inout std_logic_vector(7 downto 0);
+
+ -- External trigger inputs
+ trig : in std_logic_vector(1 downto 0);
+
+ -- Serial Console
+ avr_RxD : in std_logic;
+ avr_TxD : out std_logic;
+
+ -- GODIL Switches
+ sw1 : in std_logic;
+ sw2 : in std_logic;
+
+ -- GODIL LEDs
+ led3 : out std_logic;
+ led6 : out std_logic;
+ led8 : out std_logic;
+
+ -- OHO_DY1 connected to test connector
+ tmosi : out std_logic;
+ tdin : out std_logic;
+ tcclk : out std_logic;
+
+ -- Debugging signals
+ test1 : out std_logic;
+ test2 : out std_logic
+
+ );
+end MC6809CpuMonGODIL;
+
+architecture behavioral of MC6809CpuMonGODIL is
+
+ signal clk_count : std_logic_vector(1 downto 0);
+ signal quadrature : std_logic_vector(1 downto 0);
+
+ signal clock7_3728 : std_logic;
+
+ signal sw_reset : std_logic;
+ signal sw_interrupt : std_logic;
+ signal led_bkpt : std_logic;
+ signal led_trig0 : std_logic;
+ signal led_trig1 : std_logic;
+
+ signal E : std_logic;
+ signal Q : std_logic;
+ signal DMA_n_BREQ_n : std_logic;
+ signal MRDY : std_logic;
+ signal TSC : std_logic;
+ signal LIC : std_logic;
+ signal AVMA : std_logic;
+ signal BUSY : std_logic;
+
+ signal XTAL : std_logic;
+ signal EXTAL : std_logic;
+
+begin
+
+ -- Generics allows polarity of switches/LEDs to be tweaked from the project file
+ sw_interrupt <= sw1 when SW1ActiveHigh else not sw1;
+ sw_reset <= sw2 when SW2ActiveHigh else not sw2;
+ led3 <= led_trig0 when LEDsActiveHigh else not led_trig0;
+ led6 <= led_trig1 when LEDsActiveHigh else not led_trig1;
+ led8 <= led_bkpt when LEDsActiveHigh else not led_bkpt;
+
+ wrapper : entity work.MC6809CpuMonCore
+ generic map (
+ UseCPU09Core => true,
+ ClkMult => ClkMult,
+ ClkDiv => ClkDiv,
+ ClkPer => ClkPer,
+ num_comparators => num_comparators,
+ avr_prog_mem_size => avr_prog_mem_size
+ )
+ port map (
+
+ -- Fast clock
+ clock => clock49,
+
+ -- Quadrature clocks
+ E => E,
+ Q => Q,
+
+ --6809 Signals
+ DMA_n_BREQ_n => DMA_n_BREQ_n,
+
+ -- 6809E Sig
+ TSC => TSC,
+ LIC => LIC,
+ AVMA => AVMA,
+ BUSY => BUSY,
+
+ -- Signals common to both 6809 and 6809E
+ RES_n => RES_n,
+ NMI_n => NMI_n,
+ IRQ_n => IRQ_n,
+ FIRQ_n => FIRQ_n,
+ HALT_n => HALT_n,
+ BS => BS,
+ BA => BA,
+ R_W_n => R_W_n,
+
+ Addr => Addr,
+ Data => Data,
+
+ -- External trigger inputs
+ trig => trig,
+
+ -- Serial Console
+ avr_RxD => avr_RxD,
+ avr_TxD => avr_TxD,
+
+ -- Switches
+ sw_interrupt => sw_interrupt,
+ sw_reset => sw_reset,
+
+ -- LEDs
+ led_bkpt => led_bkpt,
+ led_trig0 => led_trig0,
+ led_trig1 => led_trig1,
+
+ -- OHO_DY1 connected to test connector
+ tmosi => tmosi,
+ tdin => tdin,
+ tcclk => tcclk,
+
+ -- Debugging signals
+ test1 => test1,
+ test2 => test2
+ );
+
+ -- Pins whose functions are dependent on "E" mode
+ PIN33 <= BUSY when EMode_n = '0' else 'Z';
+ DMA_n_BREQ_n <= '1' when EMode_n = '0' else PIN33;
+
+ PIN34 <= 'Z' when EMode_n = '0' else E;
+ E <= PIN34 when EMode_n = '0' else quadrature(1);
+
+ PIN35 <= 'Z' when EMode_n = '0' else Q;
+ Q <= PIN35 when EMode_n = '0' else quadrature(0);
+
+ PIN36 <= AVMA when EMode_n = '0' else 'Z';
+ MRDY <= '1' when EMode_n = '0' else PIN36;
+
+ PIN38 <= LIC when EMode_n = '0' else 'Z';
+ EXTAL <= '0' when EMode_n = '0' else PIN38;
+
+ TSC <= PIN39 when EMode_n = '0' else '0';
+ XTAL <= '0' when EMode_n = '0' else PIN39;
+
+ -- A locally generated test clock
+ -- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
+ -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
+ clock_test <= clk_count(1) when EMode_n = '0' else clock7_3728;
+
+ -- Quadrature clock generator, unused in 6809E mode
+ quadrature_gen : process(EXTAL)
+ begin
+ if rising_edge(EXTAL) then
+ if (MRDY = '1') then
+ if (quadrature = "00") then
+ quadrature <= "01";
+ elsif (quadrature = "01") then
+ quadrature <= "11";
+ elsif (quadrature = "11") then
+ quadrature <= "10";
+ else
+ quadrature <= "00";
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Seperate piece of circuitry that emits a 7.3728MHz clock
+ inst_dcm1 : entity work.DCM1 port map(
+ CLKIN_IN => clock49,
+ CLK0_OUT => clock7_3728,
+ CLK0_OUT1 => open,
+ CLK2X_OUT => open
+ );
+
+ clk_gen : process(clock7_3728)
+ begin
+ if rising_edge(clock7_3728) then
+ clk_count <= clk_count + 1;
+ end if;
+ end process;
+
+end behavioral;
diff --git a/src/MultiBootLoader.v b/src/MultiBootLoader.v
index e589644..53b1a5a 100644
--- a/src/MultiBootLoader.v
+++ b/src/MultiBootLoader.v
@@ -148,8 +148,8 @@ module MultiBootLoader
5'b11101: icap_din = 16'hC000; // Z80 (mode = 1)
5'b01101: icap_din = 16'hC000; // Z80 (mode = 0)
5'b01110: icap_din = 16'h0000; // 65C02
- // 5'b11100: icap_din = 16'h4000; // 6809 (mode = 1)
- // 5'b01100: icap_din = 16'h4000; // 6809 (mode = 0)
+ 5'b11100: icap_din = 16'h4000; // 6809 (mode = 1)
+ 5'b01100: icap_din = 16'h4000; // 6809 (mode = 0)
default: icap_din = 16'h4000; // Unknown Adapter
endcase
@@ -174,8 +174,8 @@ module MultiBootLoader
5'b11101: icap_din = 16'h030F; // Z80 (mode = 1)
5'b01101: icap_din = 16'h030F; // Z80 (mode = 0)
5'b01110: icap_din = 16'h0315; // 65C02
- // 5'b11100: icap_din = 16'h031A; // 6809 (mode = 1)
- // 5'b01100: icap_din = 16'h031A; // 6809 (mode = 0)
+ 5'b11100: icap_din = 16'h031A; // 6809 (mode = 1)
+ 5'b01100: icap_din = 16'h031A; // 6809 (mode = 0)
default: icap_din = 16'h0305; // Unknown Adapter
endcase
diff --git a/target/godil_250/ice6809/Makefile b/target/godil_250/ice6809/Makefile
index b6f8493..c13bf31 100644
--- a/target/godil_250/ice6809/Makefile
+++ b/target/godil_250/ice6809/Makefile
@@ -5,7 +5,7 @@ ROOT = ../../..
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
-PROJECT = MC6809ECpuMon
+PROJECT = MC6809CpuMonGODIL
# The target .bit file to be generated including the monitor program
TARGET = ice6809
diff --git a/target/godil_250/ice6809/ice6809.xise b/target/godil_250/ice6809/ice6809.xise
index 4bff496..887b57e 100644
--- a/target/godil_250/ice6809/ice6809.xise
+++ b/target/godil_250/ice6809/ice6809.xise
@@ -18,17 +18,13 @@
-
-
-
-
-
+
-
+
@@ -227,7 +223,7 @@
-
+
@@ -241,6 +237,14 @@
+
+
+
+
+
+
+
+
@@ -256,7 +260,7 @@
-
+
@@ -270,7 +274,7 @@
-
+
@@ -350,9 +354,9 @@
-
-
-
+
+
+
@@ -410,7 +414,7 @@
-
+
@@ -422,10 +426,10 @@
-
-
-
-
+
+
+
+
@@ -445,7 +449,7 @@
-
+
@@ -549,7 +553,10 @@
-
+
+
+
+
diff --git a/target/godil_250/ice6809/memory.bmm b/target/godil_250/ice6809/memory.bmm
index 13098d9..3914280 100644
--- a/target/godil_250/ice6809/memory.bmm
+++ b/target/godil_250/ice6809/memory.bmm
@@ -2,41 +2,41 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
END_BUS_BLOCK;
-
+
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
\ No newline at end of file
diff --git a/target/godil_250/icez80/icez80.xise b/target/godil_250/icez80/icez80.xise
index f52efa3..6b8539d 100644
--- a/target/godil_250/icez80/icez80.xise
+++ b/target/godil_250/icez80/icez80.xise
@@ -32,11 +32,11 @@
-
+
-
+
@@ -44,7 +44,7 @@
-
+
@@ -60,7 +60,7 @@
-
+
@@ -72,7 +72,7 @@
-
+
@@ -92,7 +92,7 @@
-
+
@@ -124,7 +124,7 @@
-
+
@@ -156,11 +156,11 @@
-
+
-
+
@@ -168,15 +168,15 @@
-
+
-
+
-
+
@@ -192,11 +192,11 @@
-
+
-
+
@@ -208,19 +208,19 @@
-
+
-
+
-
+
-
+
@@ -228,34 +228,34 @@
-
+
-
+
-
+
-
+
-
+
-
+
-
+
diff --git a/target/godil_500/ice6809/Makefile b/target/godil_500/ice6809/Makefile
index b6f8493..c13bf31 100644
--- a/target/godil_500/ice6809/Makefile
+++ b/target/godil_500/ice6809/Makefile
@@ -5,7 +5,7 @@ ROOT = ../../..
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
-PROJECT = MC6809ECpuMon
+PROJECT = MC6809CpuMonGODIL
# The target .bit file to be generated including the monitor program
TARGET = ice6809
diff --git a/target/godil_500/ice6809/ice6809.xise b/target/godil_500/ice6809/ice6809.xise
index d186b86..d3fa078 100644
--- a/target/godil_500/ice6809/ice6809.xise
+++ b/target/godil_500/ice6809/ice6809.xise
@@ -18,17 +18,13 @@
-
-
-
-
-
+
-
+
@@ -227,7 +223,7 @@
-
+
@@ -241,6 +237,14 @@
+
+
+
+
+
+
+
+
@@ -350,9 +354,9 @@
-
-
-
+
+
+
@@ -410,7 +414,7 @@
-
+
@@ -422,10 +426,10 @@
-
-
-
-
+
+
+
+
@@ -445,7 +449,7 @@
-
+
diff --git a/target/godil_500/ice6809/memory.bmm b/target/godil_500/ice6809/memory.bmm
index 13098d9..3914280 100644
--- a/target/godil_500/ice6809/memory.bmm
+++ b/target/godil_500/ice6809/memory.bmm
@@ -2,41 +2,41 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
END_BUS_BLOCK;
-
+
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
\ No newline at end of file
diff --git a/target/godil_500/ipcore/WatchEvents.xise b/target/godil_500/ipcore/WatchEvents.xise
index dc5f769..ecf0951 100644
--- a/target/godil_500/ipcore/WatchEvents.xise
+++ b/target/godil_500/ipcore/WatchEvents.xise
@@ -30,7 +30,6 @@
-
diff --git a/target/lx9_dave/gen_mcs.sh b/target/lx9_dave/gen_mcs.sh
index 5dbb103..746c880 100755
--- a/target/lx9_dave/gen_mcs.sh
+++ b/target/lx9_dave/gen_mcs.sh
@@ -3,7 +3,6 @@
# The S25FL032P has space for ~12 designs if they are uncompressed
#
-#-u 1A4000 \
#-u 1F8000 \
#-u 24C000 \
#-u 2A0000 \
@@ -23,6 +22,7 @@ promgen \
-u A8000 ice6502/ice6502.bit \
-u FC000 icez80/icez80.bit \
-u 150000 ice65c02/ice65c02.bit \
+ -u 1A4000 ice6809/ice6809.bit \
-o $NAME.mcs -p mcs -w -spi -s 8192
rm -f $NAME.cfi $NAME.prm
diff --git a/target/lx9_dave/ice6809/Makefile b/target/lx9_dave/ice6809/Makefile
new file mode 100644
index 0000000..1e517bd
--- /dev/null
+++ b/target/lx9_dave/ice6809/Makefile
@@ -0,0 +1,18 @@
+# The root directory of the project
+ROOT = ../../..
+
+# The common directory for makefile includes, etc.
+COMMON = ../../common
+
+# The project .bit file produced by the Xilinx .xise project
+PROJECT = MC6809CpuMonALS
+
+# The target .bit file to be generated including the monitor program
+TARGET = ice6809
+
+# Frequuency that the AVR runs at
+F_CPU = 16000000
+
+# Common include files
+include $(COMMON)/Makefile_$(TARGET).inc
+include $(COMMON)/Makefile.inc
diff --git a/target/lx9_dave/ice6809/board.ucf b/target/lx9_dave/ice6809/board.ucf
new file mode 100644
index 0000000..a6e209f
--- /dev/null
+++ b/target/lx9_dave/ice6809/board.ucf
@@ -0,0 +1,78 @@
+NET "clock" TNM_NET = clk_period_grp_50;
+TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;
+
+NET "E" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
+
+#NET "VSS" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
+NET "NMI_n" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
+NET "IRQ_n" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
+NET "FIRQ_n" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
+NET "BS" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5
+NET "BA" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6
+#NET "VCC" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7
+NET "Addr<0>" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8
+NET "Addr<1>" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9
+NET "Addr<2>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10
+NET "Addr<3>" LOC="P21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11
+NET "Addr<4>" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12
+NET "Addr<5>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13
+NET "Addr<6>" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14
+NET "Addr<7>" LOC="P14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15
+NET "Addr<8>" LOC="P6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16
+NET "Addr<9>" LOC="P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17
+NET "Addr<10>" LOC="P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18
+NET "Addr<11>" LOC="P1" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19
+NET "Addr<12>" LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20
+
+NET "Addr<13>" LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21
+NET "Addr<14>" LOC="P143" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22
+NET "Addr<15>" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23
+NET "Data<7>" LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24
+NET "Data<6>" LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25
+NET "Data<5>" LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26
+NET "Data<4>" LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27
+NET "Data<3>" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28
+NET "Data<2>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29
+NET "Data<1>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30
+NET "Data<0>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31
+NET "R_W_n<0>" LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
+NET "R_W_n<1>" LOC="P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
+NET "BUSY" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33
+NET "E" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
+NET "Q" LOC="P82" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35
+NET "AVMA" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36
+NET "RES_n" LOC="P81" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
+NET "LIC" LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38
+NET "TSC" LOC="P74" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
+NET "HALT_n" LOC="P75" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40
+
+# Output Enables
+NET "OERW_n" LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "OEAH_n" LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "OEAL_n" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "OED_n" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "DIRD" LOC="P93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# LEDs and Switches
+NET "led_bkpt" LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
+NET "led_trig0" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
+NET "led_trig1" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
+NET "sw_reset_n" LOC="P45" | IOSTANDARD = LVCMOS33 | PULLUP ; # reset
+NET "sw_interrupt_n" LOC="P66" | IOSTANDARD = LVCMOS33 | PULLUP ; # interrupt
+
+# ID/Jumper
+NET "mode" LOC="P140" | IOSTANDARD = LVCMOS33 | PULLUP ; # mode jumper
+NET "id<0>" LOC="P88 " | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
+NET "id<1>" LOC="P87 " | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
+NET "id<2>" LOC="P85" | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
+NET "id<3>" LOC="P84" | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
+
+# UART
+NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
+
+# External trigger inputs
+NET "trig<0>" LOC="P116" | IOSTANDARD = LVCMOS33 ;
+NET "trig<1>" LOC="P123" | IOSTANDARD = LVCMOS33 ;
diff --git a/target/lx9_dave/ice6809/ice6809.xise b/target/lx9_dave/ice6809/ice6809.xise
new file mode 100644
index 0000000..7117370
--- /dev/null
+++ b/target/lx9_dave/ice6809/ice6809.xise
@@ -0,0 +1,613 @@
+
+
+
+
+
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diff --git a/target/lx9_dave/ice6809/memory.bmm b/target/lx9_dave/ice6809/memory.bmm
new file mode 100644
index 0000000..3914280
--- /dev/null
+++ b/target/lx9_dave/ice6809/memory.bmm
@@ -0,0 +1,42 @@
+ADDRESS_MAP avrmap PPC405 0
+
+ ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
+ BUS_BLOCK
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+ END_BUS_BLOCK;
+
+ BUS_BLOCK
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+ END_BUS_BLOCK;
+
+ BUS_BLOCK
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+ END_BUS_BLOCK;
+
+ BUS_BLOCK
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+ END_BUS_BLOCK;
+
+ BUS_BLOCK
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+ END_BUS_BLOCK;
+
+ BUS_BLOCK
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+ END_BUS_BLOCK;
+
+ BUS_BLOCK
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+ END_BUS_BLOCK;
+
+ BUS_BLOCK
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+ END_BUS_BLOCK;
+
+ BUS_BLOCK
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+ END_BUS_BLOCK;
+
+ END_ADDRESS_SPACE;
+
+END_ADDRESS_MAP;
\ No newline at end of file
diff --git a/target/lx9_jason/ice6809/Makefile b/target/lx9_jason/ice6809/Makefile
index 818f1e8..b23c81c 100644
--- a/target/lx9_jason/ice6809/Makefile
+++ b/target/lx9_jason/ice6809/Makefile
@@ -5,7 +5,7 @@ ROOT = ../../..
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
-PROJECT = MC6809ECpuMon
+PROJECT = MC6809CpuMonGODIL
# The target .bit file to be generated including the monitor program
TARGET = ice6809
diff --git a/target/lx9_jason/ice6809/ice6809.xise b/target/lx9_jason/ice6809/ice6809.xise
index fd45017..62c651b 100644
--- a/target/lx9_jason/ice6809/ice6809.xise
+++ b/target/lx9_jason/ice6809/ice6809.xise
@@ -18,17 +18,13 @@
-
-
-
-
-
+
-
+
@@ -227,7 +223,7 @@
-
+
@@ -241,6 +237,14 @@
+
+
+
+
+
+
+
+
@@ -364,9 +368,9 @@
-
-
-
+
+
+
@@ -435,7 +439,7 @@
-
+
@@ -450,10 +454,10 @@
-
-
-
-
+
+
+
+
@@ -477,7 +481,7 @@
-
+
diff --git a/target/lx9_jason/ice6809/memory.bmm b/target/lx9_jason/ice6809/memory.bmm
index 13098d9..3914280 100644
--- a/target/lx9_jason/ice6809/memory.bmm
+++ b/target/lx9_jason/ice6809/memory.bmm
@@ -2,41 +2,41 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
END_BUS_BLOCK;
-
+
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
\ No newline at end of file
diff --git a/target/lx9_jason_flipped/ice6809/Makefile b/target/lx9_jason_flipped/ice6809/Makefile
index 818f1e8..b23c81c 100644
--- a/target/lx9_jason_flipped/ice6809/Makefile
+++ b/target/lx9_jason_flipped/ice6809/Makefile
@@ -5,7 +5,7 @@ ROOT = ../../..
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
-PROJECT = MC6809ECpuMon
+PROJECT = MC6809CpuMonGODIL
# The target .bit file to be generated including the monitor program
TARGET = ice6809
diff --git a/target/lx9_jason_flipped/ice6809/ice6809.xise b/target/lx9_jason_flipped/ice6809/ice6809.xise
index fd45017..34f0de0 100644
--- a/target/lx9_jason_flipped/ice6809/ice6809.xise
+++ b/target/lx9_jason_flipped/ice6809/ice6809.xise
@@ -18,17 +18,13 @@
-
-
-
-
-
+
-
+
@@ -227,7 +223,7 @@
-
+
@@ -241,6 +237,14 @@
+
+
+
+
+
+
+
+
@@ -272,7 +276,7 @@
-
+
@@ -364,9 +368,9 @@
-
-
-
+
+
+
@@ -435,7 +439,7 @@
-
+
@@ -450,10 +454,10 @@
-
-
-
-
+
+
+
+
@@ -477,7 +481,7 @@
-
+
diff --git a/target/lx9_jason_flipped/ice6809/memory.bmm b/target/lx9_jason_flipped/ice6809/memory.bmm
index 13098d9..3914280 100644
--- a/target/lx9_jason_flipped/ice6809/memory.bmm
+++ b/target/lx9_jason_flipped/ice6809/memory.bmm
@@ -2,41 +2,41 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
- mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+ wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
END_BUS_BLOCK;
-
+
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
\ No newline at end of file