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R65C02: fix warnings

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Change-Id: I0578e4afcdc0817046bafe2b78fecbfe82102f05
This commit is contained in:
David Banks 2021-03-13 11:23:56 +00:00
parent 839d510af9
commit c184b6466a
1 changed files with 21 additions and 26 deletions
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21
src/AlanD/R65Cx2.vhd
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@ -15,7 +15,6 @@ use ieee.numeric_std.ALL;
entity R65C02 is
port (
reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
@ -41,8 +40,9 @@ end R65C02;
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (-) => fetch, cycle2, .., cycleJump
-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump
-- Jmp abs (3) => fetch, cycle2, cycleJump
-- Jmp (ind) (5) => fetch, cycle2, cycle3, cycleRead, cycleJump
-- Jmp (ind,x) (5) => fetch, cycle2, cycle3, cycleRead, cycleJump
-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4
-- -----------------------------------------------------------------------
@ -566,7 +566,6 @@ architecture Behavioral of R65C02 is
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
@ -701,7 +700,7 @@ begin
--hardware interrupts IRQ & NMI will push the B flag as being 0.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C)
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C, R)
variable lowBits : unsigned(5 downto 0);
variable nineBits : unsigned(8 downto 0);
variable rmwBits : unsigned(8 downto 0);
@ -717,6 +716,7 @@ begin
rmwBits := (others => '-');
tsxBits := (others => '-');
R <= '1';
B <= '0';
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
@ -907,14 +907,6 @@ begin
nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
-- DMB Remove Pipelining
-- process(clk)
-- begin
-- if rising_edge(clk) then
nextOpcInfoReg <= nextOpcInfo;
-- end if;
-- end process;
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
@ -982,6 +974,8 @@ begin
case theCpuCycle is
when opcodeFetch =>
-- DMB: Implement single cycle NOPs (columns 3,7,B,F) by
-- looking ahead at opcode (bypassing the normal decoding)
if nextOpcode(1 downto 0) = "11" then
nextCpuCycle <= opcodeFetch;
else
@ -1047,6 +1041,7 @@ begin
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect =>
nextCpuCycle <= cycleIndirect;