From c8f997863e5f9daccf3de4bdf1aeccfb591aaa10 Mon Sep 17 00:00:00 2001 From: David Banks Date: Fri, 8 Nov 2019 09:54:07 +0000 Subject: [PATCH] Z80: Fix timing of T80 IO cycles Change-Id: I769dcb01b95008b62455c86151252fdbd6d0aab5 --- src/T80/T80a.vhd | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/src/T80/T80a.vhd b/src/T80/T80a.vhd index eab8db8..2d00cfa 100644 --- a/src/T80/T80a.vhd +++ b/src/T80/T80a.vhd @@ -131,8 +131,8 @@ begin BUSAK_n <= BUSAK_n_i; MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); - RD_n_i <= not RD or Req_Inhibit; - WR_n_j <= WR_n_i; -- 0247a + RD_n_i <= not RD or (IORQ and IReq_Inhibit) or Req_Inhibit; -- DMB + WR_n_j <= WR_n_i or (IORQ and IReq_Inhibit); -- DMB HALT_n <= HALT_n_int; @@ -212,7 +212,7 @@ begin process (CLK_n) -- 0247a begin if CLK_n'event and CLK_n = '1' then - -- IReq_Inhibit <= not IORQ; + IReq_Inhibit <= (not IORQ) and IntCycle_n; end if; end process; @@ -229,7 +229,7 @@ begin WR_n_i <= '1'; end if; else - if TState = "001" and IORQ_n_i = '0' then + if TState = "001" then -- DMB WR_n_i <= not Write; elsif Tstate = "011" then WR_n_i <= '1'; @@ -295,11 +295,7 @@ begin if TState = "001" and NoRead = '0' then IORQ_n_i <= not IORQ; MREQ <= not IORQ; - if IORQ = '0' then - RD <= not Write; - elsif IORQ_n_i = '0' then - RD <= not Write; - end if; + RD <= not Write; -- DMB end if; if TState = "011" then RD <= '0';