mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2025-01-10 17:29:28 +00:00
Added watch functionality
Change-Id: I0510b12c8bc16c0ee6e23d6dd133a4b3b019d76c
This commit is contained in:
David Banks
parent
16a4769b47
commit
c9c6001332
@ -17,7 +17,7 @@
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<files>
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<file xil_pn:name="src/AtomBusMon.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
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</file>
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<file xil_pn:name="src/constraints.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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@ -233,6 +233,13 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
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</file>
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<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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<properties>
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@ -19,12 +19,11 @@
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#define OFFSET_IAL 0
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#define OFFSET_IAH 1
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#define OFFSET_BAL 2
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#define OFFSET_BAH 3
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#define OFFSET_WAL 4
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#define OFFSET_WAH 5
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#define OFFSET_BM 6
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#define OFFSET_WM 7
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#define OFFSET_BW_IAL 2
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#define OFFSET_BW_IAH 3
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#define OFFSET_BW_BAL 4
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#define OFFSET_BW_BAH 5
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#define OFFSET_BW_M 6
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// Commands
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// 000x Enable/Disable single strpping
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@ -38,6 +37,7 @@
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#define CMD_LOAD_REG 0x04
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#define CMD_RESET 0x06
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#define CMD_STEP 0x08
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#define CMD_WATCH_READ 0x09
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// Control bits
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#define CMD_MASK 0x1F
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@ -46,28 +46,33 @@
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#define MUX_SEL_BIT 5
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// Status bits
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#define BRKPT_INTERRUPTED_MASK 0x40
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#define BRKPT_ACTIVE_MASK 0x80
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#define INTERRUPTED_MASK 0x40
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#define BW_ACTIVE_MASK 0x80
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// Breakpoint Modes
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#define BRKPT_INSTR 0x01
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#define BRKPT_READ 0x02
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#define BRKPT_WRITE 0x04
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#define BRKPT_INSTR 0
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#define BRKPT_READ 1
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#define BRKPT_WRITE 2
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#define WATCH_INSTR 3
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#define WATCH_READ 4
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#define WATCH_WRITE 5
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#define UNDEFINED 6
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char *brkptStrings[8] = {
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"No breakpoint",
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"Instruction breakpoint",
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"Read breakpoint",
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"Instruction, read breakpoints",
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"Write breakpoint",
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"Instruction, write breakpoints",
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"Read, write breakpoints",
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"Instruction, read, write breakpoints"
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#define BW_MEM_MASK ((1<<BRKPT_READ) | (1<<BRKPT_WRITE) | (1<<WATCH_READ) | (1<<WATCH_WRITE))
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char *modeStrings[7] = {
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"Instruction breakpoint",
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"Read breakpoint",
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"Write breakpoint",
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"Instruction watch",
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"Read watch",
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"Write watch",
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"Undefined",
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};
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#define VERSION "0.11"
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#define NUMCMDS 14
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#define NUMCMDS 20
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#define MAXBKPTS 4
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int numbkpts = 0;
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@ -102,9 +107,15 @@ char *cmdStrings[NUMCMDS] = {
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"breaki",
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"breakr",
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"breakw",
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"watchi",
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"watchr",
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"watchw",
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"bcleari",
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"bclearr",
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"bclearw",
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"wcleari",
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"wclearr",
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"wclearw",
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"continue",
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};
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@ -220,6 +231,40 @@ void lcdAddr(unsigned int addr) {
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}
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void logMode(unsigned int mode) {
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int i;
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int first = 1;
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for (i = 0; i < UNDEFINED; i++) {
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if (mode & 1) {
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if (!first) {
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log0(",");
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first = 0;
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}
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log0("%s", modeStrings[i]);
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}
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mode >>= 1;
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}
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}
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int logDetails() {
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unsigned int i_addr = hwRead16(OFFSET_BW_IAL);
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unsigned int b_addr = hwRead16(OFFSET_BW_BAL);
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unsigned int mode = hwRead8(OFFSET_BW_M);
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unsigned int watch = mode & 8;
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// Convert from 4-bit compressed to 6 bit expanded mode representation
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if (watch) {
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mode = (mode & 7) << 3;
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}
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// Update the serial console
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logMode(mode);
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log0(" hit at %04X", i_addr);
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if (mode & BW_MEM_MASK) {
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log0(" accessing %04X", b_addr);
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}
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log0("\n");
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return watch;
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}
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/*******************************************
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* Commands
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*******************************************/
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@ -238,23 +283,10 @@ void doCmdAddr() {
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// Update the LCD display
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lcdAddr(i_addr);
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// Update the serial console
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log0("%04X %04X %02X\n", i_addr);
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log0("%04X\n", i_addr);
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}
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void doCmdAddrDetail() {
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unsigned int i_addr = hwRead16(OFFSET_IAL);
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unsigned int b_addr = hwRead16(OFFSET_BAL);
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unsigned int b_mode = hwRead8(OFFSET_BM);
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// Update the LCD display
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lcdAddr(i_addr);
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// Update the serial console
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log0("%s hit at %04X", brkptStrings[b_mode], i_addr);
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if (b_mode != BRKPT_INSTR) {
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log0(" accessing %04X", b_addr);
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}
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log0("\n");
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}
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void doCmdStep(char *params) {
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long i;
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@ -308,7 +340,9 @@ void doCmdBList(char *params) {
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int i;
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if (numbkpts) {
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for (i = 0; i < numbkpts; i++) {
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log0("%d: %04X %s\n", i, breakpoints[i], brkptStrings[modes[i]]);
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log0("%d: %04X: ", i, breakpoints[i]);
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logMode(modes[i]);
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log0("\n");
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}
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} else {
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log0("No breakpoints set\n");
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@ -316,7 +350,8 @@ void doCmdBList(char *params) {
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}
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void setBreakpoint(int i, int addr, int mode) {
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log0("%s set at %04X\n", brkptStrings[mode], addr);
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logMode(mode);
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log0(" set at %04X\n", addr);
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breakpoints[i] = addr;
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modes[i] = mode;
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}
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@ -328,7 +363,8 @@ void doCmdBreak(char *params, unsigned int mode) {
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for (i = 0; i < numbkpts; i++) {
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if (breakpoints[i] == addr) {
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if (modes[i] & mode) {
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log0("%s already set at %04X\n", brkptStrings[mode], addr);
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logMode(mode);
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log0(" already set at %04X\n", addr);
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} else {
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setBreakpoint(i, addr, modes[i] | mode);
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}
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@ -355,15 +391,27 @@ void doCmdBreak(char *params, unsigned int mode) {
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}
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void doCmdBreakI(char *params) {
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doCmdBreak(params, BRKPT_INSTR);
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doCmdBreak(params, 1 << BRKPT_INSTR);
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}
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void doCmdBreakR(char *params) {
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doCmdBreak(params, BRKPT_READ);
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doCmdBreak(params, 1 << BRKPT_READ);
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}
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void doCmdBreakW(char *params) {
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doCmdBreak(params, BRKPT_WRITE);
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doCmdBreak(params, 1 << BRKPT_WRITE);
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}
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void doCmdWatchI(char *params) {
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doCmdBreak(params, 1 << WATCH_INSTR);
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}
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void doCmdWatchR(char *params) {
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doCmdBreak(params, 1 << WATCH_READ);
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}
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void doCmdWatchW(char *params) {
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doCmdBreak(params, 1 << WATCH_WRITE);
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}
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void doCmdBClear(char *params, unsigned int mode) {
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@ -379,7 +427,9 @@ void doCmdBClear(char *params, unsigned int mode) {
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}
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if (n < numbkpts) {
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if (modes[n] & mode) {
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log0("Removing %s at %04X\n", brkptStrings[mode], breakpoints[n]);
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log0("Removing ");
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logMode(mode);
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log0(" at %04X\n", breakpoints[n]);
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modes[n] &= ~mode;
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if (modes[n] == 0) {
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for (i = n; i < numbkpts; i++) {
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@ -389,24 +439,38 @@ void doCmdBClear(char *params, unsigned int mode) {
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numbkpts--;
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}
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} else {
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log0("%s not set at %04X\n", brkptStrings[mode], breakpoints[n]);
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logMode(mode);
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log0(" not set at %04X\n", breakpoints[n]);
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}
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} else {
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log0("%s not set at %04X\n", brkptStrings[mode], n);
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logMode(mode);
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log0(" not set at %04X\n", n);
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}
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doCmdBList(NULL);
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}
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void doCmdBClearI(char *params) {
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doCmdBClear(params, BRKPT_INSTR);
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doCmdBClear(params, 1 << BRKPT_INSTR);
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}
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void doCmdBClearR(char *params) {
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doCmdBClear(params, BRKPT_READ);
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doCmdBClear(params, 1 << BRKPT_READ);
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}
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void doCmdBClearW(char *params) {
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doCmdBClear(params, BRKPT_WRITE);
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doCmdBClear(params, 1 << BRKPT_WRITE);
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}
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void doCmdWClearI(char *params) {
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doCmdBClear(params, 1 << WATCH_INSTR);
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}
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void doCmdWClearR(char *params) {
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doCmdBClear(params, 1 << WATCH_READ);
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}
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void doCmdWClearW(char *params) {
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doCmdBClear(params, 1 << WATCH_WRITE);
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}
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void shiftBreakpointRegister(unsigned int addr, unsigned int mode) {
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@ -414,7 +478,7 @@ void shiftBreakpointRegister(unsigned int addr, unsigned int mode) {
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long reg = mode;
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reg <<= 16;
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reg |= addr;
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for (i = 0; i < 20; i++) {
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for (i = 0; i <= 21; i++) {
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hwCmd(CMD_LOAD_REG, reg & 1);
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reg >>= 1;
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}
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@ -444,12 +508,19 @@ void doCmdContinue(char *params) {
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// Wait for breakpoint to become active
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log0("6502 free running...\n");
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int cont = 1;
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do {
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status = STATUS_DIN;
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} while (!(status & BRKPT_ACTIVE_MASK) && !(status && BRKPT_INTERRUPTED_MASK));
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// Output cause
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doCmdAddrDetail();
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if (status & BW_ACTIVE_MASK) {
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cont = logDetails();
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hwCmd(CMD_WATCH_READ, 0);
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}
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if (status & INTERRUPTED_MASK) {
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log0("Interrupted at ");
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doCmdAddr();
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cont = 0;
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}
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} while (cont);
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// Enable single stepping
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setSingle(1);
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@ -486,9 +557,15 @@ void (*cmdFuncs[NUMCMDS])(char *params) = {
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doCmdBreakI,
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doCmdBreakR,
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doCmdBreakW,
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doCmdWatchI,
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doCmdWatchR,
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doCmdWatchW,
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doCmdBClearI,
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doCmdBClearR,
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doCmdBClearW,
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doCmdWClearI,
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doCmdWClearR,
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doCmdWClearW,
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doCmdContinue
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};
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277
ipcore_dir/WatchEvents.vhd
Normal file
277
ipcore_dir/WatchEvents.vhd
Normal file
@ -0,0 +1,277 @@
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--------------------------------------------------------------------------------
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-- This file is owned and controlled by Xilinx and must be used solely --
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-- for design, simulation, implementation and creation of design files --
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-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2015 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
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--------------------------------------------------------------------------------
|
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-- You must compile the wrapper file WatchEvents.vhd when simulating
|
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-- the core, WatchEvents. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
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|
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LIBRARY ieee;
|
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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LIBRARY XilinxCoreLib;
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-- synthesis translate_on
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ENTITY WatchEvents IS
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PORT (
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clk : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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END WatchEvents;
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|
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ARCHITECTURE WatchEvents_a OF WatchEvents IS
|
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-- synthesis translate_off
|
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COMPONENT wrapped_WatchEvents
|
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PORT (
|
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clk : IN STD_LOGIC;
|
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din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
|
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full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_WatchEvents USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
|
||||
GENERIC MAP (
|
||||
c_add_ngc_constraint => 0,
|
||||
c_application_type_axis => 0,
|
||||
c_application_type_rach => 0,
|
||||
c_application_type_rdch => 0,
|
||||
c_application_type_wach => 0,
|
||||
c_application_type_wdch => 0,
|
||||
c_application_type_wrch => 0,
|
||||
c_axi_addr_width => 32,
|
||||
c_axi_aruser_width => 1,
|
||||
c_axi_awuser_width => 1,
|
||||
c_axi_buser_width => 1,
|
||||
c_axi_data_width => 64,
|
||||
c_axi_id_width => 4,
|
||||
c_axi_ruser_width => 1,
|
||||
c_axi_type => 0,
|
||||
c_axi_wuser_width => 1,
|
||||
c_axis_tdata_width => 64,
|
||||
c_axis_tdest_width => 4,
|
||||
c_axis_tid_width => 8,
|
||||
c_axis_tkeep_width => 4,
|
||||
c_axis_tstrb_width => 4,
|
||||
c_axis_tuser_width => 4,
|
||||
c_axis_type => 0,
|
||||
c_common_clock => 1,
|
||||
c_count_type => 0,
|
||||
c_data_count_width => 10,
|
||||
c_default_value => "BlankString",
|
||||
c_din_width => 36,
|
||||
c_din_width_axis => 1,
|
||||
c_din_width_rach => 32,
|
||||
c_din_width_rdch => 64,
|
||||
c_din_width_wach => 32,
|
||||
c_din_width_wdch => 64,
|
||||
c_din_width_wrch => 2,
|
||||
c_dout_rst_val => "0",
|
||||
c_dout_width => 36,
|
||||
c_enable_rlocs => 0,
|
||||
c_enable_rst_sync => 1,
|
||||
c_error_injection_type => 0,
|
||||
c_error_injection_type_axis => 0,
|
||||
c_error_injection_type_rach => 0,
|
||||
c_error_injection_type_rdch => 0,
|
||||
c_error_injection_type_wach => 0,
|
||||
c_error_injection_type_wdch => 0,
|
||||
c_error_injection_type_wrch => 0,
|
||||
c_family => "spartan3",
|
||||
c_full_flags_rst_val => 0,
|
||||
c_has_almost_empty => 0,
|
||||
c_has_almost_full => 0,
|
||||
c_has_axi_aruser => 0,
|
||||
c_has_axi_awuser => 0,
|
||||
c_has_axi_buser => 0,
|
||||
c_has_axi_rd_channel => 0,
|
||||
c_has_axi_ruser => 0,
|
||||
c_has_axi_wr_channel => 0,
|
||||
c_has_axi_wuser => 0,
|
||||
c_has_axis_tdata => 0,
|
||||
c_has_axis_tdest => 0,
|
||||
c_has_axis_tid => 0,
|
||||
c_has_axis_tkeep => 0,
|
||||
c_has_axis_tlast => 0,
|
||||
c_has_axis_tready => 1,
|
||||
c_has_axis_tstrb => 0,
|
||||
c_has_axis_tuser => 0,
|
||||
c_has_backup => 0,
|
||||
c_has_data_count => 0,
|
||||
c_has_data_counts_axis => 0,
|
||||
c_has_data_counts_rach => 0,
|
||||
c_has_data_counts_rdch => 0,
|
||||
c_has_data_counts_wach => 0,
|
||||
c_has_data_counts_wdch => 0,
|
||||
c_has_data_counts_wrch => 0,
|
||||
c_has_int_clk => 0,
|
||||
c_has_master_ce => 0,
|
||||
c_has_meminit_file => 0,
|
||||
c_has_overflow => 0,
|
||||
c_has_prog_flags_axis => 0,
|
||||
c_has_prog_flags_rach => 0,
|
||||
c_has_prog_flags_rdch => 0,
|
||||
c_has_prog_flags_wach => 0,
|
||||
c_has_prog_flags_wdch => 0,
|
||||
c_has_prog_flags_wrch => 0,
|
||||
c_has_rd_data_count => 0,
|
||||
c_has_rd_rst => 0,
|
||||
c_has_rst => 0,
|
||||
c_has_slave_ce => 0,
|
||||
c_has_srst => 0,
|
||||
c_has_underflow => 0,
|
||||
c_has_valid => 0,
|
||||
c_has_wr_ack => 0,
|
||||
c_has_wr_data_count => 0,
|
||||
c_has_wr_rst => 0,
|
||||
c_implementation_type => 0,
|
||||
c_implementation_type_axis => 1,
|
||||
c_implementation_type_rach => 1,
|
||||
c_implementation_type_rdch => 1,
|
||||
c_implementation_type_wach => 1,
|
||||
c_implementation_type_wdch => 1,
|
||||
c_implementation_type_wrch => 1,
|
||||
c_init_wr_pntr_val => 0,
|
||||
c_interface_type => 0,
|
||||
c_memory_type => 1,
|
||||
c_mif_file_name => "BlankString",
|
||||
c_msgon_val => 1,
|
||||
c_optimization_mode => 0,
|
||||
c_overflow_low => 0,
|
||||
c_preload_latency => 0,
|
||||
c_preload_regs => 1,
|
||||
c_prim_fifo_type => "512x36",
|
||||
c_prog_empty_thresh_assert_val => 4,
|
||||
c_prog_empty_thresh_assert_val_axis => 1022,
|
||||
c_prog_empty_thresh_assert_val_rach => 1022,
|
||||
c_prog_empty_thresh_assert_val_rdch => 1022,
|
||||
c_prog_empty_thresh_assert_val_wach => 1022,
|
||||
c_prog_empty_thresh_assert_val_wdch => 1022,
|
||||
c_prog_empty_thresh_assert_val_wrch => 1022,
|
||||
c_prog_empty_thresh_negate_val => 5,
|
||||
c_prog_empty_type => 0,
|
||||
c_prog_empty_type_axis => 0,
|
||||
c_prog_empty_type_rach => 0,
|
||||
c_prog_empty_type_rdch => 0,
|
||||
c_prog_empty_type_wach => 0,
|
||||
c_prog_empty_type_wdch => 0,
|
||||
c_prog_empty_type_wrch => 0,
|
||||
c_prog_full_thresh_assert_val => 511,
|
||||
c_prog_full_thresh_assert_val_axis => 1023,
|
||||
c_prog_full_thresh_assert_val_rach => 1023,
|
||||
c_prog_full_thresh_assert_val_rdch => 1023,
|
||||
c_prog_full_thresh_assert_val_wach => 1023,
|
||||
c_prog_full_thresh_assert_val_wdch => 1023,
|
||||
c_prog_full_thresh_assert_val_wrch => 1023,
|
||||
c_prog_full_thresh_negate_val => 510,
|
||||
c_prog_full_type => 0,
|
||||
c_prog_full_type_axis => 0,
|
||||
c_prog_full_type_rach => 0,
|
||||
c_prog_full_type_rdch => 0,
|
||||
c_prog_full_type_wach => 0,
|
||||
c_prog_full_type_wdch => 0,
|
||||
c_prog_full_type_wrch => 0,
|
||||
c_rach_type => 0,
|
||||
c_rd_data_count_width => 10,
|
||||
c_rd_depth => 512,
|
||||
c_rd_freq => 1,
|
||||
c_rd_pntr_width => 9,
|
||||
c_rdch_type => 0,
|
||||
c_reg_slice_mode_axis => 0,
|
||||
c_reg_slice_mode_rach => 0,
|
||||
c_reg_slice_mode_rdch => 0,
|
||||
c_reg_slice_mode_wach => 0,
|
||||
c_reg_slice_mode_wdch => 0,
|
||||
c_reg_slice_mode_wrch => 0,
|
||||
c_synchronizer_stage => 2,
|
||||
c_underflow_low => 0,
|
||||
c_use_common_overflow => 0,
|
||||
c_use_common_underflow => 0,
|
||||
c_use_default_settings => 0,
|
||||
c_use_dout_rst => 0,
|
||||
c_use_ecc => 0,
|
||||
c_use_ecc_axis => 0,
|
||||
c_use_ecc_rach => 0,
|
||||
c_use_ecc_rdch => 0,
|
||||
c_use_ecc_wach => 0,
|
||||
c_use_ecc_wdch => 0,
|
||||
c_use_ecc_wrch => 0,
|
||||
c_use_embedded_reg => 0,
|
||||
c_use_fifo16_flags => 0,
|
||||
c_use_fwft_data_count => 1,
|
||||
c_valid_low => 0,
|
||||
c_wach_type => 0,
|
||||
c_wdch_type => 0,
|
||||
c_wr_ack_low => 0,
|
||||
c_wr_data_count_width => 10,
|
||||
c_wr_depth => 512,
|
||||
c_wr_depth_axis => 1024,
|
||||
c_wr_depth_rach => 16,
|
||||
c_wr_depth_rdch => 1024,
|
||||
c_wr_depth_wach => 16,
|
||||
c_wr_depth_wdch => 1024,
|
||||
c_wr_depth_wrch => 16,
|
||||
c_wr_freq => 1,
|
||||
c_wr_pntr_width => 9,
|
||||
c_wr_pntr_width_axis => 10,
|
||||
c_wr_pntr_width_rach => 4,
|
||||
c_wr_pntr_width_rdch => 10,
|
||||
c_wr_pntr_width_wach => 4,
|
||||
c_wr_pntr_width_wdch => 10,
|
||||
c_wr_pntr_width_wrch => 4,
|
||||
c_wr_response_latency => 1,
|
||||
c_wrch_type => 0
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_WatchEvents
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END WatchEvents_a;
|
||||
386
ipcore_dir/WatchEvents.xise
Normal file
386
ipcore_dir/WatchEvents.xise
Normal file
@ -0,0 +1,386 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="WatchEvents.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="WatchEvents.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s250e" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|WatchEvents|WatchEvents_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="WatchEvents.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/WatchEvents" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="WatchEvents" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="WatchEvents_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="WatchEvents_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="WatchEvents_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="WatchEvents_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="WatchEvents" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-10T19:17:46" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B14BB500359CAAA9F2FE2F4318B515B5" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@ -77,23 +77,26 @@ architecture behavioral of AtomBusMon is
|
||||
signal cmd : std_logic_vector(3 downto 0);
|
||||
|
||||
signal addr_sync : std_logic_vector(15 downto 0);
|
||||
|
||||
signal addr_inst : std_logic_vector(15 downto 0);
|
||||
signal addr_watch : std_logic_vector(15 downto 0);
|
||||
signal mode_watch : std_logic_vector(7 downto 0);
|
||||
|
||||
signal single : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal step : std_logic;
|
||||
|
||||
signal bw_status : std_logic_vector(19 downto 0);
|
||||
|
||||
signal brkpt_reg : std_logic_vector(87 downto 0);
|
||||
signal brkpt_enable : std_logic;
|
||||
signal brkpt_active : std_logic;
|
||||
signal brkpt_active1 : std_logic;
|
||||
signal brkpt_reg : std_logic_vector(79 downto 0);
|
||||
signal brkpt_active1 : std_logic;
|
||||
|
||||
signal watch_active : std_logic;
|
||||
signal watch_din : std_logic_vector(35 downto 0);
|
||||
signal watch_dout : std_logic_vector(35 downto 0);
|
||||
signal watch_empty : std_logic;
|
||||
signal watch_rd : std_logic;
|
||||
signal watch_wr : std_logic;
|
||||
|
||||
signal brkpt_status : std_logic_vector(19 downto 0);
|
||||
signal brkpt_status_latched : std_logic_vector(19 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
inst_dcm5 : entity work.DCM0 port map(
|
||||
@ -167,7 +170,7 @@ begin
|
||||
portdin(4) => '0',
|
||||
portdin(5) => '0',
|
||||
portdin(6) => sw1,
|
||||
portdin(7) => brkpt_active1,
|
||||
portdin(7) => not watch_empty,
|
||||
portdout => open,
|
||||
|
||||
-- Mux Port
|
||||
@ -182,6 +185,19 @@ begin
|
||||
txd => avr_TxD
|
||||
);
|
||||
|
||||
WatchEvents_inst : entity work.WatchEvents port map(
|
||||
clk => Phi2,
|
||||
din => watch_din,
|
||||
wr_en => watch_wr,
|
||||
rd_en => watch_rd,
|
||||
dout => watch_dout,
|
||||
full => open,
|
||||
empty => watch_empty
|
||||
);
|
||||
|
||||
watch_din <= bw_status & Addr when Sync = '1' else
|
||||
bw_status & addr_inst;
|
||||
|
||||
lcd_rw <= lcd_rw_int;
|
||||
lcd_db <= lcd_db_out when lcd_rw_int = '0' else (others => 'Z');
|
||||
lcd_db_in <= lcd_db;
|
||||
@ -197,59 +213,81 @@ begin
|
||||
dy_data(1) <= hex & "0000" & Addr(7 downto 4);
|
||||
dy_data(2) <= hex & "0000" & "00" & (not nsw2) & sw1;
|
||||
|
||||
mux <= addr_inst(7 downto 0) when muxsel = 0 else
|
||||
addr_inst(15 downto 8) when muxsel = 1 else
|
||||
brkpt_status_latched(7 downto 0) when muxsel = 2 else
|
||||
brkpt_status_latched(15 downto 8) when muxsel = 3 else
|
||||
addr_watch(7 downto 0) when muxsel = 4 else
|
||||
addr_watch(15 downto 8) when muxsel = 5 else
|
||||
"0000" & brkpt_status_latched(19 downto 16) when muxsel = 6 else
|
||||
mode_watch when muxsel = 7 else
|
||||
mux <= addr_inst(7 downto 0) when muxsel = 0 else
|
||||
addr_inst(15 downto 8) when muxsel = 1 else
|
||||
watch_dout(7 downto 0) when muxsel = 2 else
|
||||
watch_dout(15 downto 8) when muxsel = 3 else
|
||||
watch_dout(23 downto 16) when muxsel = 4 else
|
||||
watch_dout(31 downto 24) when muxsel = 5 else
|
||||
"0000" & watch_dout(35 downto 32) when muxsel = 6 else
|
||||
"10101010";
|
||||
|
||||
brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync)
|
||||
variable active : std_logic;
|
||||
variable bactive : std_logic;
|
||||
variable wactive : std_logic;
|
||||
variable status : std_logic_vector(19 downto 0);
|
||||
variable i : integer;
|
||||
variable brkpt_addr : std_logic_vector(15 downto 0);
|
||||
variable brkpt_mode_i : std_logic;
|
||||
variable brkpt_mode_ar : std_logic;
|
||||
variable brkpt_mode_aw : std_logic;
|
||||
variable reg_addr : std_logic_vector(15 downto 0);
|
||||
variable reg_mode_bi : std_logic;
|
||||
variable reg_mode_bar : std_logic;
|
||||
variable reg_mode_baw : std_logic;
|
||||
variable reg_mode_wi : std_logic;
|
||||
variable reg_mode_war : std_logic;
|
||||
variable reg_mode_waw : std_logic;
|
||||
begin
|
||||
active := '0';
|
||||
status := (others => '0');
|
||||
bactive := '0';
|
||||
wactive := '0';
|
||||
status := "00001010101010101010";
|
||||
if (brkpt_enable = '1') then
|
||||
for i in 0 to 3 loop
|
||||
brkpt_addr := brkpt_reg(i * 20 + 15 downto i * 20);
|
||||
brkpt_mode_i := brkpt_reg(i * 20 + 16);
|
||||
brkpt_mode_ar := brkpt_reg(i * 20 + 17);
|
||||
brkpt_mode_aw := brkpt_reg(i * 20 + 18);
|
||||
if (Addr = brkpt_addr) then
|
||||
reg_addr := brkpt_reg(i * 22 + 15 downto i * 22);
|
||||
reg_mode_bi := brkpt_reg(i * 22 + 16);
|
||||
reg_mode_bar := brkpt_reg(i * 22 + 17);
|
||||
reg_mode_baw := brkpt_reg(i * 22 + 18);
|
||||
reg_mode_wi := brkpt_reg(i * 22 + 19);
|
||||
reg_mode_war := brkpt_reg(i * 22 + 20);
|
||||
reg_mode_waw := brkpt_reg(i * 22 + 21);
|
||||
if (Addr = reg_addr) then
|
||||
if (Sync = '1') then
|
||||
if (brkpt_mode_i = '1') then
|
||||
active := '1';
|
||||
status := "0001" & brkpt_reg(i * 20 + 15 downto i * 20);
|
||||
if (reg_mode_bi = '1') then
|
||||
bactive := '1';
|
||||
status := "0001" & reg_addr;
|
||||
end if;
|
||||
if (reg_mode_wi = '1') then
|
||||
wactive := '1';
|
||||
status := "1001" & reg_addr;
|
||||
end if;
|
||||
else
|
||||
if (RNW = '1') then
|
||||
if (brkpt_mode_ar = '1') then
|
||||
active := '1';
|
||||
status := "0010" & brkpt_reg(i * 20 + 15 downto i * 20);
|
||||
if (reg_mode_bar = '1') then
|
||||
bactive := '1';
|
||||
status := "0010" & reg_addr;
|
||||
end if;
|
||||
if (reg_mode_war = '1') then
|
||||
wactive := '1';
|
||||
status := "1010" & reg_addr;
|
||||
end if;
|
||||
else
|
||||
if (brkpt_mode_aw = '1') then
|
||||
active := '1';
|
||||
status := "0100" & brkpt_reg(i * 20 + 15 downto i * 20);
|
||||
if (reg_mode_baw = '1') then
|
||||
bactive := '1';
|
||||
status := "0100" & reg_addr;
|
||||
end if;
|
||||
if (reg_mode_waw = '1') then
|
||||
wactive := '1';
|
||||
status := "1100" & reg_addr;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
brkpt_active <= active;
|
||||
brkpt_status <= status;
|
||||
watch_active <= wactive;
|
||||
brkpt_active <= bactive;
|
||||
bw_status <= status;
|
||||
end process;
|
||||
|
||||
|
||||
watch_wr <= '1' when watch_active = '1' or (brkpt_active = '1' and brkpt_active1 = '0') else '0';
|
||||
|
||||
-- 6502 Control
|
||||
syncProcess: process (Phi2)
|
||||
begin
|
||||
@ -257,12 +295,14 @@ begin
|
||||
-- Command processing
|
||||
cmd_edge1 <= cmd_edge;
|
||||
cmd_edge2 <= cmd_edge1;
|
||||
watch_rd <= '0';
|
||||
if (cmd_edge2 = '0' and cmd_edge1 = '1') then
|
||||
-- 000x Enable/Disable single strpping
|
||||
-- 001x Enable/Disable breakpoints / watches
|
||||
-- 010x Load register
|
||||
-- 011x Reset
|
||||
-- 1000 Singe Step
|
||||
-- 1000 Single Step
|
||||
-- 1001 Watch Read
|
||||
|
||||
if (cmd(3 downto 1) = "000") then
|
||||
single <= cmd(0);
|
||||
@ -279,6 +319,11 @@ begin
|
||||
if (cmd(3 downto 1) = "011") then
|
||||
reset <= cmd(0);
|
||||
end if;
|
||||
|
||||
if (cmd(3 downto 0) = "1001") then
|
||||
watch_rd <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
if (reset = '1') then
|
||||
@ -293,10 +338,9 @@ begin
|
||||
addr_inst <= Addr;
|
||||
end if;
|
||||
|
||||
if (brkpt_active = '1') then
|
||||
brkpt_status_latched <= brkpt_status;
|
||||
end if;
|
||||
-- Breakpoints and Watches written to the FIFO
|
||||
brkpt_active1 <= brkpt_active;
|
||||
|
||||
|
||||
-- Single Stepping
|
||||
if ((single = '0') or (cmd_edge2 = '0' and cmd_edge1 = '1' and cmd = "1000")) then
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user