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Eliminated some warnings - changes mostly cosmetic

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Change-Id: I141b05c932d0736e689ff3a2cb2c90c24c850933
This commit is contained in:
David Banks 2015-11-29 12:06:42 +00:00
parent 847b781708
commit de16b3af1a
10 changed files with 64 additions and 72 deletions
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64
src/AVR8/CommonPacks/std_library.vhd
View File

@ -210,32 +210,30 @@ function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_l
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
if (not (fn_det_x(vect_a) or fn_det_x(vect_b))) then
return(std_logic_vector(unsigned(vect_a) + unsigned(vect_b)));
-- pragma translate_off
else
tmp_a := (others =>'X');
tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X');
tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
end if;
return(std_logic_vector(unsigned(vect_a) + unsigned(vect_b)));
end "+";
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
if (not fn_det_x(vect)) then
return(std_logic_vector(unsigned(vect) + int));
-- pragma translate_off
else
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
-- pragma translate_on
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + int));
end "+";
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
@ -243,58 +241,54 @@ variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
if (not (fn_det_x(vect) or fn_det_x(d))) then
return(std_logic_vector(unsigned(vect) + unsigned(tmp_b)));
-- pragma translate_off
else
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_b := (others =>'X');
return(tmp_b);
-- pragma translate_on
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + unsigned(tmp_b)));
end "+";
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
if (not (fn_det_x(vect_a) or fn_det_x(vect_b))) then
return(std_logic_vector(unsigned(vect_a) - unsigned(vect_b)));
-- pragma translate_off
else
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X'); tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
end if;
return(std_logic_vector(unsigned(vect_a) - unsigned(vect_b)));
end "-";
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
if (not fn_det_x(vect)) then
return(std_logic_vector(unsigned(vect) - int));
-- pragma translate_off
else
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
-- pragma translate_on
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - int));
end "-";
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
if (not fn_det_x(vect)) then
return(std_logic_vector(int - unsigned(vect)));
-- pragma translate_off
else
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
-- pragma translate_on
end if;
-- pragma translate_on
return(std_logic_vector(int - unsigned(vect)));
end "-";
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
@ -302,13 +296,13 @@ variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
if (not (fn_det_x(vect) or fn_det_x(d))) then
return(std_logic_vector(unsigned(vect) - unsigned(tmp_b)));
-- pragma translate_off
else tmp_a := (others =>'X');
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_a := (others =>'X');
return(tmp_a);
-- pragma translate_on
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - unsigned(tmp_b)));
end "-";
end std_library;

4
src/AtomBusMon.vhd
View File

@ -72,9 +72,7 @@ begin
inst_dcm0 : entity work.DCM0 port map(
CLKIN_IN => clock49,
CLK0_OUT => clock_avr,
CLK0_OUT1 => open,
CLK2X_OUT => open
CLKFX_OUT => clock_avr
);
mon : entity work.BusMonCore

10
src/AtomCpuMon.ucf
View File

@ -1,7 +1,11 @@
NET "clock49" TNM_NET = clk_period_grp_49;
TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 500ns LOW;
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
#NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 4
@ -38,7 +42,7 @@ NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 | PERIOD = 500.0 ; # 6502 pin 37
NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37
NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40

6
src/AtomCpuMon.vhd
View File

@ -96,10 +96,8 @@ architecture behavioral of AtomCpuMon is
begin
inst_dcm0 : entity work.DCM0 port map(
CLKIN_IN => clock49,
CLK0_OUT => clock_avr,
CLK0_OUT1 => open,
CLK2X_OUT => open
CLKIN_IN => clock49,
CLKFX_OUT => clock_avr
);
core : entity work.MOS6502CpuMonCore

4
src/AtomFast6502.vhd
View File

@ -122,9 +122,7 @@ begin
inst_dcm0 : entity work.DCM0 port map(
CLKIN_IN => clock49,
CLK0_OUT => clock_avr,
CLK0_OUT1 => open,
CLK2X_OUT => open
CLKFX_OUT => clock_avr
);
inst_dcm2 : entity work.DCM2 port map(

4
src/BusMonCore.vhd
View File

@ -143,6 +143,7 @@ architecture behavioral of BusMonCore is
signal fifo_din : std_logic_vector(fifo_width - 1 downto 0);
signal fifo_dout : std_logic_vector(fifo_width - 1 downto 0);
signal fifo_empty : std_logic;
signal fifo_empty_n : std_logic;
signal fifo_rd : std_logic;
signal fifo_rd_en : std_logic;
signal fifo_wr : std_logic;
@ -234,7 +235,7 @@ begin
portdin(4) => '0',
portdin(5) => '0',
portdin(6) => sw1,
portdin(7) => not fifo_empty,
portdin(7) => fifo_empty_n,
portdout(0) => muxsel(0),
portdout(1) => muxsel(1),
@ -256,6 +257,7 @@ begin
rxd => avr_RxD,
txd => avr_TxD
);
fifo_empty_n <= not fifo_empty;
WatchEvents_inst : entity work.WatchEvents port map(
clk => busmon_clk,

17
src/DCM/DCM0.vhd
View File

@ -6,12 +6,11 @@ use UNISIM.Vcomponents.all;
entity DCM0 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
CLKFX_OUT : out std_logic);
end DCM0;
architecture BEHAVIORAL of DCM0 is
signal CLK0 : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
@ -19,15 +18,15 @@ begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
port map (I => CLKFX_BUF, O => CLKFX_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0, -- 15.855 =49.152 * 10 / 31
CLKFX_DIVIDE => 31,
CLKFX_MULTIPLY => 10,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKIN_PERIOD => 20.345,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
@ -36,7 +35,7 @@ begin
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
port map (CLKFB => CLK0,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
@ -46,8 +45,8 @@ begin
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK0 => CLK0,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,

4
src/MC6809ECpuMon.vhd
View File

@ -155,9 +155,7 @@ begin
inst_dcm0 : entity work.DCM0 port map(
CLKIN_IN => clock49,
CLK0_OUT => clock_avr,
CLK0_OUT1 => open,
CLK2X_OUT => open
CLKFX_OUT => clock_avr
);
mon : entity work.BusMonCore

19
src/MOS6502CpuMonCore.vhd
View File

@ -78,9 +78,11 @@ architecture behavioral of MOS6502CpuMonCore is
signal Data : std_logic_vector(7 downto 0);
signal Dout_int : std_logic_vector(7 downto 0);
signal R_W_n_int : std_logic;
signal Rd_n_int : std_logic;
signal Wr_n_int : std_logic;
signal Sync_int : std_logic;
signal hold : std_logic;
signal Addr_int : std_logic_vector(15 downto 0);
signal Addr_int : std_logic_vector(23 downto 0);
signal IRQ_n_sync : std_logic;
signal NMI_n_sync : std_logic;
@ -117,10 +119,10 @@ begin
busmon_clken => busmon_clken,
cpu_clk => cpu_clk,
cpu_clken => cpu_clken,
Addr => Addr_int,
Addr => Addr_int(15 downto 0),
Data => Data,
Rd_n => not R_W_n_int,
Wr_n => R_W_n_int,
Rd_n => Rd_n_int,
Wr_n => Wr_n_int,
RdIO_n => '1',
WrIO_n => '1',
Sync => Sync_int,
@ -155,6 +157,8 @@ begin
SS_Step => SS_Step,
SS_Single => SS_Single
);
Wr_n_int <= R_W_n_int;
Rd_n_int <= not R_W_n_int;
Data <= Din when R_W_n_int = '1' else Dout_int;
-- The CPU is slightly pipelined and the register update of the last
@ -199,8 +203,7 @@ begin
NMI_n => NMI_n,
R_W_n => R_W_n_int,
Sync => Sync_int,
A(23 downto 16) => open,
A(15 downto 0) => Addr_int,
A => Addr_int,
DI => Din,
DO => Dout_int,
Regs => Regs
@ -223,7 +226,7 @@ begin
Regs => Regs
);
Dout_int <= std_logic_vector(cpu_dout_us);
Addr_int <= std_logic_vector(cpu_addr_us);
Addr_int(15 downto 0) <= std_logic_vector(cpu_addr_us);
end generate;
@ -262,7 +265,7 @@ begin
end process;
R_W_n <= '1' when memory_rd1 = '1' else '0' when memory_wr1 = '1' else R_W_n_int;
Addr <= memory_addr1 when (memory_rd1 = '1' or memory_wr1 = '1') else Addr_int;
Addr <= memory_addr1 when (memory_rd1 = '1' or memory_wr1 = '1') else Addr_int(15 downto 0);
Sync <= Sync_int;
Dout <= memory_dout when memory_wr1 = '1' else Dout_int;

4
src/Z80CpuMon.vhd
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@ -145,9 +145,7 @@ begin
inst_dcm0 : entity work.DCM0 port map(
CLKIN_IN => clock49,
CLK0_OUT => clock_avr,
CLK0_OUT1 => open,
CLK2X_OUT => open
CLKFX_OUT => clock_avr
);
mon : entity work.BusMonCore