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https://github.com/hoglet67/AtomBusMon.git
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6502: Implemented go command (#12)
Change-Id: I35f3e02c54f87f19e9479985d2783e91fc681e40
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@ -50,6 +50,9 @@ char *cmdStrings[] = {
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"dis",
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"flush",
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"fill",
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#if defined(CPU_6502) || defined(CPU_65C02)
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"go",
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#endif
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"crc",
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"copy",
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"compare",
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@ -98,6 +101,9 @@ void (*cmdFuncs[])(char *params) = {
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doCmdDis,
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doCmdFlush,
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doCmdFill,
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#if defined(CPU_6502) || defined(CPU_65C02)
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doCmdGo,
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#endif
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doCmdCrc,
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doCmdCopy,
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doCmdCompare,
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@ -174,49 +180,52 @@ static const char * const argsStrings[] PROGMEM = {
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// Must be kept in step with cmdStrings (just above)
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static const uint8_t helpMeta[] PROGMEM = {
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#if defined(COMMAND_HISTORY)
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16, 7, // history
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17, 7, // history
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#endif
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15, 15, // help
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16, 15, // help
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9, 8, // continue
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21, 7, // next
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29, 6, // step
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24, 7, // regs
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22, 7, // next
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30, 6, // step
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25, 7, // regs
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12, 10, // dis
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14, 7, // flush
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15, 7, // flush
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13, 11, // fill
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#if defined(CPU_6502) || defined(CPU_65C02)
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14, 0, // go
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#endif
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11, 9, // crc
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10, 13, // copy
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8, 13, // compare
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20, 1, // mem
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23, 2, // rd
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38, 3, // wr
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21, 1, // mem
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24, 2, // rd
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39, 3, // wr
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#if defined(CPU_Z80)
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18, 1, // io
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17, 2, // in
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22, 3, // out
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19, 1, // io
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18, 2, // in
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23, 3, // out
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#endif
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30, 12, // test
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19, 0, // load
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26, 9, // save
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28, 7, // srec
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27, 14, // special
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25, 7, // reset
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31, 6, // trace
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31, 12, // test
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20, 0, // load
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27, 9, // save
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29, 7, // srec
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28, 14, // special
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26, 7, // reset
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32, 6, // trace
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1, 7, // blist
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6, 4, // breakx
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37, 4, // watchx
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38, 4, // watchx
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4, 4, // breakr
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35, 4, // watchr
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36, 4, // watchr
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5, 4, // breakw
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36, 4, // watchw
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37, 4, // watchw
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#if defined(CPU_Z80)
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2, 4, // breaki
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33, 4, // watchi
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3, 4, // breako
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34, 4, // watcho
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35, 4, // watcho
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#endif
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7, 0, // clear
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32, 5, // trigger
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33, 5, // trigger
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0, 0
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};
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@ -263,7 +272,10 @@ static const uint8_t helpMeta[] PROGMEM = {
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// 10101 Read IO and Auto Inc Address
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// 10110 Write IO
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// 10111 Write IO and Auto Inc Address
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// 11xxx Unused
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// 11000 Exec Go
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// 11xx1 Unused
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// 11x1x Unused
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// 111xx Unused
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#define CMD_SINGLE_ENABLE 0x00
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#define CMD_BRKPT_ENABLE 0x02
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@ -281,6 +293,7 @@ static const uint8_t helpMeta[] PROGMEM = {
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#define CMD_RD_IO_INC 0x15
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#define CMD_WR_IO 0x16
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#define CMD_WR_IO_INC 0x17
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#define CMD_EXEC_GO 0x18
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/********************************************************
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* AVR Status Register Definitions
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@ -1451,6 +1464,19 @@ void doCmdFill(char *params) {
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}
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}
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#if defined(CPU_6502) || defined(CPU_65C02)
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void doCmdGo(char *params) {
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addr_t addr;
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params = parsehex4(params, &addr);
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loadData(0x4C);
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loadAddr(addr);
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hwCmd(CMD_EXEC_GO, 0);
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logAddr();
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}
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#endif
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void doCmdCrc(char *params) {
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long i;
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uint8_t j;
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@ -55,6 +55,7 @@ void doCmdCrc(char *params);
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void doCmdDis(char *params);
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void doCmdFlush(char *params);
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void doCmdFill(char *params);
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void doCmdGo(char *params);
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void doCmdHelp(char *params);
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#if defined(COMMAND_HISTORY)
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void doCmdHistory(char *params);
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@ -65,6 +65,7 @@ entity BusMonCore is
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WrMemOut : out std_logic;
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RdIOOut : out std_logic;
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WrIOOut : out std_logic;
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ExecOut : out std_logic;
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AddrOut : out std_logic_vector(15 downto 0);
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DataOut : out std_logic_vector(7 downto 0);
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DataIn : in std_logic_vector(7 downto 0);
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@ -164,6 +165,7 @@ architecture behavioral of BusMonCore is
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signal memory_wr : std_logic;
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signal io_rd : std_logic;
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signal io_wr : std_logic;
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signal exec : std_logic;
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signal addr_dout_reg : std_logic_vector(23 downto 0);
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signal din_reg : std_logic_vector(7 downto 0);
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@ -448,7 +450,10 @@ begin
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-- 10101 Read IO and Auto Inc Address
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-- 10110 Write IO
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-- 10111 Write IO and Auto Inc Address
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-- 11xxx Unused
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-- 11000 Exec Go
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-- 111xx Unused
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-- 11x1x Unused
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-- 11xx1 Unused
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cpuProcess: process (busmon_clk)
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begin
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@ -471,6 +476,7 @@ begin
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memory_wr <= '0';
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io_rd <= '0';
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io_wr <= '0';
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exec <= '0';
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SS_Step <= '0';
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if (cmd_edge2 /= cmd_edge1) then
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if (cmd(4 downto 1) = "0000") then
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@ -521,6 +527,10 @@ begin
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auto_inc <= cmd(0);
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end if;
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if (cmd(4 downto 0) = "11000") then
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exec <= '1';
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end if;
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-- Acknowlege certain commands immediately
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if cmd(4) = '0' then
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cmd_ack <= not cmd_ack;
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@ -595,6 +605,7 @@ begin
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AddrOut <= addr_dout_reg(23 downto 8);
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DataOut <= addr_dout_reg(7 downto 0);
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SS_Single <= single;
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ExecOut <= exec;
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-- Reset Logic
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-- Generate a short (~1ms @ 1MHz) power up reset pulse
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@ -73,12 +73,13 @@ end MOS6502CpuMonCore;
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architecture behavioral of MOS6502CpuMonCore is
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type state_type is (idle, nop0, nop1, rd, wr);
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type state_type is (idle, nop0, nop1, rd, wr, exec1, exec2);
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signal state : state_type;
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signal cpu_clken_ss : std_logic;
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signal Data : std_logic_vector(7 downto 0);
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signal Din_int : std_logic_vector(7 downto 0);
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signal Dout_int : std_logic_vector(7 downto 0);
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signal R_W_n_int : std_logic;
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signal Rd_n_int : std_logic;
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@ -111,6 +112,9 @@ architecture behavioral of MOS6502CpuMonCore is
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signal NMI_n_masked : std_logic;
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signal IRQ_n_masked : std_logic;
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signal exec : std_logic;
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signal exec_held : std_logic;
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begin
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mon : entity work.BusMonCore
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@ -151,6 +155,7 @@ begin
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WrMemOut => memory_wr,
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RdIOOut => open,
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WrIOOut => open,
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ExecOut => exec,
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AddrOut => memory_addr,
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DataOut => memory_dout,
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DataIn => memory_din,
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@ -192,7 +197,7 @@ begin
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Regs1( 63 downto 48) <= last_PC;
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Regs1(255 downto 64) <= (others => '0');
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cpu_clken_ss <= '1' when Rdy = '1' and (state = idle) and cpu_clken = '1' else '0';
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cpu_clken_ss <= '1' when Rdy = '1' and (state = idle or state = exec1 or state = exec2) and cpu_clken = '1' else '0';
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GenT65Core: if UseT65Core generate
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inst_t65: entity work.T65 port map (
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@ -208,7 +213,7 @@ begin
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R_W_n => R_W_n_int,
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Sync => Sync_int,
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A => Addr_int,
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DI => Din,
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DI => Din_int,
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DO => Dout_int,
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Regs => Regs
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);
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@ -221,7 +226,7 @@ begin
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enable => cpu_clken_ss,
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nmi_n => NMI_n_masked,
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irq_n => IRQ_n_masked,
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di => unsigned(Din),
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di => unsigned(Din_int),
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do => cpu_dout_us,
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addr => cpu_addr_us,
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nwe => R_W_n_int,
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@ -233,6 +238,11 @@ begin
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Addr_int(15 downto 0) <= std_logic_vector(cpu_addr_us);
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end generate;
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Din_int <= memory_dout( 7 downto 0) when state = idle and Sync_int = '1' and exec_held = '1' else
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memory_addr( 7 downto 0) when state = exec1 else
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memory_addr(15 downto 8) when state = exec2 else
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Din;
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men_access_machine : process(cpu_clk, cpu_reset_n)
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begin
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if cpu_reset_n = '0' then
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@ -255,12 +265,21 @@ begin
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elsif state = wr then
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memory_wr1 <= '0';
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end if;
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if exec = '1' then
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exec_held <= '1';
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elsif state = exec1 then
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exec_held <= '0';
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end if;
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if cpu_clken = '1' and Rdy = '1' then
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case state is
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-- idle is when the CPU is running normally
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when idle =>
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if Sync_int = '1' and SS_Single = '1' then
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state <= nop0;
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if Sync_int = '1' then
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if exec_held = '1' then
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state <= exec1;
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elsif SS_Single = '1' then
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state <= nop0;
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end if;
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end if;
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-- nop0 is the first state entered when the CPU is paused
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when nop0 =>
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@ -268,7 +287,7 @@ begin
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state <= rd;
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elsif memory_wr1 = '1' then
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state <= wr;
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elsif SS_Step_held = '1' then
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elsif SS_Step_held = '1' or exec_held = '1' then
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state <= idle;
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else
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state <= nop1;
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@ -282,6 +301,12 @@ begin
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-- wr is a monitor initiated write cycle
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when wr =>
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state <= nop0;
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-- exec1 is the LSB of a forced JMP
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when exec1 =>
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state <= exec2;
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-- exec2 is the MSB of a forced JMP
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when exec2 =>
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state <= idle;
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end case;
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end if;
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end if;
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@ -289,7 +314,7 @@ begin
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-- Only count cycles when the 6502 is actually running
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-- TODO: Should this be qualified with cpu_clken and rdy?
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CountCycle <= '1' when state = idle else '0';
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CountCycle <= '1' when state = idle or state = exec1 or state = exec2 else '0';
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R_W_n <= R_W_n_int when state = idle else
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'0' when state = wr else
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@ -308,7 +333,7 @@ begin
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-- Data is captured by the bus monitor on the rising edge of cpu_clk
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-- that sees done = 1.
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memory_done <= '1' when state = rd or state = wr else '0';
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memory_done <= '1' when state = rd or state = wr or state = exec2 else '0';
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memory_din <= Din;
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