6502: Added special command to inhibit IRQ/NMI

Change-Id: I6ba8a1b3b92e5852382d35eee7a59b6a9d7e63e8
This commit is contained in:
David Banks 2019-06-15 17:50:29 +01:00
parent e9d4e98b96
commit efdd41a239
4 changed files with 121 additions and 84 deletions

View File

@ -10,7 +10,7 @@
* VERSION and NAME are used in the start-up message
********************************************************/
#define VERSION "0.73"
#define VERSION "0.74"
#if (CPU == Z80)
#define NAME "ICE-T80"
@ -28,9 +28,9 @@
#ifdef CPUEMBEDDED
#if (CPU == Z80)
#define NUM_CMDS 30
#define NUM_CMDS 31
#else
#define NUM_CMDS 23
#define NUM_CMDS 24
#endif
#else
#define NUM_CMDS 14
@ -59,6 +59,7 @@ char *cmdStrings[NUM_CMDS] = {
#endif
"test",
"srec",
"special",
#endif
"reset",
"trace",
@ -99,6 +100,7 @@ void (*cmdFuncs[NUM_CMDS])(char *params) = {
#endif
doCmdTest,
doCmdSRec,
doCmdSpecial,
#endif
doCmdReset,
doCmdTrace,
@ -132,9 +134,14 @@ void (*cmdFuncs[NUM_CMDS])(char *params) = {
#define CMD_EDGE 0x20
// Commands are placed on bits 4..0
// Currently bits 6 and 7 are unused
#define CMD_MASK 0x3F
// Bits 7..6 are the special function output bits
// On the 6502, these are used to mask IRQ and NMI
#define SPECIAL_0 6
#define SPECIAL_1 7
#define SPECIAL_MASK ((1<<SPECIAL_0) | (1<<SPECIAL_1))
// Hardware Commands:
//
// 0000x Enable/Disable single strpping
@ -1157,6 +1164,30 @@ void doCmdSRec(char *params) {
}
void logSpecial(char *function, int value) {
log0("%s", function);
if (value) {
log0(" inhibited\n");
} else {
log0(" enabled\n");
}
}
void doCmdSpecial(char *params) {
#if (CPU == 6502)
int special = -1;
sscanf(params, "%x", &special);
if (special >= 0 && special <= 3) {
CTRL_PORT &= ~SPECIAL_MASK;
CTRL_PORT = (CTRL_PORT & ~SPECIAL_MASK) | (special << SPECIAL_0);
}
logSpecial("NMI", CTRL_PORT & (1 << SPECIAL_1));
logSpecial("IRQ", CTRL_PORT & (1 << SPECIAL_0));
#else
log0("Special functions not implemented\n");
#endif
}
#endif // CPUEMBEDDED
void doCmdTrace(char *params) {

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@ -57,6 +57,7 @@ void doCmdReset(char *params);
void doCmdStep(char *params);
void doCmdTest(char *params);
void doCmdSRec(char *params);
void doCmdSpecial(char *params);
void doCmdTrace(char *params);
void doCmdTrigger(char *params);
void doCmdWatchI(char *params);

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@ -67,6 +67,9 @@ entity BusMonCore is
DataIn : in std_logic_vector(7 downto 0);
Done : in std_logic;
-- Special outputs (function is CPU specific)
Special : out std_logic_vector(1 downto 0);
-- Single Step interface
SS_Single : out std_logic;
SS_Step : out std_logic;
@ -224,8 +227,8 @@ begin
portbout(3) => cmd(3),
portbout(4) => cmd(4),
portbout(5) => cmd_edge,
portbout(6) => unused_b6,
portbout(7) => unused_b7,
portbout(6) => Special(0),
portbout(7) => Special(1),
-- Status Port
portdin(0) => '0',
@ -558,5 +561,3 @@ begin
SS_Single <= single;
end behavioral;

View File

@ -83,8 +83,6 @@ architecture behavioral of MOS6502CpuMonCore is
signal Sync_int : std_logic;
signal hold : std_logic;
signal Addr_int : std_logic_vector(23 downto 0);
signal IRQ_n_sync : std_logic;
signal NMI_n_sync : std_logic;
signal cpu_addr_us: unsigned (15 downto 0);
signal cpu_dout_us: unsigned (7 downto 0);
@ -95,6 +93,7 @@ architecture behavioral of MOS6502CpuMonCore is
signal SS_Single : std_logic;
signal SS_Step : std_logic;
signal CountCycle : std_logic;
signal special : std_logic_vector(1 downto 0);
signal memory_rd : std_logic;
signal memory_rd1 : std_logic;
@ -106,6 +105,9 @@ architecture behavioral of MOS6502CpuMonCore is
signal memory_din : std_logic_vector(7 downto 0);
signal memory_done : std_logic;
signal NMI_n_masked : std_logic;
signal IRQ_n_masked : std_logic;
begin
mon : entity work.BusMonCore
@ -154,12 +156,15 @@ begin
DataOut => memory_dout,
DataIn => memory_din,
Done => memory_done,
Special => special,
SS_Step => SS_Step,
SS_Single => SS_Single
);
Wr_n_int <= R_W_n_int;
Rd_n_int <= not R_W_n_int;
Data <= Din when R_W_n_int = '1' else Dout_int;
NMI_n_masked <= NMI_n or special(1);
IRQ_n_masked <= IRQ_n or special(0);
-- The CPU is slightly pipelined and the register update of the last
-- instruction overlaps with the opcode fetch of the next instruction.
@ -199,8 +204,8 @@ begin
Enable => cpu_clken_ss,
Clk => cpu_clk,
Rdy => '1',
IRQ_n => IRQ_n,
NMI_n => NMI_n,
IRQ_n => IRQ_n_masked,
NMI_n => NMI_n_masked,
R_W_n => R_W_n_int,
Sync => Sync_int,
A => Addr_int,
@ -215,8 +220,8 @@ begin
reset => Res_n_in,
clk => cpu_clk,
enable => cpu_clken_ss,
nmi_n => NMI_n,
irq_n => IRQ_n,
nmi_n => NMI_n_masked,
irq_n => IRQ_n_masked,
di => unsigned(Din),
do => cpu_dout_us,
addr => cpu_addr_us,
@ -275,4 +280,3 @@ begin
memory_din <= Din;
end behavioral;