Updated XPM_T65 to 0.998

Change-Id: I3152215ec4d3d2148c23a4ecb1a6eefcd79329af

.gitignore

@@ -8,6 +8,7 @@ nohup.out
 target/**/*.o
 target/**/*.bit
 target/**/*.mcs
+target/**/*.bin
 target/**/avr_progmem.*
 target/*/ipcore/WatchEvents.asy
 target/*/ipcore/WatchEvents.gise

firmware/AtomBusMon.h

@@ -1,13 +1,20 @@
 #ifndef __ATOMBUSMON_DEFINES__
 #define __ATOMBUSMON_DEFINES__
 
+#include <stdio.h>
+
+typedef uint8_t  data_t;
+typedef uint16_t addr_t;
+typedef uint8_t  offset_t;
+typedef uint16_t modes_t;
+typedef uint8_t  trigger_t;
+typedef uint16_t cmd_t;
+typedef uint16_t param_t;
+typedef int16_t  bknum_t;
+
 #include "status.h"
 #include "dis.h"
 
-#ifdef LCD
-#include "hd44780.h"
-#endif
-
 // The Atom CRC Polynomial
 #define CRC_POLY          0x002d
 
@@ -21,43 +28,56 @@
           __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000.0 * __ms)+1);\
     else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000.0 * __ms))
 
-unsigned int hwRead8(unsigned int offset);
-unsigned int hwRead16(unsigned int offset);
 
-#ifdef CPUEMBEDDED
-unsigned int disMem(unsigned int addr);
-void loadData(unsigned int data);
-void loadAddr(unsigned int addr);
-unsigned int readMemByte();
-unsigned int readMemByteInc();
+uint8_t hwRead8(offset_t offset);
+uint16_t hwRead16(offset_t offset);
+
+addr_t disMem(addr_t addr);
+void loadData(data_t data);
+void loadAddr(addr_t addr);
+data_t readMemByte();
+data_t readMemByteInc();
 void writeMemByte();
 void writeMemByteInc();
-unsigned int disMem(unsigned int addr);
-#endif
+addr_t disMem(addr_t addr);
 
-void doCmdBreak(char *params, unsigned int mode);
+void doCmdBreak(char *params, modes_t mode);
 void doCmdBreakI(char *params);
 void doCmdBreakRdIO(char *params);
 void doCmdBreakRdMem(char *params);
 void doCmdBreakWrIO(char *params);
 void doCmdBreakWrMem(char *params);
 void doCmdClear(char *params);
+void doCmdCompare(char *params);
 void doCmdContinue(char *params);
+void doCmdCopy(char *params);
 void doCmdCrc(char *params);
 void doCmdDis(char *params);
+void doCmdExec(char *params);
+void doCmdFlush(char *params);
 void doCmdFill(char *params);
+void doCmdGo(char *params);
 void doCmdHelp(char *params);
+#if defined(COMMAND_HISTORY)
+void doCmdHistory(char *params);
+void helpForCommand(uint8_t i);
+#endif
 void doCmdIO(char *params);
 void doCmdList(char *params);
+void doCmdLoad(char *params);
 void doCmdMem(char *params);
+void doCmdMode(char *params);
+void doCmdNext(char *params);
 void doCmdReadIO(char *params);
 void doCmdReadMem(char *params);
 void doCmdRegs(char *params);
 void doCmdReset(char *params);
 void doCmdStep(char *params);
 void doCmdTest(char *params);
+void doCmdSave(char *params);
 void doCmdSRec(char *params);
-void doCmdSpecial(char *params);
+void doCmdTimerMode(char *params);
+void doCmdTimeout(char *params);
 void doCmdTrace(char *params);
 void doCmdTrigger(char *params);
 void doCmdWatchI(char *params);
@@ -67,5 +87,9 @@ void doCmdWatchWrIO(char *params);
 void doCmdWatchWrMem(char *params);
 void doCmdWriteIO(char *params);
 void doCmdWriteMem(char *params);
+void doCmdXCmd0(char *params);
+void doCmdXCmd1(char *params);
+void doCmdXCmd2(char *params);
+void doCmdXCmd3(char *params);
 
 #endif

firmware/dis.h

@@ -1,6 +1,15 @@
 #ifndef __DIS_DEFINES__
 #define __DIS_DEFINES__
 
-unsigned int disassemble(unsigned int addr);
+// The processor dependent config/status port
+#define PDC_PORT         PORTA
+#define PDC_DDR          DDRA
+#define PDC_DIN          PINA
+
+#define MODE_NORMAL      0
+#define MODE_DIS_CMD     1
+
+addr_t disassemble(addr_t addr, uint8_t m);
+
 
 #endif

firmware/dis6502.c

@@ -2,9 +2,9 @@
 #include "AtomBusMon.h"
 
 enum
-{
-  IMP, IMPA, MARK2, BRA, IMM, ZP, ZPX, ZPY, INDX, INDY, IND, MARK3, ABS, ABSX, ABSY, IND16, IND1X
-};
+  {
+    IMP, IMPA, MARK2, BRA, IMM, ZP, ZPX, ZPY, INDX, INDY, MARK3, ABS, ABSX, ABSY, IND16
+  };
 
 enum
   {
@@ -18,7 +18,6 @@ enum
     I_BMI,
     I_BNE,
     I_BPL,
-    I_BRA,
     I_BRK,
     I_BVC,
     I_BVS,
@@ -46,12 +45,8 @@ enum
     I_ORA,
     I_PHA,
     I_PHP,
-    I_PHX,
-    I_PHY,
     I_PLA,
     I_PLP,
-    I_PLX,
-    I_PLY,
     I_ROL,
     I_ROR,
     I_RTI,
@@ -61,19 +56,14 @@ enum
     I_SED,
     I_SEI,
     I_STA,
-    I_STP,
     I_STX,
     I_STY,
-    I_STZ,
     I_TAX,
     I_TAY,
-    I_TRB,
-    I_TSB,
     I_TSX,
     I_TXA,
     I_TXS,
     I_TYA,
-    I_WAI,
     I_XXX
   };
 
@@ -88,7 +78,6 @@ BIT\
 BMI\
 BNE\
 BPL\
-BRA\
 BRK\
 BVC\
 BVS\
@@ -116,12 +105,8 @@ NOP\
 ORA\
 PHA\
 PHP\
-PHX\
-PHY\
 PLA\
 PLP\
-PLX\
-PLY\
 ROL\
 ROR\
 RTI\
@@ -131,141 +116,177 @@ SEC\
 SED\
 SEI\
 STA\
-STP\
 STX\
 STY\
-STZ\
 TAX\
 TAY\
-TRB\
-TSB\
 TSX\
 TXA\
 TXS\
 TYA\
-WAI\
 ---\
 ";
 
 static const unsigned char dopname[256] PROGMEM =
 {
-/*00*/ I_BRK, I_ORA, I_XXX, I_XXX, I_TSB, I_ORA, I_ASL, I_XXX, I_PHP, I_ORA, I_ASL, I_XXX, I_TSB, I_ORA, I_ASL, I_XXX,
-/*10*/ I_BPL, I_ORA, I_ORA, I_XXX, I_TRB, I_ORA, I_ASL, I_XXX, I_CLC, I_ORA, I_INC, I_XXX, I_TRB, I_ORA, I_ASL, I_XXX,
+/*00*/ I_BRK, I_ORA, I_XXX, I_XXX, I_XXX, I_ORA, I_ASL, I_XXX, I_PHP, I_ORA, I_ASL, I_XXX, I_XXX, I_ORA, I_ASL, I_XXX,
+/*10*/ I_BPL, I_ORA, I_XXX, I_XXX, I_XXX, I_ORA, I_ASL, I_XXX, I_CLC, I_ORA, I_XXX, I_XXX, I_XXX, I_ORA, I_ASL, I_XXX,
 /*20*/ I_JSR, I_AND, I_XXX, I_XXX, I_BIT, I_AND, I_ROL, I_XXX, I_PLP, I_AND, I_ROL, I_XXX, I_BIT, I_AND, I_ROL, I_XXX,
-/*30*/ I_BMI, I_AND, I_AND, I_XXX, I_BIT, I_AND, I_ROL, I_XXX, I_SEC, I_AND, I_DEC, I_XXX, I_BIT, I_AND, I_ROL, I_XXX,
+/*30*/ I_BMI, I_AND, I_XXX, I_XXX, I_XXX, I_AND, I_ROL, I_XXX, I_SEC, I_AND, I_XXX, I_XXX, I_XXX, I_AND, I_ROL, I_XXX,
 /*40*/ I_RTI, I_EOR, I_XXX, I_XXX, I_XXX, I_EOR, I_LSR, I_XXX, I_PHA, I_EOR, I_LSR, I_XXX, I_JMP, I_EOR, I_LSR, I_XXX,
-/*50*/ I_BVC, I_EOR, I_EOR, I_XXX, I_XXX, I_EOR, I_LSR, I_XXX, I_CLI, I_EOR, I_PHY, I_XXX, I_XXX, I_EOR, I_LSR, I_XXX,
-/*60*/ I_RTS, I_ADC, I_XXX, I_XXX, I_STZ, I_ADC, I_ROR, I_XXX, I_PLA, I_ADC, I_ROR, I_XXX, I_JMP, I_ADC, I_ROR, I_XXX,
-/*70*/ I_BVS, I_ADC, I_ADC, I_XXX, I_STZ, I_ADC, I_ROR, I_XXX, I_SEI, I_ADC, I_PLY, I_XXX, I_JMP, I_ADC, I_ROR, I_XXX,
-/*80*/ I_BRA, I_STA, I_XXX, I_XXX, I_STY, I_STA, I_STX, I_XXX, I_DEY, I_BIT, I_TXA, I_XXX, I_STY, I_STA, I_STX, I_XXX,
-/*90*/ I_BCC, I_STA, I_STA, I_XXX, I_STY, I_STA, I_STX, I_XXX, I_TYA, I_STA, I_TXS, I_XXX, I_STZ, I_STA, I_STZ, I_XXX,
+/*50*/ I_BVC, I_EOR, I_XXX, I_XXX, I_XXX, I_EOR, I_LSR, I_XXX, I_CLI, I_EOR, I_XXX, I_XXX, I_XXX, I_EOR, I_LSR, I_XXX,
+/*60*/ I_RTS, I_ADC, I_XXX, I_XXX, I_XXX, I_ADC, I_ROR, I_XXX, I_PLA, I_ADC, I_ROR, I_XXX, I_JMP, I_ADC, I_ROR, I_XXX,
+/*70*/ I_BVS, I_ADC, I_XXX, I_XXX, I_XXX, I_ADC, I_ROR, I_XXX, I_SEI, I_ADC, I_XXX, I_XXX, I_XXX, I_ADC, I_ROR, I_XXX,
+/*80*/ I_XXX, I_STA, I_XXX, I_XXX, I_STY, I_STA, I_STX, I_XXX, I_DEY, I_XXX, I_TXA, I_XXX, I_STY, I_STA, I_STX, I_XXX,
+/*90*/ I_BCC, I_STA, I_XXX, I_XXX, I_STY, I_STA, I_STX, I_XXX, I_TYA, I_STA, I_TXS, I_XXX, I_XXX, I_STA, I_XXX, I_XXX,
 /*A0*/ I_LDY, I_LDA, I_LDX, I_XXX, I_LDY, I_LDA, I_LDX, I_XXX, I_TAY, I_LDA, I_TAX, I_XXX, I_LDY, I_LDA, I_LDX, I_XXX,
-/*B0*/ I_BCS, I_LDA, I_LDA, I_XXX, I_LDY, I_LDA, I_LDX, I_XXX, I_CLV, I_LDA, I_TSX, I_XXX, I_LDY, I_LDA, I_LDX, I_XXX,
-/*C0*/ I_CPY, I_CMP, I_XXX, I_XXX, I_CPY, I_CMP, I_DEC, I_XXX, I_INY, I_CMP, I_DEX, I_WAI, I_CPY, I_CMP, I_DEC, I_XXX,
-/*D0*/ I_BNE, I_CMP, I_CMP, I_XXX, I_XXX, I_CMP, I_DEC, I_XXX, I_CLD, I_CMP, I_PHX, I_STP, I_XXX, I_CMP, I_DEC, I_XXX,
+/*B0*/ I_BCS, I_LDA, I_XXX, I_XXX, I_LDY, I_LDA, I_LDX, I_XXX, I_CLV, I_LDA, I_TSX, I_XXX, I_LDY, I_LDA, I_LDX, I_XXX,
+/*C0*/ I_CPY, I_CMP, I_XXX, I_XXX, I_CPY, I_CMP, I_DEC, I_XXX, I_INY, I_CMP, I_DEX, I_XXX, I_CPY, I_CMP, I_DEC, I_XXX,
+/*D0*/ I_BNE, I_CMP, I_XXX, I_XXX, I_XXX, I_CMP, I_DEC, I_XXX, I_CLD, I_CMP, I_XXX, I_XXX, I_XXX, I_CMP, I_DEC, I_XXX,
 /*E0*/ I_CPX, I_SBC, I_XXX, I_XXX, I_CPX, I_SBC, I_INC, I_XXX, I_INX, I_SBC, I_NOP, I_XXX, I_CPX, I_SBC, I_INC, I_XXX,
-/*F0*/ I_BEQ, I_SBC, I_SBC, I_XXX, I_XXX, I_SBC, I_INC, I_XXX, I_SED, I_SBC, I_PLX, I_XXX, I_XXX, I_SBC, I_INC, I_XXX
+/*F0*/ I_BEQ, I_SBC, I_XXX, I_XXX, I_XXX, I_SBC, I_INC, I_XXX, I_SED, I_SBC, I_XXX, I_XXX, I_XXX, I_SBC, I_INC, I_XXX
 };
 
 static const unsigned char dopaddr[256] PROGMEM =
 {
-/*00*/ IMP, INDX,  IMP, IMP,  ZP,   ZP,	   ZP,	 IMP,	IMP,  IMM,   IMPA,  IMP,  ABS,	  ABS,	 ABS,  IMP,
-/*10*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,	 IMP,	IMP,  ABSY,  IMPA,  IMP,  ABS,	  ABSX,	 ABSX, IMP,
-/*20*/ ABS, INDX,  IMP, IMP,  ZP,   ZP,	   ZP,	 IMP,	IMP,  IMM,   IMPA,  IMP,  ABS,	  ABS,	 ABS,  IMP,
-/*30*/ BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPX,	 IMP,	IMP,  ABSY,  IMPA,  IMP,  ABSX,	  ABSX,	 ABSX, IMP,
-/*40*/ IMP, INDX,  IMP, IMP,  ZP,   ZP,	   ZP,	 IMP,	IMP,  IMM,   IMPA,  IMP,  ABS,	  ABS,	 ABS,  IMP,
-/*50*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,	 IMP,	IMP,  ABSY,  IMP,   IMP,  ABS,	  ABSX,	 ABSX, IMP,
-/*60*/ IMP, INDX,  IMP, IMP,  ZP,   ZP,	   ZP,	 IMP,	IMP,  IMM,   IMPA,  IMP,  IND16,  ABS,	 ABS,  IMP,
-/*70*/ BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPX,	 IMP,	IMP,  ABSY,  IMP,   IMP,  IND1X,  ABSX,	 ABSX, IMP,
-/*80*/ BRA, INDX,  IMP, IMP,  ZP,   ZP,	   ZP,	 IMP,	IMP,  IMM,   IMP,   IMP,  ABS,	  ABS,	 ABS,  IMP,
-/*90*/ BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPY,	 IMP,	IMP,  ABSY,  IMP,   IMP,  ABS,	  ABSX,	 ABSX, IMP,
-/*A0*/ IMM, INDX,  IMM, IMP,  ZP,   ZP,	   ZP,	 IMP,	IMP,  IMM,   IMP,   IMP,  ABS,	  ABS,	 ABS,  IMP,
-/*B0*/ BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPY,	 IMP,	IMP,  ABSY,  IMP,   IMP,  ABSX,	  ABSX,	 ABSY, IMP,
-/*C0*/ IMM, INDX,  IMP, IMP,  ZP,   ZP,	   ZP,	 IMP,	IMP,  IMM,   IMP,   IMP,  ABS,	  ABS,	 ABS,  IMP,
-/*D0*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,	 IMP,	IMP,  ABSY,  IMP,   IMP,  ABS,	  ABSX,	 ABSX, IMP,
-/*E0*/ IMM, INDX,  IMP, IMP,  ZP,   ZP,	   ZP,	 IMP,	IMP,  IMM,   IMP,   IMP,  ABS,	  ABS,	 ABS,  IMP,
-/*F0*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,	 IMP,	IMP,  ABSY,  IMP,   IMP,  ABS,	  ABSX,	 ABSX, IMP
+/*00*/ IMM, INDX,  IMP, IMP,  IMP,  ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  IMP,    ABS,   ABS,  IMP,
+/*10*/ BRA, INDY,  IMP, IMP,  IMP,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  IMP,    ABSX,  ABSX, IMP,
+/*20*/ ABS, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
+/*30*/ BRA, INDY,  IMP, IMP,  IMP,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  IMP,    ABSX,  ABSX, IMP,
+/*40*/ IMP, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
+/*50*/ BRA, INDY,  IMP, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP,
+/*60*/ IMP, INDX,  IMP, IMP,  IMP,  ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  IND16,  ABS,   ABS,  IMP,
+/*70*/ BRA, INDY,  IMP, IMP,  IMP,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  IMP,    ABSX,  ABSX, IMP,
+/*80*/ IMP, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMP,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+/*90*/ BRA, INDY,  IMP, IMP,  ZPX,  ZPX,   ZPY,  IMP,   IMP,  ABSY,  IMP,   IMP,  IMP,    ABSX,  IMP,  IMP,
+/*A0*/ IMM, INDX,  IMM, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+/*B0*/ BRA, INDY,  IMP, IMP,  ZPX,  ZPX,   ZPY,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABSX,   ABSX,  ABSY, IMP,
+/*C0*/ IMM, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+/*D0*/ BRA, INDY,  IMP, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP,
+/*E0*/ IMM, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+/*F0*/ BRA, INDY,  IMP, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP
 };
 
-unsigned int disassemble(unsigned int addr)
+addr_t disassemble(addr_t addr, uint8_t m)
 {
-  
-	unsigned int temp;
-	unsigned int op = readMemByteInc();
-        int mode = pgm_read_byte(dopaddr + op);
-	unsigned int p1 = (mode > MARK2) ? readMemByteInc() : 0;
-	unsigned int p2 = (mode > MARK3) ? readMemByteInc() : 0;
 
-	int opIndex = pgm_read_byte(dopname + op) * 3;
-	log0("%04X : ", addr);
-	for (temp = 0; temp < 3; temp++) {
-	  log0("%c", pgm_read_byte(opString + opIndex + temp));
-	}
-	log0(" ");
+  char buffer[40];
+  uint8_t temp;
+  data_t op = readMemByteInc();
+  data_t p1 = 0;
+  data_t p2 = 0;
+  uint8_t mode = pgm_read_byte(dopaddr + op);
+  char *ptr;
 
-	switch (mode)
-	{
-	case IMP:
-		log0("        ");
-		break;
-	case IMPA:
-		log0("A       ");
-		break;
-	case BRA:
-		temp = addr + 2 + (signed char)p1;
-		log0("%04X    ", temp);
-		addr++;
-		break;
-	case IMM:
-		log0("#%02X     ", p1);
-		addr++;
-		break;
-	case ZP:
-		log0("%02X      ", p1);
-		addr++;
-		break;
-	case ZPX:
-		log0("%02X,X    ", p1);
-		addr++;
-		break;
-	case ZPY:
-		log0("%02X,Y    ", p1);
-		addr++;
-		break;
-	case IND:
-		log0("(%02X)    ", p1);
-		addr++;
-		break;
-	case INDX:
-		log0("(%02X,X)  ", p1);
-		addr++;
-		break;
-	case INDY:
-		log0("(%02X),Y  ", p1);
-		addr++;
-		break;
-	case ABS:
-		log0("%02X%02X    ", p2, p1);
-		addr += 2;
-		break;
-	case ABSX:
-		log0("%02X%02X,X  ", p2, p1);
-		addr += 2;
-		break;
-	case ABSY:
-		log0("%02X%02X,Y  ", p2, p1);
-		addr += 2;
-		break;
-	case IND16:
-		log0("(%02X%02X)  ", p2, p1);
-		addr += 2;
-		break;
-	case IND1X:
-		log0("(%02X%02X,X)", p2, p1);
-		addr += 2;
-		break;
-	}
-	log0("\n");
-	addr++;
-	return addr;
+  // 012345678901234567890123456789
+  // AAAA : 11 22 33 : III MMMMMMMM
+
+  // Template
+  strfill(buffer, ' ', sizeof(buffer));
+  buffer[5] = ':';
+  buffer[16] = ':';
+
+  // Address
+  strhex4(buffer, addr++);
+
+  // Hex
+  strhex2(buffer + 7, op);
+
+  if (mode > MARK2) {
+    p1 = readMemByteInc();
+    strhex2(buffer + 10, p1);
+    addr++;
+  }
+
+  if (mode > MARK3) {
+    p2 = readMemByteInc();
+    strhex2(buffer + 13, p2);
+    addr++;
+  }
+
+  uint16_t opIndex = pgm_read_byte(dopname + op) * 3;
+
+  ptr = buffer + 18;
+  for (temp = 0; temp < 3; temp++) {
+    *ptr++ = pgm_read_byte(opString + opIndex + temp);
+  }
+  ptr++;
+
+  switch (mode)
+    {
+    case IMP:
+      break;
+    case IMPA:
+      *ptr++ = 'A';
+      break;
+    case BRA:
+      *ptr++ = '$';
+      ptr = strhex4(ptr, addr + (int8_t)p1);
+      break;
+    case IMM:
+      *ptr++ = '#';
+      // Fall through to
+    case ZP:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      break;
+    case ZPX:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'X';
+      break;
+    case ZPY:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'Y';
+      break;
+    case INDX:
+      *ptr++ = '(';
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'X';
+      *ptr++ = ')';
+      break;
+    case INDY:
+      *ptr++ = '(';
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ')';
+      *ptr++ = ',';
+      *ptr++ = 'Y';
+      break;
+    case ABS:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p2);
+      ptr = strhex2(ptr, p1);
+      break;
+    case ABSX:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p2);
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'X';
+      break;
+    case ABSY:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p2);
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'Y';
+      break;
+    case IND16:
+      *ptr++ = '(';
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p2);
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ')';
+      break;
+    }
+  *ptr++ = '\n';
+  *ptr++ = '\0';
+  logs(buffer);
+  return addr;
 }

firmware/dis65c02.c

@@ -0,0 +1,327 @@
+#include <avr/pgmspace.h>
+#include "AtomBusMon.h"
+
+enum
+  {
+    IMP, IMPA, MARK2, BRA, IMM, ZP, ZPX, ZPY, INDX, INDY, IND, MARK3, ABS, ABSX, ABSY, IND16, IND1X
+  };
+
+enum
+  {
+    I_ADC,
+    I_AND,
+    I_ASL,
+    I_BCC,
+    I_BCS,
+    I_BEQ,
+    I_BIT,
+    I_BMI,
+    I_BNE,
+    I_BPL,
+    I_BRA,
+    I_BRK,
+    I_BVC,
+    I_BVS,
+    I_CLC,
+    I_CLD,
+    I_CLI,
+    I_CLV,
+    I_CMP,
+    I_CPX,
+    I_CPY,
+    I_DEC,
+    I_DEX,
+    I_DEY,
+    I_EOR,
+    I_INC,
+    I_INX,
+    I_INY,
+    I_JMP,
+    I_JSR,
+    I_LDA,
+    I_LDX,
+    I_LDY,
+    I_LSR,
+    I_NOP,
+    I_ORA,
+    I_PHA,
+    I_PHP,
+    I_PHX,
+    I_PHY,
+    I_PLA,
+    I_PLP,
+    I_PLX,
+    I_PLY,
+    I_ROL,
+    I_ROR,
+    I_RTI,
+    I_RTS,
+    I_SBC,
+    I_SEC,
+    I_SED,
+    I_SEI,
+    I_STA,
+    I_STP,
+    I_STX,
+    I_STY,
+    I_STZ,
+    I_TAX,
+    I_TAY,
+    I_TRB,
+    I_TSB,
+    I_TSX,
+    I_TXA,
+    I_TXS,
+    I_TYA,
+    I_WAI,
+    I_XXX
+  };
+
+static const char opString[] PROGMEM = "\
+ADC\
+AND\
+ASL\
+BCC\
+BCS\
+BEQ\
+BIT\
+BMI\
+BNE\
+BPL\
+BRA\
+BRK\
+BVC\
+BVS\
+CLC\
+CLD\
+CLI\
+CLV\
+CMP\
+CPX\
+CPY\
+DEC\
+DEX\
+DEY\
+EOR\
+INC\
+INX\
+INY\
+JMP\
+JSR\
+LDA\
+LDX\
+LDY\
+LSR\
+NOP\
+ORA\
+PHA\
+PHP\
+PHX\
+PHY\
+PLA\
+PLP\
+PLX\
+PLY\
+ROL\
+ROR\
+RTI\
+RTS\
+SBC\
+SEC\
+SED\
+SEI\
+STA\
+STP\
+STX\
+STY\
+STZ\
+TAX\
+TAY\
+TRB\
+TSB\
+TSX\
+TXA\
+TXS\
+TYA\
+WAI\
+---\
+";
+
+static const unsigned char dopname[256] PROGMEM =
+{
+/*00*/ I_BRK, I_ORA, I_XXX, I_XXX, I_TSB, I_ORA, I_ASL, I_XXX, I_PHP, I_ORA, I_ASL, I_XXX, I_TSB, I_ORA, I_ASL, I_XXX,
+/*10*/ I_BPL, I_ORA, I_ORA, I_XXX, I_TRB, I_ORA, I_ASL, I_XXX, I_CLC, I_ORA, I_INC, I_XXX, I_TRB, I_ORA, I_ASL, I_XXX,
+/*20*/ I_JSR, I_AND, I_XXX, I_XXX, I_BIT, I_AND, I_ROL, I_XXX, I_PLP, I_AND, I_ROL, I_XXX, I_BIT, I_AND, I_ROL, I_XXX,
+/*30*/ I_BMI, I_AND, I_AND, I_XXX, I_BIT, I_AND, I_ROL, I_XXX, I_SEC, I_AND, I_DEC, I_XXX, I_BIT, I_AND, I_ROL, I_XXX,
+/*40*/ I_RTI, I_EOR, I_XXX, I_XXX, I_XXX, I_EOR, I_LSR, I_XXX, I_PHA, I_EOR, I_LSR, I_XXX, I_JMP, I_EOR, I_LSR, I_XXX,
+/*50*/ I_BVC, I_EOR, I_EOR, I_XXX, I_XXX, I_EOR, I_LSR, I_XXX, I_CLI, I_EOR, I_PHY, I_XXX, I_XXX, I_EOR, I_LSR, I_XXX,
+/*60*/ I_RTS, I_ADC, I_XXX, I_XXX, I_STZ, I_ADC, I_ROR, I_XXX, I_PLA, I_ADC, I_ROR, I_XXX, I_JMP, I_ADC, I_ROR, I_XXX,
+/*70*/ I_BVS, I_ADC, I_ADC, I_XXX, I_STZ, I_ADC, I_ROR, I_XXX, I_SEI, I_ADC, I_PLY, I_XXX, I_JMP, I_ADC, I_ROR, I_XXX,
+/*80*/ I_BRA, I_STA, I_XXX, I_XXX, I_STY, I_STA, I_STX, I_XXX, I_DEY, I_BIT, I_TXA, I_XXX, I_STY, I_STA, I_STX, I_XXX,
+/*90*/ I_BCC, I_STA, I_STA, I_XXX, I_STY, I_STA, I_STX, I_XXX, I_TYA, I_STA, I_TXS, I_XXX, I_STZ, I_STA, I_STZ, I_XXX,
+/*A0*/ I_LDY, I_LDA, I_LDX, I_XXX, I_LDY, I_LDA, I_LDX, I_XXX, I_TAY, I_LDA, I_TAX, I_XXX, I_LDY, I_LDA, I_LDX, I_XXX,
+/*B0*/ I_BCS, I_LDA, I_LDA, I_XXX, I_LDY, I_LDA, I_LDX, I_XXX, I_CLV, I_LDA, I_TSX, I_XXX, I_LDY, I_LDA, I_LDX, I_XXX,
+/*C0*/ I_CPY, I_CMP, I_XXX, I_XXX, I_CPY, I_CMP, I_DEC, I_XXX, I_INY, I_CMP, I_DEX, I_WAI, I_CPY, I_CMP, I_DEC, I_XXX,
+/*D0*/ I_BNE, I_CMP, I_CMP, I_XXX, I_XXX, I_CMP, I_DEC, I_XXX, I_CLD, I_CMP, I_PHX, I_STP, I_XXX, I_CMP, I_DEC, I_XXX,
+/*E0*/ I_CPX, I_SBC, I_XXX, I_XXX, I_CPX, I_SBC, I_INC, I_XXX, I_INX, I_SBC, I_NOP, I_XXX, I_CPX, I_SBC, I_INC, I_XXX,
+/*F0*/ I_BEQ, I_SBC, I_SBC, I_XXX, I_XXX, I_SBC, I_INC, I_XXX, I_SED, I_SBC, I_PLX, I_XXX, I_XXX, I_SBC, I_INC, I_XXX
+};
+
+static const unsigned char dopaddr[256] PROGMEM =
+{
+/*00*/ IMM, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
+/*10*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMPA,  IMP,  ABS,    ABSX,  ABSX, IMP,
+/*20*/ ABS, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
+/*30*/ BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMPA,  IMP,  ABSX,   ABSX,  ABSX, IMP,
+/*40*/ IMP, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
+/*50*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP,
+/*60*/ IMP, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  IND16,  ABS,   ABS,  IMP,
+/*70*/ BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  IND1X,  ABSX,  ABSX, IMP,
+/*80*/ BRA, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+/*90*/ BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPY,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP,
+/*A0*/ IMM, INDX,  IMM, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+/*B0*/ BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPY,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABSX,   ABSX,  ABSY, IMP,
+/*C0*/ IMM, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+/*D0*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP,
+/*E0*/ IMM, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+/*F0*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP
+};
+
+addr_t disassemble(addr_t addr, uint8_t m)
+{
+
+  char buffer[40];
+  uint8_t temp;
+  data_t op = readMemByteInc();
+  data_t p1 = 0;
+  data_t p2 = 0;
+  uint8_t mode = pgm_read_byte(dopaddr + op);
+  char *ptr;
+
+  // 012345678901234567890123456789
+  // AAAA : 11 22 33 : III MMMMMMMM
+
+  // Template
+  strfill(buffer, ' ', sizeof(buffer));
+  buffer[5] = ':';
+  buffer[16] = ':';
+
+  // Address
+  strhex4(buffer, addr++);
+
+  // Hex
+  strhex2(buffer + 7, op);
+
+  if (mode > MARK2) {
+    p1 = readMemByteInc();
+    strhex2(buffer + 10, p1);
+    addr++;
+  }
+
+  if (mode > MARK3) {
+    p2 = readMemByteInc();
+    strhex2(buffer + 13, p2);
+    addr++;
+  }
+
+  uint16_t opIndex = pgm_read_byte(dopname + op) * 3;
+
+  ptr = buffer + 18;
+  for (temp = 0; temp < 3; temp++) {
+    *ptr++ = pgm_read_byte(opString + opIndex + temp);
+  }
+  ptr++;
+
+  switch (mode)
+    {
+    case IMP:
+      break;
+    case IMPA:
+      *ptr++ = 'A';
+      break;
+    case BRA:
+      *ptr++ = '$';
+      ptr = strhex4(ptr, addr + (int8_t)p1);
+      break;
+    case IMM:
+      *ptr++ = '#';
+      // Fall through to
+    case ZP:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      break;
+    case ZPX:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'X';
+      break;
+    case ZPY:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'Y';
+      break;
+    case IND:
+      *ptr++ = '(';
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ')';
+      break;
+    case INDX:
+      *ptr++ = '(';
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'X';
+      *ptr++ = ')';
+      break;
+    case INDY:
+      *ptr++ = '(';
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ')';
+      *ptr++ = ',';
+      *ptr++ = 'Y';
+      break;
+    case ABS:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p2);
+      ptr = strhex2(ptr, p1);
+      break;
+    case ABSX:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p2);
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'X';
+      break;
+    case ABSY:
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p2);
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'Y';
+      break;
+    case IND16:
+      *ptr++ = '(';
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p2);
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ')';
+      break;
+    case IND1X:
+      *ptr++ = '(';
+      *ptr++ = '$';
+      ptr = strhex2(ptr, p2);
+      ptr = strhex2(ptr, p1);
+      *ptr++ = ',';
+      *ptr++ = 'X';
+      *ptr++ = ')';
+      break;
+    }
+  *ptr++ = '\n';
+  *ptr++ = '\0';
+  logs(buffer);
+  return addr;
+}

firmware/dis6809.c

@@ -18,24 +18,6 @@
 #include <avr/pgmspace.h>
 #include "AtomBusMon.h"
 
-unsigned char get_memb(unsigned int addr) {
-  loadAddr(addr);
-  return readMemByteInc();
-}
-
-#include <stdio.h>
-
-typedef unsigned char tt_u8;
-typedef signed char tt_s8;
-typedef unsigned short tt_u16;
-typedef signed short tt_s16;
-
-
-unsigned int get_memw(unsigned int addr) {
-  loadAddr(addr);
-  return (readMemByteInc() << 8) + readMemByteInc();
-}
-
 enum opcodes {
   OP_UU  ,
   OP_XX  ,
@@ -312,15 +294,15 @@ TSTB";
 
 // The first byte is the opcode index
 // The second byte is <length><mode>
-//	modes:
-//	1 immediate
-//	2 direct    
-//	3 indexed   
-//	4 extended  
-//	5 inherent
-//	6 relative
+//      modes:
+//      1 immediate
+//      2 direct
+//      3 indexed
+//      4 extended
+//      5 inherent
+//      6 relative
 
-static const unsigned char map0[] PROGMEM = {
+static const uint8_t map0[] PROGMEM = {
    OP_NEG , 0x22,
    OP_XX  , 0x22,
    OP_XX  , 0x12,
@@ -579,142 +561,110 @@ static const unsigned char map0[] PROGMEM = {
    OP_STU , 0x34,
 };
 
-static const unsigned char map1[] PROGMEM = {
-    33,	OP_LBRN, 0x46,
-    34,	OP_LBHI, 0x46,
-    35,	OP_LBLS, 0x46,
-    36,	OP_LBCC, 0x46,
-    37,	OP_LBLO, 0x46,
-    38,	OP_LBNE, 0x46,
-    39,	OP_LBEQ, 0x46,
-    40,	OP_LBVC, 0x46,
-    41,	OP_LBVS, 0x46,
-    42,	OP_LBPL, 0x46,
-    43,	OP_LBMI, 0x46,
-    44,	OP_LBGE, 0x46,
-    45,	OP_LBLT, 0x46,
-    46,	OP_LBGT, 0x46,
-    47,	OP_LBLE, 0x46,
-    63,	OP_SWI2, 0x25,
-   131,	OP_CMPD, 0x41,
-   140,	OP_CMPY, 0x41,
-   142,	OP_LDY , 0x41,
-   147,	OP_CMPD, 0x32,
-   156,	OP_CMPY, 0x32,
-   158,	OP_LDY , 0x32,
-   159,	OP_STY , 0x32,
-   163,	OP_CMPD, 0x33,
-   172,	OP_CMPY, 0x33,
-   174,	OP_LDY , 0x33,
-   175,	OP_STY , 0x33,
-   179,	OP_CMPD, 0x44,
-   188,	OP_CMPY, 0x44,
-   190,	OP_LDY , 0x44,
-   191,	OP_STY , 0x44,
-   206,	OP_LDS , 0x41,
-   222,	OP_LDS , 0x32,
-   223,	OP_STS , 0x32,
-   238,	OP_LDS , 0x33,
-   239,	OP_STS , 0x33,
-   254,	OP_LDS , 0x44,
-   255,	OP_STS , 0x44,
+static const uint8_t map1[] PROGMEM = {
+    33, OP_LBRN, 0x46,
+    34, OP_LBHI, 0x46,
+    35, OP_LBLS, 0x46,
+    36, OP_LBCC, 0x46,
+    37, OP_LBLO, 0x46,
+    38, OP_LBNE, 0x46,
+    39, OP_LBEQ, 0x46,
+    40, OP_LBVC, 0x46,
+    41, OP_LBVS, 0x46,
+    42, OP_LBPL, 0x46,
+    43, OP_LBMI, 0x46,
+    44, OP_LBGE, 0x46,
+    45, OP_LBLT, 0x46,
+    46, OP_LBGT, 0x46,
+    47, OP_LBLE, 0x46,
+    63, OP_SWI2, 0x25,
+   131, OP_CMPD, 0x41,
+   140, OP_CMPY, 0x41,
+   142, OP_LDY , 0x41,
+   147, OP_CMPD, 0x32,
+   156, OP_CMPY, 0x32,
+   158, OP_LDY , 0x32,
+   159, OP_STY , 0x32,
+   163, OP_CMPD, 0x33,
+   172, OP_CMPY, 0x33,
+   174, OP_LDY , 0x33,
+   175, OP_STY , 0x33,
+   179, OP_CMPD, 0x44,
+   188, OP_CMPY, 0x44,
+   190, OP_LDY , 0x44,
+   191, OP_STY , 0x44,
+   206, OP_LDS , 0x41,
+   222, OP_LDS , 0x32,
+   223, OP_STS , 0x32,
+   238, OP_LDS , 0x33,
+   239, OP_STS , 0x33,
+   254, OP_LDS , 0x44,
+   255, OP_STS , 0x44,
 };
 
-static const unsigned char map2[] PROGMEM = {
-    63,	OP_SWI3, 0x25,
-   131,	OP_CMPU, 0x41,
-   140,	OP_CMPS, 0x41,
-   147,	OP_CMPU, 0x32,
-   156,	OP_CMPS, 0x32,
-   163,	OP_CMPU, 0x33,
-   172,	OP_CMPS, 0x33,
-   179,	OP_CMPU, 0x44,
-   188,	OP_CMPS, 0x44,
+static const uint8_t map2[] PROGMEM = {
+    63, OP_SWI3, 0x25,
+   131, OP_CMPU, 0x41,
+   140, OP_CMPS, 0x41,
+   147, OP_CMPU, 0x32,
+   156, OP_CMPS, 0x32,
+   163, OP_CMPU, 0x33,
+   172, OP_CMPS, 0x33,
+   179, OP_CMPU, 0x44,
+   188, OP_CMPS, 0x44,
    255, OP_XX  , 0x10
 };
 
 static const char regi[] = { 'X', 'Y', 'U', 'S' };
 
 static const char *exgi[] = { "D", "X", "Y", "U", "S", "PC", "??", "??", "A",
-			      "B", "CC", "DP", "??", "??", "??", "??" };
+                              "B", "CC", "DP", "??", "??", "??", "??" };
 
 static const char *pshsregi[] = { "PC", "U", "Y", "X", "DP", "B", "A", "CC" };
+
 static const char *pshuregi[] = { "PC", "S", "Y", "X", "DP", "B", "A", "CC" };
 
-/* disassemble one instruction at adress adr and return its size */
+extern const char statusString[];
 
-char hexdigit(tt_u16 v)
-{
-  v &= 0xf;
-  if (v <= 9)
-    return '0' + v;
-  else
-    return 'A' - 10 + v;
+static uint8_t get_memb(addr_t addr) {
+  loadAddr(addr);
+  return readMemByteInc();
 }
 
-char *hex8str(tt_u8 v)
-{
-  static char tmpbuf[3] = "  ";
-
-  tmpbuf[1] = hexdigit(v);
-  tmpbuf[0] = hexdigit(v >> 4);
-
-  return tmpbuf;
+static uint16_t get_memw(addr_t addr) {
+  loadAddr(addr);
+  return (readMemByteInc() << 8) + readMemByteInc();
 }
 
-char *hex16str(tt_u16 v)
-{
-  static char tmpbuf[5] = "    ";
-
-  tmpbuf[3] = hexdigit(v);
-  v >>= 4;
-  tmpbuf[2] = hexdigit(v);
-  v >>= 4;
-  tmpbuf[1] = hexdigit(v);
-  v >>= 4;
-  tmpbuf[0] = hexdigit(v);
-
-  return tmpbuf;
-}
-
-extern char *statusString;
-
-char *ccstr(tt_u8 val)
-{
-  static char tempbuf[9] = "        ";
-  int i;
-
+static char *strcc(char *ptr, uint8_t val) {
+  uint8_t i;
   for (i = 0; i < 8; i++) {
-    if (val & 0x80)
-      tempbuf[i] = statusString[i];
-    else
-      tempbuf[i] = '.';
+    *ptr++ = (val & 0x80) ? statusString[i] : '.';
     val <<= 1;
   }
-
-  return tempbuf;
+  return ptr;
 }
 
-unsigned int disassemble(unsigned int addr)
-{
-  int d = get_memb(addr);
-  int s, i;
-  tt_u8 pb;
+/* disassemble one instruction at address addr and return the address of the next instruction */
+
+addr_t disassemble(addr_t addr, uint8_t m) {
+  uint8_t d = get_memb(addr);
+  uint8_t s;
+  int8_t i;
+  uint8_t pb;
   char reg;
-  const unsigned char *map = NULL;
+  char *ptr;
+  static char buffer[64];
+  const uint8_t *map = NULL;
 
   // Default for most undefined opcodes
   unsigned char sm = 0x10; // size_mode byte
   unsigned char oi = OP_XX; // opcode index
 
-  FILE *stream = &ser0stream;
-
   if (d == 0x10) {
-    d = get_memb(addr + 1); 
+    d = get_memb(addr + 1);
     map = map1;
-  }
-
-  if (d == 0x11) {
+  } else if (d == 0x11) {
     d = get_memb(addr + 1);
     map = map2;
   }
@@ -724,12 +674,13 @@ unsigned int disassemble(unsigned int addr)
     map -= 3;
     do {
       map += 3;
-      if (pgm_read_byte(map) == d) {
-	oi = pgm_read_byte(++map);
-	sm = pgm_read_byte(++map);
-	break;
+      s = pgm_read_byte(map);
+      if (s == d) {
+        oi = pgm_read_byte(++map);
+        sm = pgm_read_byte(++map);
+        break;
       }
-    } while (*map < 255);
+    } while (s < 255);
   } else {
     // Lookup directly in map0
     map = map0 + 2 * d;
@@ -739,187 +690,258 @@ unsigned int disassemble(unsigned int addr)
 
   s = sm >> 4;
 
-  fprintf(stream, "%04X ", addr);
+  // 0123456789012345678901234567890123456789
+  // AAAA : HH HH HH HH : OOOO AAAAAAAAA
 
+  strfill(buffer, ' ', sizeof(buffer));
+  buffer[5] = ':';
+  buffer[19] = ':';
+
+  // Address
+  strhex4(buffer, addr);
+
+  // Hex
+  ptr = buffer + 7;
   for (i = 0; i < s; i++) {
-    fputs(hex8str(get_memb(addr + i)), stream);
-    fputc(' ', stream);
-  }
-  for (i = s; i < 4; i++) {
-    fputs("   ", stream);
+    strhex2(ptr, get_memb(addr + i));
+    ptr += 3;
   }
 
-  const char *ip = inst + oi * 4; 
-  for (i = 0; i < 4; i++)
-    fputc(pgm_read_byte(ip++), stream);
+  // Opcode
+  ptr = buffer + 21;
+  const char *ip = inst + oi * 4;
+  for (i = 0; i < 4; i++) {
+    *ptr++ = pgm_read_byte(ip++);
+  }
+  ptr++;
 
-  fputs("  ", stream);
-
-  
   switch(sm & 15) {
   case 1:             /* immediate */
-    fputs("#$", stream);
-    if (s == 2)
-      fputs(hex8str(get_memb(addr + 1)), stream);
-    else
-      fputs(hex16str(get_memw(addr + s - 2)), stream);
+    *ptr++ = '#';
+    *ptr++ = '$';
+    if (s == 2) {
+      ptr = strhex2(ptr, get_memb(addr + 1));
+    } else {
+      ptr = strhex4(ptr, get_memw(addr + s - 2));
+    }
     break;
   case 2:             /* direct */
-    fputs("$", stream);
-    fputs(hex8str(get_memb(addr + s - 1)), stream);
+    *ptr++ = '$';
+    ptr = strhex2(ptr, get_memb(addr + s - 1));
     break;
   case 3:             /* indexed */
     pb = get_memb(addr + s - 1);
     reg = regi[(pb >> 5) & 0x03];
-
     if (!(pb & 0x80)) {       /* n4,R */
-      if (pb & 0x10)
-	fprintf(stream, "-$%s,%c", hex8str(((pb & 0x0f) ^ 0x0f) + 1), reg);
-      else
-	fprintf(stream, "$%s,%c", hex8str(pb & 0x0f), reg);
-    }
-    else {
-      if (pb & 0x10)
-	fputc('[', stream);
+      if (pb & 0x10) {
+        *ptr++ = '-';
+        *ptr++ = '$';
+        ptr = strhex2(ptr, ((pb & 0x0f) ^ 0x0f) + 1);
+      } else {
+        *ptr++ = '$';
+        ptr = strhex2(ptr, pb & 0x0f);
+      }
+      *ptr++ = ',';
+      *ptr++ = reg;
+    } else {
+      if (pb & 0x10) {
+        *ptr++ = '[';
+      }
       switch (pb & 0x0f) {
       case 0:                 /* ,R+ */
-	fprintf(stream, ",%c+", reg);
-	break;
+        *ptr++ = ',';
+        *ptr++ = reg;
+        *ptr++ = '+';
+        break;
       case 1:                 /* ,R++ */
-	fprintf(stream, ",%c++", reg);
-	break;
+        *ptr++ = ',';
+        *ptr++ = reg;
+        *ptr++ = '+';
+        *ptr++ = '+';
+        break;
       case 2:                 /* ,-R */
-	fprintf(stream, ",-%c", reg);
-	break;
+        *ptr++ = ',';
+        *ptr++ = '-';
+        *ptr++ = reg;
+        break;
       case 3:                 /* ,--R */
-	fprintf(stream, ",--%c", reg);
-	break;
+        *ptr++ = ',';
+        *ptr++ = '-';
+        *ptr++ = '-';
+        *ptr++ = reg;
+        break;
       case 4:                 /* ,R */
-	fprintf(stream, ",%c", reg);
-	break;
+        *ptr++ = ',';
+        *ptr++ = reg;
+        break;
       case 5:                 /* B,R */
-	fprintf(stream, "B,%c", reg);
-	break;
+        *ptr++ = 'B';
+        *ptr++ = ',';
+        *ptr++ = reg;
+        break;
       case 6:                 /* A,R */
-	fprintf(stream, "A,%c", reg);
-	break;
+        *ptr++ = 'A';
+        *ptr++ = ',';
+        *ptr++ = reg;
+        break;
       case 8:                 /* n7,R */
-	s += 1;
-	fprintf(stream, "$%s,%c", hex8str(get_memb(addr + s - 1)), reg);
-	break;
+        s += 1;
+        *ptr++ = '$';
+        ptr = strhex2(ptr, get_memb(addr + s - 1));
+        *ptr++ = ',';
+        *ptr++ = reg;
+        break;
       case 9:                 /* n15,R */
-	s += 2;
-	fprintf(stream, "$%s,%c", hex16str(get_memw(addr + s - 2)), reg);
-	break;
+        s += 2;
+        *ptr++ = '$';
+        ptr = strhex4(ptr, get_memw(addr + s - 2));
+        *ptr++ = ',';
+        *ptr++ = reg;
+        break;
       case 11:                /* D,R */
-	fprintf(stream, "D,%c", reg);
-	break;
+        *ptr++ = 'D';
+        *ptr++ = ',';
+        *ptr++ = reg;
+        break;
       case 12:                /* n7,PCR */
-	s += 1;
-	fprintf(stream, "$%s,PCR", hex8str(get_memb(addr + s - 1)));
-	break;
+        s += 1;
+        *ptr++ = '$';
+        ptr = strhex2(ptr, get_memb(addr + s - 1));
+        *ptr++ = ',';
+        *ptr++ = 'P';
+        *ptr++ = 'C';
+        *ptr++ = 'R';
+        break;
       case 13:                /* n15,PCR */
-	s += 2;
-	fprintf(stream, "$%s,PCR", hex16str(get_memw(addr + s - 2)));
-	break;
+        s += 2;
+        *ptr++ = '$';
+        ptr = strhex4(ptr, get_memw(addr + s - 2));
+        *ptr++ = ',';
+        *ptr++ = 'P';
+        *ptr++ = 'C';
+        *ptr++ = 'R';
+        break;
       case 15:                /* [n] */
-	s += 2;
-	fprintf(stream, "$%s", hex16str(get_memw(addr + s - 2)));
-	break;
+        s += 2;
+        *ptr++ = '$';
+        ptr = strhex4(ptr, get_memw(addr + s - 2));
+        break;
       default:
-	fputs("??", stream);
-	break; }
-      if (pb & 0x10)
-	fputc(']', stream);
+        *ptr++ = '?';
+        *ptr++ = '?';
+        break;
+      }
+      if (pb & 0x10) {
+        *ptr++ = ']';
+      }
     }
     break;
   case 4:          /* extended */
-    fprintf(stream, "$%s", hex16str(get_memw(addr + s - 2)));
+    *ptr++ = '$';
+    ptr = strhex4(ptr, get_memw(addr + s - 2));
     break;
   case 5:          /* inherent */
     pb = get_memb(addr + 1);
     switch (d) {
     case 0x1e: case 0x1f:              /* exg tfr */
-      fprintf(stream, "%s,%s", exgi[(pb >> 4) & 0x0f], exgi[pb & 0x0f]);
-      break; 
+      ptr = strinsert(ptr, exgi[(pb >> 4) & 0x0f]);
+      *ptr++ = ',';
+      ptr = strinsert(ptr, exgi[pb & 0x0f]);
+      break;
     case 0x1a: case 0x1c: case 0x3c:   /* orcc andcc cwai */
-      fprintf(stream, "#$%s=%s", hex8str(pb), ccstr(pb));
+      *ptr++ = '#';
+      *ptr++ = '$';
+      ptr = strhex2(ptr, pb);
+      *ptr++ = '=';
+      ptr = strcc(ptr, pb);
       break;
     case 0x34:                         /* pshs */
       {
-	int p = 0;
-
-	for (i = 0; i < 8; i++) {
-	  if (pb & 0x80) {
-	    if (p)
-	      fputc(',', stream);
-	    fputs(pshsregi[i], stream);
-	    p = 1;
-	  }
-	  pb <<= 1;
-	}
+        int p = 0;
+        for (i = 0; i < 8; i++) {
+          if (pb & 0x80) {
+            if (p) {
+              *ptr++ = ',';
+            }
+            ptr = strinsert(ptr, pshsregi[i]);
+            p = 1;
+          }
+          pb <<= 1;
+        }
       }
       break;
     case 0x35:                         /* puls */
       {
-	int p = 0;
-
-	for (i = 7; i >= 0; i--) {
-	  if (pb & 0x01) {
-	    if (p)
-	      fputc(',', stream);
-	    fputs(pshsregi[i], stream);
-	    p = 1;
-	  }
-	  pb >>= 1;
-	}
+        int p = 0;
+        for (i = 7; i >= 0; i--) {
+          if (pb & 0x01) {
+            if (p) {
+              *ptr++ = ',';
+            }
+            ptr = strinsert(ptr, pshsregi[i]);
+            p = 1;
+          }
+          pb >>= 1;
+        }
       }
       break;
     case 0x36:                         /* pshu */
       {
-	int p = 0;
-
-	for (i = 0; i < 8; i++) {
-	  if (pb & 0x80) {
-	    if (p)
-	      fputc(',', stream);
-	    fputs(pshuregi[i], stream);
-	    p = 1;
-	  }
-	  pb <<= 1;
-	}
+        int p = 0;
+        for (i = 0; i < 8; i++) {
+          if (pb & 0x80) {
+            if (p) {
+              *ptr++ = ',';
+            }
+            ptr = strinsert(ptr, pshuregi[i]);
+            p = 1;
+          }
+          pb <<= 1;
+        }
       }
       break;
     case 0x37:                         /* pulu */
       {
-	int p = 0;
-
-	for (i = 7; i >= 0; i--) {
-	  if (pb & 0x01) {
-	    if (p)
-	      fputc(',', stream);
-	    fputs(pshuregi[i], stream);
-	    p = 1;
-	  }
-	  pb >>= 1;
-	}
+        int p = 0;
+        for (i = 7; i >= 0; i--) {
+          if (pb & 0x01) {
+            if (p) {
+              *ptr++ = ',';
+            }
+            ptr = strinsert(ptr, pshuregi[i]);
+            p = 1;
+          }
+          pb >>= 1;
+        }
       }
       break;
     }
-    break; 
+    break;
   case 6:             /* relative */
     {
-      tt_s16 v;
-
-      if (s == 2)
-	v = (tt_s16)(tt_s8)get_memb(addr + 1);
-      else
-	v = (tt_s16)get_memw(addr + s - 2);
-      fprintf(stream, "$%s", hex16str(addr + (tt_u16)s + v));
-      break;
-    }
+      int16_t v;
+      if (s == 2) {
+        v = (int16_t)(int8_t)get_memb(addr + 1);
+      } else {
+        v = (int16_t)get_memw(addr + s - 2);
+      }
+      *ptr++ = '$';
+      ptr = strhex4(ptr, addr + (uint16_t)s + v);
+     }
+    break;
   }
-  fputc('\n', stream);
 
+  // Get rid of trailing white space
+  while (*(--ptr) == ' ');
+  ptr++;
+
+  // Add a newline and terminate the string
+  *ptr++ = '\n';
+  *ptr++ = '\0';
+
+  // Log using the normal (data memory) string logger
+  logs(buffer);
+
+  // Return the address of the next instruction
   return addr + s;
 }

firmware/disz80.c

@@ -1,11 +1,11 @@
 /*  Z80 disassembler
-    
+
 *** Copyright:  1994-1996 Günter Woigk
 mailto:kio@little-bat.de
 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 
 Permission to use, copy, modify, distribute, and sell this software and
 its documentation for any purpose is hereby granted without fee, provided
@@ -59,16 +59,16 @@ PERFORMANCE OF THIS SOFTWARE.
 // ---- opcode definitions ------------------------------------------------------------------
 
 enum {
-  NIX,    NOP,    LD,     INC,    DEC,    RLCA,   EX,     ADD,    
+  NIX,    NOP,    LD,     INC,    DEC,    RLCA,   EX,     ADD,
   RRCA,   DJNZ,   RLA,    JR,     RRA,    DAA,    CPL,    HALT,
-  SCF,    CCF,    RLC,    RRC,    RL,     RR,     SLA,    SRA,    
+  SCF,    CCF,    RLC,    RRC,    RL,     RR,     SLA,    SRA,
   SLL,    SRL,    IN,     OUT,    SBC,    NEG,    RETN,   IM,
-  ADC,    RETI,   RRD,    RLD,    SUB,    AND,    XOR,    
-  OR,     CP,     BIT,    RES,    SET,    LDI,    CPI,    INI,    
-  OUTI,   LDD,    CPD,    IND,    OUTD,   LDIR,   CPIR,   INIR,   
-  OTIR,   LDDR,   CPDR,   INDR,   OTDR,   RET,    POP,    JP, 
-  CALL,   PUSH,   RST,    PFX,    EXX,    DI,     EI, 
-  BC,     DE,     HL,     IX,     IY,     SP,     AF,     AF2,    
+  ADC,    RETI,   RRD,    RLD,    SUB,    AND,    XOR,
+  OR,     CP,     BIT,    RES,    SET,    LDI,    CPI,    INI,
+  OUTI,   LDD,    CPD,    IND,    OUTD,   LDIR,   CPIR,   INIR,
+  OTIR,   LDDR,   CPDR,   INDR,   OTDR,   RET,    POP,    JP,
+  CALL,   PUSH,   RST,    PFX,    EXX,    DI,     EI,
+  BC,     DE,     HL,     IX,     IY,     SP,     AF,     AF2,
   B,      C,      D,      E,      H,      L,      XHL,    A,      // <- KEEP THIS ORDER!
   XBC,    XDE,    R,      I,      XC,     XSP,    PC,     F,
   N0,     N1,     N2,     N3,     N4,     N5,     N6,     N7,
@@ -77,7 +77,7 @@ enum {
   XH,     XL,     YH,     YL,     XIX,    XIY
 };
 
-static const char word_NIX[] PROGMEM = "";    
+static const char word_NIX[] PROGMEM = "";
 static const char word_NOP[] PROGMEM = "NOP";
 static const char word_LD[] PROGMEM = "LD";
 static const char word_INC[] PROGMEM = "INC";
@@ -200,7 +200,7 @@ static const char word_YL[] PROGMEM = "YL";
 static const char word_XIX[] PROGMEM = "DIS(IX)";
 static const char word_XIY[] PROGMEM = "DIS(IY)";
 
-static const char * const word[] PROGMEM = 
+static const char * const word[] PROGMEM =
   {
     word_NIX,
     word_NOP,
@@ -325,224 +325,225 @@ static const char * const word[] PROGMEM =
     word_XIX,
     word_XIY
   };
-    
-static const unsigned char cmd_00[192] PROGMEM = 
+
+static const unsigned char cmd_00[192] PROGMEM =
   {
-    NOP,0,0,    
-    LD,BC,NN,   
-    LD,XBC,A,   
-    INC,BC,0,   
-    INC,B,0,    
-    DEC,B,0,    
-    LD,B,N,     
+    NOP,0,0,
+    LD,BC,NN,
+    LD,XBC,A,
+    INC,BC,0,
+    INC,B,0,
+    DEC,B,0,
+    LD,B,N,
     RLCA,0,0,
-    EX,AF,AF2,  
-    ADD,HL,BC,  
-    LD,A,XBC,   
-    DEC,BC,0,   
-    INC,C,0,    
-    DEC,C,0,    
-    LD,C,N,     
+    EX,AF,AF2,
+    ADD,HL,BC,
+    LD,A,XBC,
+    DEC,BC,0,
+    INC,C,0,
+    DEC,C,0,
+    LD,C,N,
     RRCA,0,0,
-    DJNZ,DIS,0, 
-    LD,DE,NN,   
-    LD,XDE,A,   
-    INC,DE,0,   
-    INC,D,0,    
-    DEC,D,0,    
-    LD,D,N,     
+    DJNZ,DIS,0,
+    LD,DE,NN,
+    LD,XDE,A,
+    INC,DE,0,
+    INC,D,0,
+    DEC,D,0,
+    LD,D,N,
     RLA,0,0,
-    JR,DIS,0,   
-    ADD,HL,DE,  
-    LD,A,XDE,   
-    DEC,DE,0,   
-    INC,E,0,    
-    DEC,E,0,    
-    LD,E,N,     
+    JR,DIS,0,
+    ADD,HL,DE,
+    LD,A,XDE,
+    DEC,DE,0,
+    INC,E,0,
+    DEC,E,0,
+    LD,E,N,
     RRA,0,0,
-    JR,NZ,DIS,  
-    LD,HL,NN,   
-    LD,XNN,HL,  
-    INC,HL,0,   
-    INC,H,0,    
-    DEC,H,0,    
-    LD,H,N,     
+    JR,NZ,DIS,
+    LD,HL,NN,
+    LD,XNN,HL,
+    INC,HL,0,
+    INC,H,0,
+    DEC,H,0,
+    LD,H,N,
     DAA,0,0,
-    JR,Z,DIS,   
-    ADD,HL,HL,  
-    LD,HL,XNN,  
-    DEC,HL,0,   
-    INC,L,0,    
-    DEC,L,0,    
-    LD,L,N,     
+    JR,Z,DIS,
+    ADD,HL,HL,
+    LD,HL,XNN,
+    DEC,HL,0,
+    INC,L,0,
+    DEC,L,0,
+    LD,L,N,
     CPL,0,0,
-    JR,NC,DIS,  
-    LD,SP,NN,   
-    LD,XNN,A,   
-    INC,SP,0,   
-    INC,XHL,0,  
-    DEC,XHL,0,  
-    LD,XHL,N,   
+    JR,NC,DIS,
+    LD,SP,NN,
+    LD,XNN,A,
+    INC,SP,0,
+    INC,XHL,0,
+    DEC,XHL,0,
+    LD,XHL,N,
     SCF,0,0,
-    JR,C,N,     
-    ADD,HL,SP,  
-    LD,A,XNN,   
-    DEC,SP,0,   
-    INC,A,0,    
-    DEC,A,0,    
-    LD,A,N,     
+    JR,C,N,
+    ADD,HL,SP,
+    LD,A,XNN,
+    DEC,SP,0,
+    INC,A,0,
+    DEC,A,0,
+    LD,A,N,
     CCF,0,0
   };
 
-static const unsigned char cmd_C0[192] PROGMEM = { 
-  
-    RET,NZ,0,   
-    POP,BC,0,   
-    JP,NZ,NN,   
-    JP,NN,0,    
-    CALL,NZ,NN, 
-    PUSH,BC,0,  
-    ADD,A,N,    
+static const unsigned char cmd_C0[192] PROGMEM = {
+
+    RET,NZ,0,
+    POP,BC,0,
+    JP,NZ,NN,
+    JP,NN,0,
+    CALL,NZ,NN,
+    PUSH,BC,0,
+    ADD,A,N,
     RST,N0,0,
-    RET,Z,0,    
-    RET,0,0,    
-    JP,Z,NN,    
-    PFX,CB,0,   
-    CALL,Z,NN,  
-    CALL,NN,0,  
-    ADC,A,N,    
+    RET,Z,0,
+    RET,0,0,
+    JP,Z,NN,
+    PFX,CB,0,
+    CALL,Z,NN,
+    CALL,NN,0,
+    ADC,A,N,
     RST,N1,0,
-    RET,NC,0,   
-    POP,DE,0,   
-    JP,NC,NN,   
-    OUT,XN,A,   
-    CALL,NC,NN, 
-    PUSH,DE,0,  
-    SUB,A,N,    
+    RET,NC,0,
+    POP,DE,0,
+    JP,NC,NN,
+    OUT,XN,A,
+    CALL,NC,NN,
+    PUSH,DE,0,
+    SUB,A,N,
     RST,N2,0,
-    RET,C,0,    
-    EXX,0,0,    
-    JP,C,NN,    
-    IN,A,XN,    
-    CALL,C,NN,  
-    PFX,IX,0,   
-    SBC,A,N,    
+    RET,C,0,
+    EXX,0,0,
+    JP,C,NN,
+    IN,A,XN,
+    CALL,C,NN,
+    PFX,IX,0,
+    SBC,A,N,
     RST,N3,0,
-    RET,PO,0,   
-    POP,HL,0,   
-    JP,PO,NN,   
-    EX,HL,XSP,  
-    CALL,PO,NN, 
-    PUSH,HL,0,  
-    AND,A,N,    
+    RET,PO,0,
+    POP,HL,0,
+    JP,PO,NN,
+    EX,HL,XSP,
+    CALL,PO,NN,
+    PUSH,HL,0,
+    AND,A,N,
     RST,N4,0,
-    RET,PE,0,   
-    LD,PC,HL,   
-    JP,PE,NN,   
-    EX,DE,HL,   
-    CALL,PE,NN, 
-    PFX,ED,0,   
-    XOR,A,N,    
+    RET,PE,0,
+    LD,PC,HL,
+    JP,PE,NN,
+    EX,DE,HL,
+    CALL,PE,NN,
+    PFX,ED,0,
+    XOR,A,N,
     RST,N5,0,
-    RET,P,0,    
-    POP,AF,0,   
-    JP,P,NN,    
-    DI,0,0,     
-    CALL,P,NN,  
-    PUSH,AF,0,  
-    OR,A,N,     
+    RET,P,0,
+    POP,AF,0,
+    JP,P,NN,
+    DI,0,0,
+    CALL,P,NN,
+    PUSH,AF,0,
+    OR,A,N,
     RST,N6,0,
-    RET,M,0,    
-    LD,SP,HL,   
-    JP,M,NN,    
-    EI,0,0,     
-    CALL,M,NN,  
-    PFX,IY,0,   
-    CP,A,N,     
+    RET,M,0,
+    LD,SP,HL,
+    JP,M,NN,
+    EI,0,0,
+    CALL,M,NN,
+    PFX,IY,0,
+    CP,A,N,
     RST,N7,0
 };
 
 static const unsigned char cmd_ED40[192] PROGMEM = {
-  
-    IN,B,XC,    
-    OUT,XC,B,   
-    SBC,HL,BC,  
-    LD,XNN,BC,  
-    NEG,0,0,    
-    RETN,0,0,   
-    IM,N0,0,    
+
+    IN,B,XC,
+    OUT,XC,B,
+    SBC,HL,BC,
+    LD,XNN,BC,
+    NEG,0,0,
+    RETN,0,0,
+    IM,N0,0,
     LD,I,A,
-    IN,C,XC,    
-    OUT,XC,C,   
-    ADC,HL,BC,  
-    LD,BC,XNN,  
-    NEG,0,0,    
-    RETI,0,0,   
-    IM,N0,0,    
+    IN,C,XC,
+    OUT,XC,C,
+    ADC,HL,BC,
+    LD,BC,XNN,
+    NEG,0,0,
+    RETI,0,0,
+    IM,N0,0,
     LD,R,A,
-    IN,D,XC,    
-    OUT,XC,D,   
-    SBC,HL,DE,  
-    LD,XNN,DE,  
-    NEG,0,0,    
-    RETN,0,0,   
-    IM,N1,0,    
+    IN,D,XC,
+    OUT,XC,D,
+    SBC,HL,DE,
+    LD,XNN,DE,
+    NEG,0,0,
+    RETN,0,0,
+    IM,N1,0,
     LD,A,I,
-    IN,E,XC,    
-    OUT,XC,E,   
-    ADC,HL,DE,  
-    LD,DE,XNN,  
-    NEG,0,0,    
-    RETI,0,0,   
-    IM,N2,0,    
+    IN,E,XC,
+    OUT,XC,E,
+    ADC,HL,DE,
+    LD,DE,XNN,
+    NEG,0,0,
+    RETI,0,0,
+    IM,N2,0,
     LD,A,R,
-    IN,H,XC,    
-    OUT,XC,H,   
-    SBC,HL,HL,  
-    LD,XNN,HL,  
-    NEG,0,0,    
-    RETN,0,0,   
-    IM,N0,0,    
+    IN,H,XC,
+    OUT,XC,H,
+    SBC,HL,HL,
+    LD,XNN,HL,
+    NEG,0,0,
+    RETN,0,0,
+    IM,N0,0,
     RRD,0,0,
-    IN,L,XC,    
-    OUT,XC,L,   
-    ADC,HL,HL,  
-    LD,HL,XNN,  
-    NEG,0,0,    
-    RETI,0,0,   
-    IM,N0,0,    
+    IN,L,XC,
+    OUT,XC,L,
+    ADC,HL,HL,
+    LD,HL,XNN,
+    NEG,0,0,
+    RETI,0,0,
+    IM,N0,0,
     RLD,0,0,
-    IN,F,XC,    
-    OUT,XC,N0,  
-    SBC,HL,SP,  
-    LD,XNN,SP,  
-    NEG,0,0,    
-    RETN,0,0,   
-    IM,N1,0,    
+    IN,F,XC,
+    OUT,XC,N0,
+    SBC,HL,SP,
+    LD,XNN,SP,
+    NEG,0,0,
+    RETN,0,0,
+    IM,N1,0,
     NOP,0,0,
-    IN,A,XC,    
-    OUT,XC,A,   
-    ADC,HL,SP,  
-    LD,SP,XNN,  
-    NEG,0,0,    
-    RETI,0,0,   
-    IM,N2,0,    
-    NOP,0,0 
+    IN,A,XC,
+    OUT,XC,A,
+    ADC,HL,SP,
+    LD,SP,XNN,
+    NEG,0,0,
+    RETI,0,0,
+    IM,N2,0,
+    NOP,0,0
   };
 
+static const char msg_HALT[] PROGMEM = "**HALT**\n";
+static const char msg_INT[] PROGMEM = "**INT**\n";
+static const char msg_NMI[] PROGMEM = "**NMI**\n";
+
 unsigned char cmd_halt[] = { HALT,0,0 };
 unsigned char cmd_nop[]  = { NOP,0,0 };
 
 unsigned char c_ari[]    = { ADD,ADC,SUB,SBC,AND,XOR,OR,CP };
 
 unsigned char c_blk[]    = { LDI,CPI,INI,OUTI,0,0,0,0,LDD,CPD,IND,OUTD,0,0,0,0,
-			     LDIR,CPIR,INIR,OTIR,0,0,0,0,LDDR,CPDR,INDR,OTDR };
+                             LDIR,CPIR,INIR,OTIR,0,0,0,0,LDDR,CPDR,INDR,OTDR };
 
 unsigned char c_sh[]     = { RLC,RRC,RL,RR,SLA,SRA,SLL,SRL };
 
-
-char buffer[10];
-
 // ============================================================================================
 
 
@@ -570,11 +571,11 @@ const unsigned char* mnemo(unsigned char op) {
     {
     case 0: return copyFromPgmMem(cmd_00 + op * 3);
     case 1: if (op==0x76) return cmd_halt;
-      cl[1] = B + ((op>>3)&0x07); 
-      cl[2] = B + (op&0x07); 
+      cl[1] = B + ((op>>3)&0x07);
+      cl[2] = B + (op&0x07);
       return cl;
     case 2: ca[0] = c_ari[(op>>3)&0x07];
-      ca[2] = B + (op&0x07); 
+      ca[2] = B + (op&0x07);
       return ca;
     case 3: return copyFromPgmMem(cmd_C0 + (op&0x3f) * 3);
     }
@@ -598,7 +599,7 @@ unsigned char* mnemoCB(unsigned char op) {
     case 3: cmd[0] = SET; break;
     }
   cmd[1] = N0 + ((op>>3)&0x07);
-  cmd[2] = B + (op&0x07); 
+  cmd[2] = B + (op&0x07);
   return cmd;
 }
 
@@ -633,14 +634,14 @@ const unsigned char* mnemoED(unsigned char op) {
   static unsigned char cmd[3]={0,0,0};
 
   if (op<0x40) return cmd_nop;
-    
-  if (op>=0x080) 
+
+  if (op>=0x080)
     {   if ((op&0xE4)!=0xA0) return cmd_nop;
       cmd[0] = c_blk[op&0x1B];
       return cmd;
     };
-    
-  return copyFromPgmMem(cmd_ED40 + (op-0x40) * 3);   
+
+  return copyFromPgmMem(cmd_ED40 + (op-0x40) * 3);
 }
 
 
@@ -648,7 +649,7 @@ const unsigned char* mnemoED(unsigned char op) {
 //      note: for immediate use only!
 unsigned char*   mnemoIX (unsigned char op) {
   static unsigned char cmd[3];
-    
+
   memcpy (cmd, mnemo(op), 3);
 
   if (cmd[1]==XHL) { cmd[1]=XIX; return cmd; }
@@ -667,7 +668,7 @@ unsigned char*   mnemoIX (unsigned char op) {
 //      note: for immediate use only!
 unsigned char*   mnemoIY (unsigned char op) {
   static unsigned char cmd[3];
-    
+
   memcpy (cmd, mnemo(op), 3);
 
   if (cmd[1]==XHL) { cmd[1]=XIY; return cmd; }
@@ -693,13 +694,13 @@ int IllegalCB (unsigned char op) {
 //      instructions using IX are legal except: sll is illegal
 int IllegalXXCB (unsigned char op) {
   if ((op&0x07)!=6) return weird;
-  return op>=0x30 && op<0x38 ? illegal : legal;   
+  return op>=0x30 && op<0x38 ? illegal : legal;
 }
 
 
 // ---- get legal state of ED instruction --------------------------------------
 //      0x00-0x3F and 0x80-0xFF weird except block instructions
-//      0x40-0x7F legal or weird 
+//      0x40-0x7F legal or weird
 //      in f,(c) is legal; out (c),0 is weird
 int IllegalED (unsigned char op) {
   char *il = "1111111111110101111100111111001111110001111100011011000011110000";
@@ -715,7 +716,7 @@ int IllegalED (unsigned char op) {
 //      prefixes are legal
 int IllegalXX (unsigned char op) {
   const unsigned char *c;
-    
+
   c = mnemo(op);
 
   if (*c==PFX || c[1]==XHL || c[2]==XHL) return legal;
@@ -742,127 +743,192 @@ int OpcodeLength (unsigned char op1, unsigned char op2) {
     {
     case 0xcb:  return 2;
     case 0xed:  if (/* op2<0x40 || op2>=0x80 || ((op2&7)!=3) */ (op2&0xc7)!=0x43) return 2; else return 4;
-    case 0xdd:  
+    case 0xdd:
     case 0xfd:
-      switch (op2>>6)         
+      switch (op2>>6)
         {
         case 0: return len0[op2]-'0'+1 + (op2>=0x34&&op2<=0x36);    // inc(hl); dec(hl); ld(hl),N: add displacement
-        case 1: 
+        case 1:
         case 2: if (((op2&0x07)==6) == ((op2&0x0F8)==0x70)) return 2; else return 3;
         }
       if (op2==0xcb) return 4;
       return len3[op2&0x3F]-'0'+1;    // note: entries for prefixes are 0 giving a total of 1, just to skip the useless prefix
     }
-    
+
   return len3[op1&0x3F]-'0';          // 0xC0 - 0xFF: no prefix:  various length
 }
 
 
 // ===================================================================================
 
-void xword (unsigned char n, unsigned int *ip) {
+char * xword (char *ptr, unsigned char n, unsigned int *ip) {
   unsigned int nn;
 
+  // TODO: Replace switch with a more intelligent case
   switch (n)
     {
     case DIS:
       n = Peek((*ip)++);
-      log0("$%04X", *ip+(char)n,4);      // branch destination
+      *ptr++ = '$';
+      ptr = strhex4(ptr, *ip+(char)n);      // branch destination
       break;
-    case N: 
+    case N:
       n = Peek((*ip)++);
-      log0("$%02X", n);
+      *ptr++ = '$';
+      ptr = strhex2(ptr, n);
       break;
     case NN:
       n = Peek((*ip)++);
       nn = n+256*Peek((*ip)++);
-      log0("$%04X", nn);
+      *ptr++ = '$';
+      ptr = strhex4(ptr, nn);
       break;
     case XNN:
       n = Peek((*ip)++);
       nn = n+256*Peek((*ip)++);
-      log0("($%04X)", nn);
+      *ptr++ = '(';
+      *ptr++ = '$';
+      ptr = strhex4(ptr, nn);
+      *ptr++ = ')';
       break;
     case XN:
       n = Peek((*ip)++);
-      log0("($%02X)", n);
+      *ptr++ = '(';
+      *ptr++ = '$';
+      ptr = strhex2(ptr, n);
+      *ptr++ = ')';
       break;
     case XIX:
       n = Peek((*ip)++);
+      *ptr++ = '(';
+      *ptr++ = 'I';
+      *ptr++ = 'X';
       if (n&0x80) {
-	log0("(IX-$%02X)", 256-n);
+        *ptr++ = '-';
+        ptr = strhex2(ptr, 256 - n);
       } else {
-	log0("(IX+$%02X)", n);
+        *ptr++ = '+';
+        ptr = strhex2(ptr, n);
       }
+      *ptr++ = ')';
       break;
     case XIY:
       n = Peek((*ip)++);
+      *ptr++ = '(';
+      *ptr++ = 'I';
+      *ptr++ = 'Y';
       if (n&0x80) {
-	log0("(IY-$%02X)", 256-n);
+        *ptr++ = '-';
+        ptr = strhex2(ptr, 256 - n);
       } else {
-	log0("(IY+$%02X)", n);
+        *ptr++ = '+';
+        ptr = strhex2(ptr, n);
       }
+      *ptr++ = ')';
       break;
     default:
-      strcpy_P(buffer, (PGM_P)pgm_read_word(&(word[n])));
-      log0("%s", buffer);
+      strcpy_P(ptr, (PGM_P)pgm_read_word(&(word[n])));
+      ptr += strlen(ptr);
       break;
     }
+  return ptr;
 }
 
 
 // ---- expand 3-char descriptor m[3] to mnemonic with arguments via pc
-void disass (const unsigned char *m, unsigned int *ip) {
-  strcpy_P(buffer, (PGM_P)pgm_read_word(&(word[*m++])));
-  log0("%-5s", buffer);
+char *disass (char *ptr, const unsigned char *m, unsigned int *ip) {
+  strcpy_P(ptr, (PGM_P)pgm_read_word(&(word[*m++])));
+  *(ptr + strlen(ptr)) = ' ';
+  ptr += 5;
   if (*m) {
-    xword(*m++,ip);
+    ptr = xword(ptr, *m++,ip);
   }
   if (*m) {
-    log0(",");
-    xword(*m,ip);
+    *ptr++ = ',';
+    ptr = xword(ptr, *m,ip);
   }
+  return ptr;
 }
 
-void disassem (unsigned int *ip) {
+char * disassem (char *ptr, unsigned int *ip) {
   unsigned char op;
-    
+
   op = Peek((*ip)++);
   switch (op)
     {
     case 0xcb:
-      disass (mnemoCB(Peek((*ip)++)), ip);
+      ptr = disass(ptr, mnemoCB(Peek((*ip)++)), ip);
       break;
     case 0xed:
-      disass (mnemoED(Peek((*ip)++)), ip);
+      ptr = disass(ptr, mnemoED(Peek((*ip)++)), ip);
       break;
     case 0xdd:
       op = Peek((*ip)++);
       if (op!=0xCB) {
-	disass (mnemoIX(op), ip);
+        ptr = disass(ptr, mnemoIX(op), ip);
       } else {
-	disass (mnemoIXCB(Peek((*ip)+1)), ip);
-	(*ip)++;
+        ptr = disass(ptr, mnemoIXCB(Peek((*ip)+1)), ip);
+        (*ip)++;
       }
       break;
     case 0xfd:
       op = Peek((*ip)++);
       if (op!=0xCB) {
-	disass (mnemoIY(op), ip);
+        ptr = disass(ptr, mnemoIY(op), ip);
       } else {
-        disass (mnemoIYCB(Peek((*ip)+1)), ip);
-	(*ip)++;
+        ptr = disass(ptr, mnemoIYCB(Peek((*ip)+1)), ip);
+        (*ip)++;
       }
       break;
     default:
-      disass (mnemo(op),ip);
+      ptr = disass(ptr, mnemo(op),ip);
       break;
     }
+  return ptr;
 }
 
-unsigned int disassemble(unsigned int addr) {
-  log0("%04X : ", addr);
-  disassem(&addr);
-  log0("\n");
+addr_t disassemble(addr_t addr, uint8_t m) {
+  static char buffer[64];
+
+  char *ptr;
+  addr_t addr2 = addr;
+
+  // Ignore the current CPU state in the disassemble connamd
+  uint8_t pdc = (m == MODE_DIS_CMD) ? 0 : PDC_DIN;
+
+  // 0123456789012345678901234567890123456789
+  // AAAA : HH HH HH HH : LD   RR,($XXXX)
+
+  strfill(buffer, ' ', sizeof(buffer));
+  buffer[5] = ':';
+  buffer[19] = ':';
+
+  // Address
+  strhex4(buffer, addr);
+
+  // Opcode
+  ptr = buffer + 21;
+
+  if (pdc & 0x80) {
+    strcpy_P(ptr, msg_HALT);
+  } else if (pdc & 0x40) {
+    strcpy(ptr, msg_NMI);
+  } else if (pdc & 0x20) {
+    strcpy(ptr, msg_INT);
+  } else {
+    ptr = disassem(ptr, &addr2);
+    *ptr++ = '\n';
+    *ptr++ = '\0';
+  }
+
+  // Hex
+  loadAddr(addr);
+  ptr = buffer + 7;
+  while (addr < addr2) {
+    strhex2(ptr, readMemByteInc());
+    ptr += 3;
+    addr++;
+  }
+  logs(buffer);
   return addr;
 }

firmware/hd44780.c

@@ -1,716 +0,0 @@
-/*****************************************************************************
-Title  :   HD44780 Library
-Author :   SA Development
-Version:   1.11
-*****************************************************************************/
-
-#include "avr/pgmspace.h"
-#include "hd44780.h"
-#include "avr/sfr_defs.h"
-#if (USE_ADELAY_LIBRARY==1)
-  #include "adelay.h"
-#else
-  #define Delay_ns(__ns) \
-    if((unsigned long) (F_CPU/1000000000.0 * __ns) != F_CPU/1000000000.0 * __ns)\
-          __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000000000.0 * __ns)+1);\
-    else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000000000.0 * __ns))
-  #define Delay_us(__us) \
-    if((unsigned long) (F_CPU/1000000.0 * __us) != F_CPU/1000000.0 * __us)\
-          __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000000.0 * __us)+1);\
-    else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000000.0 * __us))
-  #define Delay_ms(__ms) \
-    if((unsigned long) (F_CPU/1000.0 * __ms) != F_CPU/1000.0 * __ms)\
-          __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000.0 * __ms)+1);\
-    else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1000.0 * __ms))
-  #define Delay_s(__s) \
-    if((unsigned long) (F_CPU/1.0 * __s) != F_CPU/1.0 * __s)\
-          __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1.0 * __s)+1);\
-    else __builtin_avr_delay_cycles((unsigned long) ( F_CPU/1.0 * __s))
-#endif
-
-#if !defined(LCD_BITS) || (LCD_BITS!=4 && LCD_BITS!=8)
-  #error LCD_BITS is not defined or not valid.
-#endif
-
-#if !defined(WAIT_MODE) || (WAIT_MODE!=0 && WAIT_MODE!=1)
-  #error WAIT_MODE is not defined or not valid.
-#endif
-
-#if !defined(RW_LINE_IMPLEMENTED) || (RW_LINE_IMPLEMENTED!=0 && RW_LINE_IMPLEMENTED!=1)
-  #error RW_LINE_IMPLEMENTED is not defined or not valid.
-#endif
-
-#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED!=1)
-  #error WAIT_MODE=1 requires RW_LINE_IMPLEMENTED=1.
-#endif
-
-#if !defined(LCD_DISPLAYS) || (LCD_DISPLAYS<1) || (LCD_DISPLAYS>4)
-  #error LCD_DISPLAYS is not defined or not valid.
-#endif
-
-// Constants/Macros
-#define PIN(x) (*(&x - 2))           // Address of Data Direction Register of Port X
-#define DDR(x) (*(&x - 1))           // Address of Input Register of Port X
-
-//PORT defines
-#define lcd_rs_port_low() LCD_RS_PORT&=~_BV(LCD_RS_PIN)
-#if RW_LINE_IMPLEMENTED==1
-  #define lcd_rw_port_low() LCD_RW_PORT&=~_BV(LCD_RW_PIN)
-#endif
-#define lcd_db0_port_low() LCD_DB0_PORT&=~_BV(LCD_DB0_PIN)
-#define lcd_db1_port_low() LCD_DB1_PORT&=~_BV(LCD_DB1_PIN)
-#define lcd_db2_port_low() LCD_DB2_PORT&=~_BV(LCD_DB2_PIN)
-#define lcd_db3_port_low() LCD_DB3_PORT&=~_BV(LCD_DB3_PIN)
-#define lcd_db4_port_low() LCD_DB4_PORT&=~_BV(LCD_DB4_PIN)
-#define lcd_db5_port_low() LCD_DB5_PORT&=~_BV(LCD_DB5_PIN)
-#define lcd_db6_port_low() LCD_DB6_PORT&=~_BV(LCD_DB6_PIN)
-#define lcd_db7_port_low() LCD_DB7_PORT&=~_BV(LCD_DB7_PIN)
-
-#define lcd_rs_port_high() LCD_RS_PORT|=_BV(LCD_RS_PIN)
-#if RW_LINE_IMPLEMENTED==1
-  #define lcd_rw_port_high() LCD_RW_PORT|=_BV(LCD_RW_PIN)
-#endif
-#define lcd_db0_port_high() LCD_DB0_PORT|=_BV(LCD_DB0_PIN)
-#define lcd_db1_port_high() LCD_DB1_PORT|=_BV(LCD_DB1_PIN)
-#define lcd_db2_port_high() LCD_DB2_PORT|=_BV(LCD_DB2_PIN)
-#define lcd_db3_port_high() LCD_DB3_PORT|=_BV(LCD_DB3_PIN)
-#define lcd_db4_port_high() LCD_DB4_PORT|=_BV(LCD_DB4_PIN)
-#define lcd_db5_port_high() LCD_DB5_PORT|=_BV(LCD_DB5_PIN)
-#define lcd_db6_port_high() LCD_DB6_PORT|=_BV(LCD_DB6_PIN)
-#define lcd_db7_port_high() LCD_DB7_PORT|=_BV(LCD_DB7_PIN)
-
-#define lcd_rs_port_set(value) if (value) lcd_rs_port_high(); else lcd_rs_port_low();
-#if RW_LINE_IMPLEMENTED==1
-  #define lcd_rw_port_set(value) if (value) lcd_rw_port_high(); else lcd_rw_port_low();
-#endif
-#define lcd_db0_port_set(value) if (value) lcd_db0_port_high(); else lcd_db0_port_low();
-#define lcd_db1_port_set(value) if (value) lcd_db1_port_high(); else lcd_db1_port_low();
-#define lcd_db2_port_set(value) if (value) lcd_db2_port_high(); else lcd_db2_port_low();
-#define lcd_db3_port_set(value) if (value) lcd_db3_port_high(); else lcd_db3_port_low();
-#define lcd_db4_port_set(value) if (value) lcd_db4_port_high(); else lcd_db4_port_low();
-#define lcd_db5_port_set(value) if (value) lcd_db5_port_high(); else lcd_db5_port_low();
-#define lcd_db6_port_set(value) if (value) lcd_db6_port_high(); else lcd_db6_port_low();
-#define lcd_db7_port_set(value) if (value) lcd_db7_port_high(); else lcd_db7_port_low();
-
-//PIN defines
-#define lcd_db0_pin_get() (((PIN(LCD_DB0_PORT) & _BV(LCD_DB0_PIN))==0)?0:1)
-#define lcd_db1_pin_get() (((PIN(LCD_DB1_PORT) & _BV(LCD_DB1_PIN))==0)?0:1)
-#define lcd_db2_pin_get() (((PIN(LCD_DB2_PORT) & _BV(LCD_DB2_PIN))==0)?0:1)
-#define lcd_db3_pin_get() (((PIN(LCD_DB3_PORT) & _BV(LCD_DB3_PIN))==0)?0:1)
-#define lcd_db4_pin_get() (((PIN(LCD_DB4_PORT) & _BV(LCD_DB4_PIN))==0)?0:1)
-#define lcd_db5_pin_get() (((PIN(LCD_DB5_PORT) & _BV(LCD_DB5_PIN))==0)?0:1)
-#define lcd_db6_pin_get() (((PIN(LCD_DB6_PORT) & _BV(LCD_DB6_PIN))==0)?0:1)
-#define lcd_db7_pin_get() (((PIN(LCD_DB7_PORT) & _BV(LCD_DB7_PIN))==0)?0:1)
-
-//DDR defines
-#define lcd_rs_ddr_low() DDR(LCD_RS_PORT)&=~_BV(LCD_RS_PIN)
-#if RW_LINE_IMPLEMENTED==1
-  #define lcd_rw_ddr_low() DDR(LCD_RW_PORT)&=~_BV(LCD_RW_PIN)
-#endif
-#define lcd_db0_ddr_low() DDR(LCD_DB0_PORT)&=~_BV(LCD_DB0_PIN)
-#define lcd_db1_ddr_low() DDR(LCD_DB1_PORT)&=~_BV(LCD_DB1_PIN)
-#define lcd_db2_ddr_low() DDR(LCD_DB2_PORT)&=~_BV(LCD_DB2_PIN)
-#define lcd_db3_ddr_low() DDR(LCD_DB3_PORT)&=~_BV(LCD_DB3_PIN)
-#define lcd_db4_ddr_low() DDR(LCD_DB4_PORT)&=~_BV(LCD_DB4_PIN)
-#define lcd_db5_ddr_low() DDR(LCD_DB5_PORT)&=~_BV(LCD_DB5_PIN)
-#define lcd_db6_ddr_low() DDR(LCD_DB6_PORT)&=~_BV(LCD_DB6_PIN)
-#define lcd_db7_ddr_low() DDR(LCD_DB7_PORT)&=~_BV(LCD_DB7_PIN)
-
-#define lcd_rs_ddr_high() DDR(LCD_RS_PORT)|=_BV(LCD_RS_PIN)
-#if RW_LINE_IMPLEMENTED==1
-  #define lcd_rw_ddr_high() DDR(LCD_RW_PORT)|=_BV(LCD_RW_PIN)
-#endif
-#define lcd_db0_ddr_high() DDR(LCD_DB0_PORT)|=_BV(LCD_DB0_PIN)
-#define lcd_db1_ddr_high() DDR(LCD_DB1_PORT)|=_BV(LCD_DB1_PIN)
-#define lcd_db2_ddr_high() DDR(LCD_DB2_PORT)|=_BV(LCD_DB2_PIN)
-#define lcd_db3_ddr_high() DDR(LCD_DB3_PORT)|=_BV(LCD_DB3_PIN)
-#define lcd_db4_ddr_high() DDR(LCD_DB4_PORT)|=_BV(LCD_DB4_PIN)
-#define lcd_db5_ddr_high() DDR(LCD_DB5_PORT)|=_BV(LCD_DB5_PIN)
-#define lcd_db6_ddr_high() DDR(LCD_DB6_PORT)|=_BV(LCD_DB6_PIN)
-#define lcd_db7_ddr_high() DDR(LCD_DB7_PORT)|=_BV(LCD_DB7_PIN)
-
-#define lcd_rs_ddr_set(value) if (value) lcd_rs_ddr_high(); else lcd_rs_ddr_low();
-#if RW_LINE_IMPLEMENTED==1
-  #define lcd_rw_ddr_set(value) if (value) lcd_rw_ddr_high(); else lcd_rw_ddr_low();
-#endif
-#define lcd_db0_ddr_set(value) if (value) lcd_db0_ddr_high(); else lcd_db0_ddr_low();
-#define lcd_db1_ddr_set(value) if (value) lcd_db1_ddr_high(); else lcd_db1_ddr_low();
-#define lcd_db2_ddr_set(value) if (value) lcd_db2_ddr_high(); else lcd_db2_ddr_low();
-#define lcd_db3_ddr_set(value) if (value) lcd_db3_ddr_high(); else lcd_db3_ddr_low();
-#define lcd_db4_ddr_set(value) if (value) lcd_db4_ddr_high(); else lcd_db4_ddr_low();
-#define lcd_db5_ddr_set(value) if (value) lcd_db5_ddr_high(); else lcd_db5_ddr_low();
-#define lcd_db6_ddr_set(value) if (value) lcd_db6_ddr_high(); else lcd_db6_ddr_low();
-#define lcd_db7_ddr_set(value) if (value) lcd_db7_ddr_high(); else lcd_db7_ddr_low();
-
-#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
-static unsigned char PrevCmdInvolvedAddressCounter=0;
-#endif
-
-#if (LCD_DISPLAYS>1)
-static unsigned char ActiveDisplay=1;
-#endif
-
-static inline void lcd_e_port_low()
-{
-  #if (LCD_DISPLAYS>1)
-  switch (ActiveDisplay)
-    {
-      case 2 : LCD_E2_PORT&=~_BV(LCD_E2_PIN);
-               break;
-      #if (LCD_DISPLAYS>=3)
-      case 3 : LCD_E3_PORT&=~_BV(LCD_E3_PIN);
-               break;
-      #endif
-      #if (LCD_DISPLAYS==4)
-      case 4 : LCD_E4_PORT&=~_BV(LCD_E4_PIN);
-               break;
-      #endif
-      default :
-  #endif
-                LCD_E_PORT&=~_BV(LCD_E_PIN);
-  #if (LCD_DISPLAYS>1)
-    }
-  #endif
-}
-
-static inline void lcd_e_port_high()
-{
-  #if (LCD_DISPLAYS>1)
-  switch (ActiveDisplay)
-    {
-      case 2 : LCD_E2_PORT|=_BV(LCD_E2_PIN);
-               break;
-      #if (LCD_DISPLAYS>=3)
-      case 3 : LCD_E3_PORT|=_BV(LCD_E3_PIN);
-               break;
-      #endif
-      #if (LCD_DISPLAYS==4)
-      case 4 : LCD_E4_PORT|=_BV(LCD_E4_PIN);
-               break;
-      #endif
-      default :
-  #endif
-                LCD_E_PORT|=_BV(LCD_E_PIN);
-  #if (LCD_DISPLAYS>1)
-    }
-  #endif
-}
-
-static inline void lcd_e_ddr_low()
-{
-  #if (LCD_DISPLAYS>1)
-  switch (ActiveDisplay)
-    {
-      case 2 : DDR(LCD_E2_PORT)&=~_BV(LCD_E2_PIN);
-               break;
-      #if (LCD_DISPLAYS>=3)
-      case 3 : DDR(LCD_E3_PORT)&=~_BV(LCD_E3_PIN);
-               break;
-      #endif
-      #if (LCD_DISPLAYS==4)
-      case 4 : DDR(LCD_E4_PORT)&=~_BV(LCD_E4_PIN);
-               break;
-      #endif
-      default :
-  #endif
-                DDR(LCD_E_PORT)&=~_BV(LCD_E_PIN);
-  #if (LCD_DISPLAYS>1)
-    }
-  #endif
-}
-
-static inline void lcd_e_ddr_high()
-{
-  #if (LCD_DISPLAYS>1)
-  switch (ActiveDisplay)
-    {
-      case 2 : DDR(LCD_E2_PORT)|=_BV(LCD_E2_PIN);
-               break;
-      #if (LCD_DISPLAYS>=3)
-      case 3 : DDR(LCD_E3_PORT)|=_BV(LCD_E3_PIN);
-               break;
-      #endif
-      #if (LCD_DISPLAYS==4)
-      case 4 : DDR(LCD_E4_PORT)|=_BV(LCD_E4_PIN);
-               break;
-      #endif
-      default :
-  #endif
-                DDR(LCD_E_PORT)|=_BV(LCD_E_PIN);
-  #if (LCD_DISPLAYS>1)
-    }
-  #endif
-}
-
-
-/*************************************************************************
-loops while lcd is busy, returns address counter
-*************************************************************************/
-#if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
-static uint8_t lcd_read(uint8_t rs);
-
-static void lcd_waitbusy(void)
-  {
-    register uint8_t c;
-    unsigned int ul1=0;
-
-    while ( ((c=lcd_read(0)) & (1<<LCD_BUSY)) && ul1<((F_CPU/16384>=16)?F_CPU/16384:16))     // Wait Until Busy Flag is Cleared
-      ul1++;
-  }
-#endif
-
-
-/*************************************************************************
-Low-level function to read byte from LCD controller
-Input:    rs     1: read data
-                 0: read busy flag / address counter
-Returns:  byte read from LCD controller
-*************************************************************************/
-#if RW_LINE_IMPLEMENTED==1
-static uint8_t lcd_read(uint8_t rs)
-  {
-    uint8_t data;
-    
-    #if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
-    if (rs)
-      lcd_waitbusy();
-      if (PrevCmdInvolvedAddressCounter)
-        {
-          Delay_us(5);
-          PrevCmdInvolvedAddressCounter=0;
-        }
-    #endif
-
-    if (rs)
-      {
-        lcd_rs_port_high();                             // RS=1: Read Data
-        #if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
-        PrevCmdInvolvedAddressCounter=1;
-        #endif
-      }
-    else lcd_rs_port_low();                           // RS=0: Read Busy Flag
-
-    
-    lcd_rw_port_high();                               // RW=1: Read Mode
-
-    #if LCD_BITS==4
-      lcd_db7_ddr_low();                              // Configure Data Pins as Input
-      lcd_db6_ddr_low();
-      lcd_db5_ddr_low();
-      lcd_db4_ddr_low();
-
-      lcd_e_port_high();                              // Read High Nibble First
-      Delay_ns(500);
-
-      data=lcd_db4_pin_get() << 4 | lcd_db5_pin_get() << 5 |
-           lcd_db6_pin_get() << 6 | lcd_db7_pin_get() << 7;
-
-      lcd_e_port_low();
-      Delay_ns(500);
-
-      lcd_e_port_high();                              // Read Low Nibble
-      Delay_ns(500);
-
-      data|=lcd_db4_pin_get() << 0 | lcd_db5_pin_get() << 1 |
-            lcd_db6_pin_get() << 2 | lcd_db7_pin_get() << 3;
-
-      lcd_e_port_low();
-
-      lcd_db7_ddr_high();                             // Configure Data Pins as Output
-      lcd_db6_ddr_high();
-      lcd_db5_ddr_high();
-      lcd_db4_ddr_high();
-
-      lcd_db7_port_high();                            // Pins High (Inactive)
-      lcd_db6_port_high();
-      lcd_db5_port_high();
-      lcd_db4_port_high();
-    #else //using 8-Bit-Mode
-      lcd_db7_ddr_low();                              // Configure Data Pins as Input
-      lcd_db6_ddr_low();
-      lcd_db5_ddr_low();
-      lcd_db4_ddr_low();
-      lcd_db3_ddr_low();
-      lcd_db2_ddr_low();
-      lcd_db1_ddr_low();
-      lcd_db0_ddr_low();
-
-      lcd_e_port_high();
-      Delay_ns(500);
-
-      data=lcd_db7_pin_get() << 7 | lcd_db6_pin_get() << 6 |
-           lcd_db5_pin_get() << 5 | lcd_db4_pin_get() << 4 |
-           lcd_db3_pin_get() << 3 | lcd_db2_pin_get() << 2 |
-           lcd_db1_pin_get() << 1 | lcd_db0_pin_get();
-
-      lcd_e_port_low();
-
-      lcd_db7_ddr_high();                             // Configure Data Pins as Output
-      lcd_db6_ddr_high();
-      lcd_db5_ddr_high();
-      lcd_db4_ddr_high();
-      lcd_db3_ddr_high();
-      lcd_db2_ddr_high();
-      lcd_db1_ddr_high();
-      lcd_db0_ddr_high();
-
-      lcd_db7_port_high();                            // Pins High (Inactive)
-      lcd_db6_port_high();
-      lcd_db5_port_high();
-      lcd_db4_port_high();
-      lcd_db3_port_high();
-      lcd_db2_port_high();
-      lcd_db1_port_high();
-      lcd_db0_port_high();
-    #endif
-    
-    lcd_rw_port_low();
-
-    #if (WAIT_MODE==0 || RW_LINE_IMPLEMENTED==0)
-    if (rs)
-      Delay_us(40);
-    else Delay_us(1);
-    #endif
-    return data;
-  }
-
-uint8_t lcd_getc()
-  {
-    return lcd_read(1);
-  }
-
-#endif
-
-/*************************************************************************
-Low-level function to write byte to LCD controller
-Input:    data   byte to write to LCD
-          rs     1: write data
-                 0: write instruction
-Returns:  none
-*************************************************************************/
-static void lcd_write(uint8_t data,uint8_t rs)
-  {
-    #if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
-      lcd_waitbusy();
-      if (PrevCmdInvolvedAddressCounter)
-        {
-          Delay_us(5);
-          PrevCmdInvolvedAddressCounter=0;
-        }
-    #endif
-
-    if (rs)
-      {
-        lcd_rs_port_high();                            // RS=1: Write Character
-        #if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
-        PrevCmdInvolvedAddressCounter=1;
-        #endif
-      }
-    else
-      {
-        lcd_rs_port_low();                          // RS=0: Write Command
-        #if (WAIT_MODE==1 && RW_LINE_IMPLEMENTED==1)
-        PrevCmdInvolvedAddressCounter=0;
-        #endif
-      }
-
-    #if LCD_BITS==4
-      lcd_db7_port_set(data&_BV(7));                  //Output High Nibble
-      lcd_db6_port_set(data&_BV(6));
-      lcd_db5_port_set(data&_BV(5));
-      lcd_db4_port_set(data&_BV(4));
-
-      Delay_ns(100);
-      lcd_e_port_high();
-
-      Delay_ns(500);
-      lcd_e_port_low();
-
-      lcd_db7_port_set(data&_BV(3));                  //Output High Nibble
-      lcd_db6_port_set(data&_BV(2));
-      lcd_db5_port_set(data&_BV(1));
-      lcd_db4_port_set(data&_BV(0));
-
-      Delay_ns(100);
-      lcd_e_port_high();
-
-      Delay_ns(500);
-      lcd_e_port_low();
-
-      lcd_db7_port_high();                            // All Data Pins High (Inactive)
-      lcd_db6_port_high();
-      lcd_db5_port_high();
-      lcd_db4_port_high();
-
-    #else //using 8-Bit_Mode
-      lcd_db7_port_set(data&_BV(7));                  //Output High Nibble
-      lcd_db6_port_set(data&_BV(6));
-      lcd_db5_port_set(data&_BV(5));
-      lcd_db4_port_set(data&_BV(4));
-      lcd_db3_port_set(data&_BV(3));                  //Output High Nibble
-      lcd_db2_port_set(data&_BV(2));
-      lcd_db1_port_set(data&_BV(1));
-      lcd_db0_port_set(data&_BV(0));
-
-      Delay_ns(100);
-      lcd_e_port_high();
-      Delay_ns(500);
-      lcd_e_port_low();
-
-      lcd_db7_port_high();                            // All Data Pins High (Inactive)
-      lcd_db6_port_high();
-      lcd_db5_port_high();
-      lcd_db4_port_high();
-      lcd_db3_port_high();
-      lcd_db2_port_high();
-      lcd_db1_port_high();
-      lcd_db0_port_high();
-    #endif
-
-    #if (WAIT_MODE==0 || RW_LINE_IMPLEMENTED==0)
-      if (!rs && data<=((1<<LCD_CLR) | (1<<LCD_HOME))) // Is command clrscr or home?
-        Delay_us(1640);
-      else Delay_us(40);
-    #endif
-  }
-
-/*************************************************************************
-Send LCD controller instruction command
-Input:   instruction to send to LCD controller, see HD44780 data sheet
-Returns: none
-*************************************************************************/
-void lcd_command(uint8_t cmd)
-  {
-    lcd_write(cmd,0);
-  }
-
-/*************************************************************************
-Set cursor to specified position
-Input:    pos position
-Returns:  none
-*************************************************************************/
-void lcd_goto(uint8_t pos)
-  {
-    lcd_command((1<<LCD_DDRAM)+pos);
-  }
-
-
-/*************************************************************************
-Clear screen
-Input:    none
-Returns:  none
-*************************************************************************/
-void lcd_clrscr()
-  {
-    lcd_command(1<<LCD_CLR);
-  }
-
-
-/*************************************************************************
-Return home
-Input:    none
-Returns:  none
-*************************************************************************/
-void lcd_home()
-  {
-    lcd_command(1<<LCD_HOME);
-  }
-
-
-/*************************************************************************
-Display character
-Input:    character to be displayed
-Returns:  none
-*************************************************************************/
-void lcd_putc(char c)
-  {
-    lcd_write(c,1);
-  }
-
-
-/*************************************************************************
-Display string
-Input:    string to be displayed
-Returns:  none
-*************************************************************************/
-void lcd_puts(const char *s)
-  {
-    register char c;
-
-    while ((c=*s++)) 
-      lcd_putc(c);
-  }
-
-
-/*************************************************************************
-Display string from flash
-Input:    string to be displayed
-Returns:  none
-*************************************************************************/
-void lcd_puts_P(const char *progmem_s)
-  {
-    register char c;
-
-    while ((c=pgm_read_byte(progmem_s++))) 
-      lcd_putc(c);
-  }
-
-/*************************************************************************
-Initialize display
-Input:    none
-Returns:  none
-*************************************************************************/
-void lcd_init()
-  {
-    //Set All Pins as Output
-    lcd_e_ddr_high();
-    lcd_rs_ddr_high();
-    #if RW_LINE_IMPLEMENTED==1
-      lcd_rw_ddr_high();
-    #endif
-    lcd_db7_ddr_high();
-    lcd_db6_ddr_high();
-    lcd_db5_ddr_high();
-    lcd_db4_ddr_high();
-    #if LCD_BITS==8
-      lcd_db3_ddr_high();
-      lcd_db2_ddr_high();
-      lcd_db1_ddr_high();
-      lcd_db0_ddr_high();
-    #endif
-
-    //Set All Control Lines Low
-    lcd_e_port_low();
-    lcd_rs_port_low();
-    #if RW_LINE_IMPLEMENTED==1
-      lcd_rw_port_low();
-    #endif
-
-    //Set All Data Lines High
-    lcd_db7_port_high();
-    lcd_db6_port_high();
-    lcd_db5_port_high();
-    lcd_db4_port_high();
-    #if LCD_BITS==8
-      lcd_db3_port_high();
-      lcd_db2_port_high();
-      lcd_db1_port_high();
-      lcd_db0_port_high();
-    #endif
-
-    //Startup Delay
-    Delay_ms(DELAY_RESET);
-
-    //Initialize Display
-    lcd_db7_port_low();
-    lcd_db6_port_low();
-    Delay_ns(100);
-    lcd_e_port_high();
-    Delay_ns(500);
-    lcd_e_port_low();
-
-    Delay_us(4100);
-
-    lcd_e_port_high();
-    Delay_ns(500);
-    lcd_e_port_low();
-
-    Delay_us(100);
-
-    lcd_e_port_high();
-    Delay_ns(500);
-    lcd_e_port_low();
-
-    Delay_us(40);
-
-    //Init differs between 4-bit and 8-bit from here
-    #if (LCD_BITS==4)
-      lcd_db4_port_low();
-      Delay_ns(100);
-      lcd_e_port_high();
-      Delay_ns(500);
-      lcd_e_port_low();
-      Delay_us(40);
-
-      lcd_db4_port_low();
-      Delay_ns(100);
-      lcd_e_port_high();
-      Delay_ns(500);
-      lcd_e_port_low();
-      Delay_ns(500);
-
-      #if (LCD_DISPLAYS==1)
-        if (LCD_DISPLAY_LINES>1)
-          lcd_db7_port_high();
-      #else
-        unsigned char c;
-        switch (ActiveDisplay)
-          {
-            case 1 : c=LCD_DISPLAY_LINES; break;
-            case 2 : c=LCD_DISPLAY2_LINES; break;
-            #if (LCD_DISPLAYS>=3)
-            case 3 : c=LCD_DISPLAY3_LINES; break;
-            #endif
-            #if (LCD_DISPLAYS==4)
-            case 4 : c=LCD_DISPLAY4_LINES; break;
-            #endif
-          }
-        if (c>1)
-          lcd_db7_port_high();
-      #endif
-
-      Delay_ns(100);
-      lcd_e_port_high();
-      Delay_ns(500);
-      lcd_e_port_low();
-      Delay_us(40);
-    #else
-      #if (LCD_DISPLAYS==1)
-        if (LCD_DISPLAY_LINES<2)
-          lcd_db3_port_low();
-      #else
-        unsigned char c;
-        switch (ActiveDisplay)
-          {
-            case 1 : c=LCD_DISPLAY_LINES; break;
-            case 2 : c=LCD_DISPLAY2_LINES; break;
-            #if (LCD_DISPLAYS>=3)
-            case 3 : c=LCD_DISPLAY3_LINES; break;
-            #endif
-            #if (LCD_DISPLAYS==4)
-            case 4 : c=LCD_DISPLAY4_LINES; break;
-            #endif
-          }
-        if (c<2)
-          lcd_db3_port_low();
-      #endif
-
-      lcd_db2_port_low();
-      Delay_ns(100);
-      lcd_e_port_high();
-      Delay_ns(500);
-      lcd_e_port_low();
-      Delay_us(40);
-    #endif
-
-    //Display Off
-    lcd_command(_BV(LCD_DISPLAYMODE));
-
-    //Display Clear
-    lcd_clrscr();
-
-    //Entry Mode Set
-    lcd_command(_BV(LCD_ENTRY_MODE) | _BV(LCD_ENTRY_INC));
-
-    //Display On
-    lcd_command(_BV(LCD_DISPLAYMODE) | _BV(LCD_DISPLAYMODE_ON));
-  }
-
-#if (LCD_DISPLAYS>1)
-void lcd_use_display(int ADisplay)
-  {
-    if (ADisplay>=1 && ADisplay<=LCD_DISPLAYS)
-      ActiveDisplay=ADisplay;
-  }
-#endif
-

firmware/hd44780.h

@@ -1,61 +0,0 @@
-/*****************************************************************************
-Title  :   HD44780 Library
-Author :   SA Development
-Version:   1.11
-*****************************************************************************/
-
-#ifndef HD44780_H
-#define HD44780_H
-
-#include "hd44780_settings.h"
-#include "inttypes.h"
-
-//LCD Constants for HD44780
-#define LCD_CLR                 0    // DB0: clear display
-
-#define LCD_HOME                1    // DB1: return to home position
-
-#define LCD_ENTRY_MODE          2    // DB2: set entry mode
-#define LCD_ENTRY_INC           1    // DB1: 1=increment, 0=decrement
-#define LCD_ENTRY_SHIFT         0    // DB0: 1=display shift on
-
-#define LCD_DISPLAYMODE         3    // DB3: turn lcd/cursor on
-#define LCD_DISPLAYMODE_ON      2    // DB2: turn display on
-#define LCD_DISPLAYMODE_CURSOR  1    // DB1: turn cursor on
-#define LCD_DISPLAYMODE_BLINK   0    // DB0: blinking cursor
-
-#define LCD_MOVE                4    // DB4: move cursor/display
-#define LCD_MOVE_DISP           3    // DB3: move display (0-> cursor)
-#define LCD_MOVE_RIGHT          2    // DB2: move right (0-> left)
-
-#define LCD_FUNCTION            5    // DB5: function set
-#define LCD_FUNCTION_8BIT       4    // DB4: set 8BIT mode (0->4BIT mode)
-#define LCD_FUNCTION_2LINES     3    // DB3: two lines (0->one line)
-#define LCD_FUNCTION_10DOTS     2    // DB2: 5x10 font (0->5x7 font)
-
-#define LCD_CGRAM               6    // DB6: set CG RAM address
-#define LCD_DDRAM               7    // DB7: set DD RAM address
-
-#define LCD_BUSY                7    // DB7: LCD is busy
-
-
-void lcd_init();
-void lcd_command(uint8_t cmd);
-
-void lcd_clrscr();
-void lcd_home();
-void lcd_goto(uint8_t pos);
-
-#if RW_LINE_IMPLEMENTED==1
-uint8_t lcd_getc();
-#endif
-
-void lcd_putc(char c);
-void lcd_puts(const char *s);
-void lcd_puts_P(const char *progmem_s);
-#if (LCD_DISPLAYS>1)
-void lcd_use_display(int ADisplay);
-#endif
-
-#endif
-

firmware/hd44780.txt

@@ -1,155 +0,0 @@
-Title  :   HD44780 Library
-Author :   SA Development
-Version:   1.11
-
-Parts of this code have been created or modified by Peter Fleury, Martin Thomas, and Andreas Heinzen as well.  I went through it line by line and modified or improved it as necessary.  This library has been cut down to only what was necessary to communicate with the LCD and does not include scrolling or wrapping features.  See the libraries for the mentioned authors to get those features if you need them.
-
-
-INSTALLATION:
--------------
-
-Three files are provided:
-
-hd44780.c - Main code file, you must add this to your project under "Source Files".
-
-hd44780.h - Main include file, you must include this in any files you wish to use the library.
-
-hd44780_settings_example.h - This is an example of the hd44780_settings.h file that the library requires (and will try to include).  The settings that are intended to be customized for each project are located in this file.
-
-The advantage to this is that the main C/H files are unmodified and can be updated to a new version without losing custom per project settings.  Another advantage is that since they are unmodified, you can put them in a shared or library directory and use them in multiple separate projects.  Then you only have one place to update them instead of multiple project directories.
-
-Two ways you can implement this:
-
-Non-shared method:
-
-1.  Copy these files into your project directory.
-2.  Rename "hd44780_settings_example.h" to "hd44780_settings.h".
-3.  Set the values appropriate to your project in "hd44780_settings.h".
-4.  Add the hd44780.c to your project.
-5.  Put "#include "hd44780.h" in any of your C files that need to use the functions.
-
-
-Shared method:
-
-1.  Create a shared directory.
-2.  Copy these files into this directory.
-
-To use it with a project:
-
-1.  Copy "hd44780_settings_example.h" to your project directory as "hd44780_settings.h".  NOTE THE "_example" was dropped from the filename.
-2.  Set the values appropriate to your project in "hd44780_settings.h".
-3.  Add the hd44780.c to your project.
-4.  Put "#include "..\shared\hd44780.h" in any of your C files that need to use the functions.  You may have to modify this to point to your shared directory.
-5.  Project -> Configuration Options -> Include Directories -> New -> Add your project directory.  It should put a ".\" in the list.  This step is necessary because when the library tries to include "hd44780_settings.h", it will look in your project directory and grab the one customized for that particular project.  This is why it is important NOT to have a hd44780_settings.h in your shared directory and why I have this file named hd44780_settings_example.h instead.  You can leave the example file in the shared directory as a file to copy and rename when starting a new project.
-
-This library will work with my Advanced Delay Library as well by changing the USE_ADELAY_LIBRARY value from 0 to 1.  By default it will use the __builtin_avr_delay_cycles function.  My only gripe about this built in function is that if you are debugging at the assembly level it does not match C code lines to the assembly lines properly.  Other than this it is exceptional.  My Advanced Delay Library accomplishes the same thing while also adding additional delay functions that can expect a variable instead of a constant to be supplied and they don't suffer the C to assembly alignment bug that the built in ones do.
-
-
-HOW TO USE:
------------
-
-Supports LCD communications on as few as 6 pins or as many as 11 pins depending on configuration.
-
-The first choice you must make is whether you want to use 4 bit or 8 bit mode.  Honestly this isn't a hard choice as I've tested both on my scope to see how the performance differed and both were very close to the same under all clock speeds I tested (16khz to 16mhz).  I don't see the point in wasting 4 uC pins for 8 bit mode as it seems to have no advantage.  Use the LCD_BITS parameter to set this:
-
-LCD_BITS=4     // 4 for 4 Bit I/O Mode 
-LCD_BITS=8     // 8 for 8 Bit I/O Mode
-
-The next choice is whether to implement a RW signal or not.  If you don't need to read anything back from the LCD, then you can skip implementing it and simply connect the RW signal to ground.  This is nice because it doesn't take up a uC pin this way.  If however, you need to read something back from the LCD, you will need to implement RW.  Use the RW_LINE_IMPLEMENTED parameter to set this:
-
-RW_LINE_IMPLEMENTED=0     //0 for no RW line (RW on LCD tied to ground)
-RW_LINE_IMPLEMENTED=1     //1 for RW line present
-
-The last big decision is which WAIT_MODE to use.  You can select between Delay Mode or Check Busy Mode.  Delay Mode will delay after each LCD command to make sure that there is time for the LCD to execute the command before the next one can be issued.  Check Busy Mode will read the check busy flag from the LCD to see if the LCD is still busy or ready for the next command.  Check Busy Mode requires the RW line to be implemented, however you can implement an RW line (RW_LINE_IMPLEMENTED=1) and use Delay Mode (WAIT_MODE=0).  You might think that the Check Busy Mode technique would be faster, but it is actually slower when running a clock below 10Mhz.  This is because the extra code is takes to check it takes up more time that the Delay Mode would have.  At 10Mhz or above, Check Busy Mode will be faster.  At 16Mhz, it was 20% faster than Delay Mode, but at 8Mhz Delay Mode was 10% faster.  Use the WAIT_MODE parameter to set this:
-
-WAIT_MODE=0     // 0=Use Delay Method (Faster if running <10Mhz)
-WAIT_MODE=1     // 1=Use Check Busy Flag (Faster if running >10Mhz) ***Requires RW Line***
-
-
-This version implements multiple LCD display support for up to 4 devices.  All devices will share their data/RS/RW(if implemented) pins.  Each device will have its own E(enable) pin.  You can use the command lcd_use_display(x) to choose which display commands will execute on.  You will need to lcd_init() each one individually.  This not only allows you to run 4 independent LCD display, but some displays like the 40 character x 4 line display are actually implemented with 2 lcd controllers.  They will have an E and E2 pin so you will need this multiple display functionallity to use a display like this.
-
-
-To init the display, clear the screen, and output "Hello World...":
-  lcd_init();
-  lcd_clrscr();
-  lcd_puts("Hello World...");
-
-To put a character:
-  lcd_putc('A');
-
-To turn off the display:
-  lcd_command(_BV(LCD_DISPLAYMODE));
-
-To turn on the display:
-  lcd_command(_BV(LCD_DISPLAYMODE) | _BV(LCD_DISPLAYMODE_ON));
-
-To turn on the display AND display an underline cursor:
-  lcd_command(_BV(LCD_DISPLAYMODE) | _BV(LCD_DISPLAYMODE_ON) | _BV(LCD_DISPLAYMODE_CURSOR));
-
-To turn on the display AND display a blinking cursor:
-  lcd_command(_BV(LCD_DISPLAYMODE) | _BV(LCD_DISPLAYMODE_ON) | _BV(LCD_DISPLAYMODE_BLINK));
-
-To move the cursor to the left:
-  lcd_command(_BV(LCD_MOVE));
-
-To move the cursor to the right:
-  lcd_command(_BV(LCD_MOVE) | _BV(LCD_MOVE_RIGHT));
-
-To move the cursor to a specific location:
-  lcd_goto(0x40); //0x40 is often the beginning of the second line
-                  //each LCD display will have its memory mapped
-                  //differently
-
-To create a custom character:
-  lcd_command(_BV(LCD_CGRAM)+0*8);    //The 0 on this line may be 0-7
-  lcd_putc(0b00000); //5x8 bitmap of character, in this example a backslash
-  lcd_putc(0b10000);
-  lcd_putc(0b01000);
-  lcd_putc(0b00100);
-  lcd_putc(0b00010);
-  lcd_putc(0b00001);
-  lcd_putc(0b00000);
-  lcd_putc(0b00000);
-  lcd_goto(0);       //DO NOT FORGET to issue a GOTO command to go back to writing to the LCD
-                     //ddram OR you will spend hours like me thinking the LCD is locked up 
-                     //when it working just fine and you are outputting to cgram instead of 
-                     //ddram!
-
-To display this custom character:
-  lcd_putc(0);                        //Displays custom character 0
-
-To shift the display so that the characters on screen are pushed to the left:
-  lcd_command(_BV(LCD_MOVE) | _BV(LCD_MOVE_DISP));
-
-To shift the display so that the characters on screen are pushed to the left:
-  lcd_command(_BV(LCD_MOVE) | _BV(LCD_MOVE_DISP) | _BV(LCD_MOVE_RIGHT));     
-
-
-VERSION HISTORY:
-----------------
-
-1.00 - Initial version.
-
-1.02 - Delay_ns, Delay_us, and Delay_ms added via a new included file "delay.h". All of these functions support values from 1-65535 so you can delay 65.535 seconds using Delay_ms, or Delay_ns(1) to delay 1ns. Realize that a delay of 1ns would only be possible if you were running at 1ghz, but asking for 1ns delay will get you a single clock delay. At 8mhz this is 125ns. The delays will get you "at least" what you ask for with as little more as possible.  The reason the delay functions were added is because the LCD library I based this on "assumed" that 2 clocks were enough for a 500ns wait. This is TRUE if you are running at less than 2mhz, but not true if you are running faster. I modified these functions to use the new Delay_ns function above so it will ALWAYS wait 500ns on the enable line now.
-
-1.03 - No longer includes my delay functions, but instead uses the internal builtin_avr_delay_cycles instead.  You can still use it with my Advanced Delay Library, check the C file for info.  This version also adds a clrscr in the init function. I was experiencing issues where a reset would corrupt part of the screen so this was necessary to make sure it starts clear.
-
-1.05 - Reorganized all code to follow the standard C and H file techniques.
-
-1.10 - Multiple LCD display support (Up to 4) added.
-
-       Bugs in the read command and 8 bit modes fixed and tested.
-       
-       You are now able to put any pins on any pin and port.  The data pins are no longer required to be on 0-3 or 0-7.  This gives you full freedom to put these pins anywhere.
-
-       All pin changes are now done through SBI CBI instructions meaning there will be zero problems with interrupts of other things occuring on pins of the same port as the LCD pins.
-
-       Checkbusy used to end up in an infinite loop if the LCD didn't response with "not busy".  I have put a 3ms maximum time on it (or 16 attempts minimum).  Since all LCD commands should run with 1.64ms, this should be more than enough and will allow the processor to continue on instead of being permanently stuck.  The delay however at 3ms everytime a call is made to the LCD will probably slow things down too much anyway, but I figured having this limit was better than nothing.
-
-1.11 - A big issue in the LCD init code has been corrected which will now allow 4-bit mode to work properly below 2mhz.  I've tested both 4-bit and 8-bit modes from 16khz to 16mhz with no issues.
-
-       Many commands have been marked as static if you don't need to access them, the only change is that lcd_read(x) is no longer available.  You must use lcd_getc() instead.
-
-       RW_LINE_IMPLEMENTED has been added which allows you to indicate whether you are implementing the RW line or not.  This used to be part of the WAIT_MODE, but having this option now allows you to implement the RW line so you can read from the LCD, but still use WAIT_MODE=0 for delays instead of using the check busy flag.
-
-       Check Busy has had an additional 6us delay added to it when the previous command involved a read or write that changes the address pointer.  This is due to the check busy flag going low before this pointer is updated and is to ensure the LCD is ready for another command.

firmware/hd44780_settings.h

@@ -1,49 +0,0 @@
-#ifndef HD44780_SETTINGS_H
-#define HD44780_SETTINGS_H
-
-// This is done in the makefile
-// #define F_CPU                    15855484     // Set Clock Frequency
-
-#define USE_ADELAY_LIBRARY       0           // Set to 1 to use my ADELAY library, 0 to use internal delay functions
-#define LCD_BITS                 4           // 4 for 4 Bit I/O Mode, 8 for 8 Bit I/O Mode
-#define RW_LINE_IMPLEMENTED      1           // 0 for no RW line (RW on LCD tied to ground), 1 for RW line present
-#define WAIT_MODE                1           // 0=Use Delay Method (Faster if running <10Mhz)
-                                             // 1=Use Check Busy Flag (Faster if running >10Mhz) ***Requires RW Line***
-#define DELAY_RESET              15          // in mS
-
-#if (LCD_BITS==8)                            // If using 8 bit mode, you must configure DB0-DB7
-  #define LCD_DB0_PORT           PORTA
-  #define LCD_DB0_PIN            0
-  #define LCD_DB1_PORT           PORTA
-  #define LCD_DB1_PIN            1
-  #define LCD_DB2_PORT           PORTA
-  #define LCD_DB2_PIN            2
-  #define LCD_DB3_PORT           PORTA
-  #define LCD_DB3_PIN            3
-#endif
-#define LCD_DB4_PORT             PORTA       // If using 4 bit omde, yo umust configure DB4-DB7
-#define LCD_DB4_PIN              4
-#define LCD_DB5_PORT             PORTA
-#define LCD_DB5_PIN              5
-#define LCD_DB6_PORT             PORTA
-#define LCD_DB6_PIN              6
-#define LCD_DB7_PORT             PORTA
-#define LCD_DB7_PIN              7
-
-#define LCD_RS_PORT              PORTA       // Port for RS line
-#define LCD_RS_PIN               0           // Pin for RS line
-
-#define LCD_RW_PORT              PORTA       // Port for RW line (ONLY used if RW_LINE_IMPLEMENTED=1)
-#define LCD_RW_PIN               1           // Pin for RW line (ONLY used if RW_LINE_IMPLEMENTED=1)
-
-#define LCD_DISPLAYS             1           // Up to 4 LCD displays can be used at one time
-                                             // All pins are shared between displays except for the E
-                                             // pin which each display will have its own
-
-                                             // Display 1 Settings - if you only have 1 display, YOU MUST SET THESE
-#define LCD_DISPLAY_LINES        1           // Number of Lines, Only Used for Set I/O Mode Command
-#define LCD_E_PORT               PORTA       // Port for E line
-#define LCD_E_PIN                2           // Pin for E line
-
-#endif
-

firmware/regs6502.c

@@ -12,18 +12,23 @@ char statusString[8] = "NV-BDIZC";
 void doCmdRegs(char *params) {
   int i;
   unsigned int p = hwRead8(OFFSET_REG_P);
-  log0("6502 Registers:\n  A=%02X X=%02X Y=%02X SP=%04X PC=%04X\n",
-       hwRead8(OFFSET_REG_A),
-       hwRead8(OFFSET_REG_X),
-       hwRead8(OFFSET_REG_Y),
-       hwRead16(OFFSET_REG_SP),
-       hwRead16(OFFSET_REG_PC));
+  logstr("6502 Registers:\n  A=");
+  loghex2(hwRead8(OFFSET_REG_A));
+  logstr(" X=");
+  loghex2(hwRead8(OFFSET_REG_X));
+  logstr(" Y=");
+  loghex2(hwRead8(OFFSET_REG_Y));
+  logstr(" SP=01");
+  loghex2(hwRead8(OFFSET_REG_SP));
+  logstr(" PC=");
+  loghex4(hwRead16(OFFSET_REG_PC));
+  logc('\n');
   char *sp = statusString;
-  log0("  Status: ");
+  logstr("  Status: ");
   for (i = 0; i <= 7; i++) {
-    log0("%c",  ((p & 128) ? (*sp) : '-'));
+    logc(((p & 128) ? (*sp) : '-'));
     p <<= 1;
     sp++;
   }
-  log0("\n");
+  logc('\n');
 }

firmware/regs6809.c

@@ -10,28 +10,35 @@
 #define OFFSET_REG_D   44
 #define OFFSET_REG_CC  45
 
-char statusString[8] = "EFHINZVC";
+const char statusString[8] = "EFHINZVC";
 
 void doCmdRegs(char *params) {
-  int i;
-  unsigned int p = hwRead8(OFFSET_REG_CC);
-  log0("6809 Registers:\n   A=%02X B=%02X X=%04X Y=%04X\n",
-       hwRead8(OFFSET_REG_A),
-       hwRead8(OFFSET_REG_B),
-       hwRead16(OFFSET_REG_X),
-       hwRead16(OFFSET_REG_Y));
-  log0("  CC=%02X D=%02X U=%04X S=%04X PC=%04X\n",
-       p,
-       hwRead8(OFFSET_REG_D),
-       hwRead16(OFFSET_REG_U),
-       hwRead16(OFFSET_REG_S),
-       hwRead16(OFFSET_REG_PC));
-  char *sp = statusString;
-  log0("  Status: ");
+  uint16_t i;
+  uint8_t p = hwRead8(OFFSET_REG_CC);
+  const char *sp = statusString;
+  logstr("6809 Registers:\n   A=");
+  loghex2(hwRead8(OFFSET_REG_A));
+  logstr(" B=");
+  loghex2(hwRead8(OFFSET_REG_B));
+  logstr(" X=");
+  loghex4(hwRead16(OFFSET_REG_X));
+  logstr(" Y=");
+  loghex4(hwRead16(OFFSET_REG_Y));
+  logstr("\n  CC=");
+  loghex2(p);
+  logstr(" D=");
+  loghex2(hwRead8(OFFSET_REG_D));
+  logstr(" U=");
+  loghex4(hwRead16(OFFSET_REG_U));
+  logstr(" S=");
+  loghex4(hwRead16(OFFSET_REG_S));
+  logstr(" PC=");
+  loghex4(hwRead16(OFFSET_REG_PC));
+  logstr("\n  Status: ");
   for (i = 0; i <= 7; i++) {
-    log0("%c",  ((p & 128) ? (*sp) : '-'));
+    logc(((p & 128) ? (*sp) : '-'));
     p <<= 1;
     sp++;
   }
-  log0("\n");
+  logc('\n');
 }

firmware/regsz80.c

@@ -1,51 +1,72 @@
 #include "AtomBusMon.h"
 
-#define OFFSET_REG_BC  32
-#define OFFSET_REG_DE  34
-#define OFFSET_REG_HL  36
-#define OFFSET_REG_IX  38
-#define OFFSET_REG_BCp 40
-#define OFFSET_REG_DEp 42
-#define OFFSET_REG_HLp 44
-#define OFFSET_REG_IY  46
-#define OFFSET_REG_AF  48
-#define OFFSET_REG_AFp 50
-#define OFFSET_REG_SP  52
-#define OFFSET_REG_PC  54
-#define OFFSET_REG_I   56
-#define OFFSET_REG_R   57
-#define OFFSET_REG_IFF 58
+// Version 350 of T80 exposes the registers in this order (bit 211..bit 0):
+// IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
 
-char statusString[8] = "SZIH-P-C";
+#define OFFSET_REG_AF      (32 + 0)
+#define OFFSET_REG_AFp     (32 + 2)
+#define OFFSET_REG_I       (32 + 4)
+#define OFFSET_REG_R       (32 + 5)
+#define OFFSET_REG_SP      (32 + 6)
+#define OFFSET_REG_PC      (32 + 8)
+#define OFFSET_REG_BCDEHL  (32 + 10)
+#define OFFSET_REG_IX      (32 + 16)
+#define OFFSET_REG_BCDEHLp (32 + 18)
+#define OFFSET_REG_IY      (32 + 24)
+#define OFFSET_REG_IFF     (32 + 26)
 
-void doCmdRegs(char *params) {
-  int i;
-  unsigned int p = hwRead16(OFFSET_REG_AF);
-  log0("Z80 Registers:\n");
-  log0("   AF=%04X  BC=%04X  DE=%04X  HL=%04X\n",
-       p,
-       hwRead16(OFFSET_REG_BC),
-       hwRead16(OFFSET_REG_DE),
-       hwRead16(OFFSET_REG_HL));
-  log0("  'AF=%04X 'BC=%04X 'DE=%04X 'HL=%04X\n",
-       hwRead16(OFFSET_REG_AFp),
-       hwRead16(OFFSET_REG_BCp),
-       hwRead16(OFFSET_REG_DEp),
-       hwRead16(OFFSET_REG_HLp));
-  log0("   IX=%04X  IY=%04X  PC=%04X  SP=%04X I=%02X R=%02X IFF=%02X\n",
-       hwRead16(OFFSET_REG_IX),
-       hwRead16(OFFSET_REG_IY),
-       hwRead16(OFFSET_REG_PC),
-       hwRead16(OFFSET_REG_SP),
-       hwRead8(OFFSET_REG_I),
-       hwRead8(OFFSET_REG_R),
-       hwRead8(OFFSET_REG_IFF));
+char statusString[8] = "SZYHXPNC";
+
+void output_abcdehlf(char *prefix, uint8_t base_af, uint8_t base_bcdehl) {
+  uint16_t i;
+  logs(prefix);
+  logstr("A=");
+  loghex2(hwRead8(base_af));
+  logs(prefix);
+  logstr("BC=");
+  loghex4(hwRead16(base_bcdehl));
+  logs(prefix);
+  logstr("DE=");
+  loghex4(hwRead16(base_bcdehl + 2));
+  logs(prefix);
+  logstr("HL=");
+  loghex4(hwRead16(base_bcdehl + 4));
+  logs(prefix);
+  logstr("F=");
+  uint8_t p = hwRead8(base_af + 1);
+  loghex2(p);
+  logstr(" (");
   char *sp = statusString;
-  log0("  Status: ");
   for (i = 0; i <= 7; i++) {
-    log0("%c",  ((p & 128) ? (*sp) : '-'));
+    logc(((p & 128) ? (*sp) : '-'));
     p <<= 1;
     sp++;
   }
-  log0("\n");
+  logs(")\n");
+}
+
+void doCmdRegs(char *params) {
+  int iff2_iff1_im = hwRead8(OFFSET_REG_IFF) & 15;
+  logstr("Z80 Registers:\n");
+  output_abcdehlf("  ", OFFSET_REG_AF,  OFFSET_REG_BCDEHL);
+  output_abcdehlf(" '", OFFSET_REG_AFp, OFFSET_REG_BCDEHLp);
+  logstr("  R=");
+  loghex2(hwRead8(OFFSET_REG_R));
+  logstr("  IX=");
+  loghex4(hwRead16(OFFSET_REG_IX));
+  logstr("  IY=");
+  loghex4(hwRead16(OFFSET_REG_IY));
+  logstr("  PC=");
+  loghex4(hwRead16(OFFSET_REG_PC));
+  logstr(" SP=");
+  loghex4(hwRead16(OFFSET_REG_SP));
+  logstr(" I=");
+  loghex2(hwRead8(OFFSET_REG_I));
+  logstr(" IM=");
+  loghex1((iff2_iff1_im & 3));
+  logstr(" IFF1=");
+  loghex1((iff2_iff1_im >> 2) & 1);
+  logstr(" IFF2=");
+  loghex1((iff2_iff1_im >> 3) & 1);
+  logc('\n');
 }

firmware/status.c

@@ -1,293 +1,308 @@
-/*
-	Status.c
-	
-	Functions for logging program status to the serial port, to
-	be used for debugging pruposes etc.
-	
-	2008-03-21, P.Harvey-Smith.
-	
-*/
-
-#include <avr/interrupt.h>
-#include <stdio.h>
-#include <ctype.h>
-#include "terminalcodes.h"
-#include "status.h"
-
-#ifdef SERIAL_STATUS
-
-static int StdioSerial_TxByte0(char DataByte, FILE *Stream);
-static int StdioSerial_TxByte1(char DataByte, FILE *Stream);
-
-FILE ser0stream = FDEV_SETUP_STREAM(StdioSerial_TxByte0,NULL,_FDEV_SETUP_WRITE);
-FILE ser1stream = FDEV_SETUP_STREAM(StdioSerial_TxByte1,NULL,_FDEV_SETUP_WRITE);
-
-void StdioSerial_TxByte(char DataByte, uint8_t	Port)
-{
-	#ifdef COOKED_SERIAL	
-		if((DataByte=='\r') || (DataByte=='\n'))
-		{
-			if(Port==1)
-			{
-				Serial_TxByte1('\r');
-				Serial_TxByte1('\n');
-			}
-			else
-			{
-				Serial_TxByte0('\r');
-				Serial_TxByte0('\n');
-			}
-		}
-		else
-	#endif
-	
-	if(Port==1)
-		Serial_TxByte1(DataByte);
-	else
-		Serial_TxByte0(DataByte);
-	
-}
-
-int StdioSerial_TxByte0(char DataByte, FILE *Stream)
-{
-	StdioSerial_TxByte(DataByte,0);
-	return 0;
-}
-
-int StdioSerial_TxByte1(char DataByte, FILE *Stream)
-{
-	StdioSerial_TxByte(DataByte,1);
-	return 0;
-}
-
-void cls(uint8_t	Port)
-{
-	if(Port==1)
-	{
-		log1(ESC_ERASE_DISPLAY);
-		log1(ESC_CURSOR_POS(0,0));
-	}
-	else
-	{
-		log0(ESC_ERASE_DISPLAY);
-		log0(ESC_CURSOR_POS(0,0));
-	}
-}
-
-
-void USART_Init0(const uint32_t BaudRate)
-{
-#ifdef UCSR0A
-	UCSR0A = 0;
-	UCSR0B = ((1 << RXEN0) | (1 << TXEN0));
-	UCSR0C = ((1 << UCSZ01) | (1 << UCSZ00));
-	
-	UBRR0  = SERIAL_UBBRVAL(BaudRate);
-#else
-	UCR = ((1 << RXEN)  | (1 << TXEN));
-	
-	UBRR  	= SERIAL_UBBRVAL(BaudRate);
-#endif
-}
-
-
-void USART_Init1(const uint32_t BaudRate)
-{
-#ifdef UCSR1A
-	UCSR1A = 0;
-	UCSR1B = ((1 << RXEN1) | (1 << TXEN1));
-	UCSR1C = ((1 << UCSZ11) | (1 << UCSZ10));
-	
-	UBRR1  = SERIAL_UBBRVAL(BaudRate);
-#endif
-}
-
-/** Transmits a given byte through the USART.
- *
- *  \param DataByte  Byte to transmit through the USART
- */
-void Serial_TxByte0(const char DataByte)
-{
-#ifdef UCSR0A
-	while ( !( UCSR0A & (1<<UDRE0)) )		;
-	UDR0=DataByte;
-#else
-	while ( !( USR & (1<<UDRE)) )		;
-	UDR=DataByte;
-#endif
-}
-
-void Serial_TxByte1(const char DataByte)
-{
-#ifdef UCSR1A
-	while ( !( UCSR1A & (1<<UDRE1)) )		;
-	UDR1=DataByte;
-#endif
-}
-
-
-/** Receives a byte from the USART.
- *
- *  \return Byte received from the USART
- */
-char Serial_RxByte0(void)
-{
-#ifdef UCSR0A
-	while (!(USR & (1 << RXC0)))	;
-	return UDR0;
-#else 
-	while (!(USR & (1<<RXC)))	;
-	return UDR;
-#endif
-}
-
-char Serial_RxByte1(void)
-{
-#ifdef UCSR1A
-	while (!(UCSR1A & (1 << RXC1)))	;
-	return UDR1;
-#else
-	return 0;
-#endif
-}
-
-uint8_t Serial_ByteRecieved0(void)
-{
-#ifdef UCSR0A
-	return (UCSR0A & (1 << RXC0));
-#else
-	return (USR & (1<<RXC));
-#endif
-}
-
-uint8_t Serial_ByteRecieved1(void)
-{
-#ifdef UCSR1A
-	return (UCSR1A & (1 << RXC1));
-#else
-	return 0;
-#endif
-}
-
-void Serial_Init(const uint32_t BaudRate0,
-				 const uint32_t BaudRate1)
-{
-	if (BaudRate0<=0)
-		USART_Init0(DefaultBaudRate);
-	else
-		USART_Init0(BaudRate0);
-
-	if (BaudRate1<=0)
-		USART_Init1(DefaultBaudRate);
-	else
-		USART_Init1(BaudRate1);
-		
-	cls(0);
-	cls(1);
-	
-	// log0("stdio initialised\n");
-	// log0("SerialPort0\n");
-	// log1("SerialPort1\n");
-}
-
-#ifdef USE_HEXDUMP
-void HexDump(const uint8_t 	*Buff, 
-				   uint16_t Length,
-				   uint8_t	Port)
-{
-	char		LineBuff[80];
-	char		*LineBuffPos;
-	uint16_t	LineOffset;
-	uint16_t	CharOffset;
-	const uint8_t		*BuffPtr;
-	
-	BuffPtr=Buff;
-	
-	for(LineOffset=0;LineOffset<Length;LineOffset+=16, BuffPtr+=16)
-	{
-		LineBuffPos=LineBuff;
-		LineBuffPos+=sprintf(LineBuffPos,"%4.4X ",LineOffset);
-		
-		for(CharOffset=0;CharOffset<16;CharOffset++)
-		{
-			if((LineOffset+CharOffset)<Length)
-				LineBuffPos+=sprintf(LineBuffPos,"%2.2X ",BuffPtr[CharOffset]);
-			else
-			    LineBuffPos+=sprintf(LineBuffPos,"   ");
-		}
-		
-		for(CharOffset=0;CharOffset<16;CharOffset++)
-		{
-			if((LineOffset+CharOffset)<Length)
-			{
-				if(isprint(BuffPtr[CharOffset]))
-					LineBuffPos+=sprintf(LineBuffPos,"%c",BuffPtr[CharOffset]);
-				else
-					LineBuffPos+=sprintf(LineBuffPos," ");
-			}
-			else
-				LineBuffPos+=sprintf(LineBuffPos,".");
-		}
-		switch (Port)
-		{
-			case 0 : log0("%s\n",LineBuff); break;
-			case 1 : log1("%s\n",LineBuff); break;
-		}
-	}
-}
-
-void HexDumpHead(const uint8_t 	*Buff, 
-				       uint16_t Length,
-				       uint8_t	Port) 
-{
-	FILE	*File;
-
-	File=&ser0stream;
-	
-	switch (Port)
-	{
-		case 0 : File=&ser0stream; break;
-		case 1 : File=&ser1stream; break;
-	}
-	
-	fprintf_P(File,PSTR("%d\n"),Buff);
-
-	fprintf_P(File,PSTR("Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ASCII\n"));
-	fprintf_P(File,PSTR("----------------------------------------------------------\n"));
-
-	HexDump(Buff,Length,Port);
-};
-#else
-void HexDump(const uint8_t 	*Buff, 
-				   uint16_t Length,
-				   uint8_t	Port) {};
-void HexDumpHead(const uint8_t 	*Buff, 
-				       uint16_t Length,
-				       uint8_t	Port) {};
-#endif 
-
-#else
-
-void USART_Init0(const uint32_t BaudRate) {};
-void Serial_TxByte0(const char DataByte) {};
-char Serial_RxByte0(void) {};
-uint8_t Serial_ByteRecieved0(void) {};
-
-void USART_Init1(const uint32_t BaudRate) {};
-void Serial_TxByte1(const char DataByte) {};
-char Serial_RxByte1(void) {};
-uint8_t Serial_ByteRecieved1(void) {};
-
-void Serial_Init(const uint32_t BaudRate0,
-				 const uint32_t BaudRate1) {};
-
-void cls(uint8_t	Port) {};
-
-void HexDump(const uint8_t 	*Buff, 
-				   uint16_t Length,
-				   uint8_t	Port) {};
-void HexDumpHead(const uint8_t 	*Buff, 
-				       uint16_t Length,
-				       uint8_t	Port) {};
-
-#endif
+/*
+	Status.c
+
+	Functions for logging program status to the serial port, to
+	be used for debugging pruposes etc.
+
+	2008-03-21, P.Harvey-Smith.
+
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "terminalcodes.h"
+#include "status.h"
+
+static int StdioSerial_TxByte0(char DataByte, FILE *Stream);
+
+FILE ser0stream = FDEV_SETUP_STREAM(StdioSerial_TxByte0,NULL,_FDEV_SETUP_WRITE);
+
+void StdioSerial_TxByte(char DataByte)
+{
+  if((DataByte=='\r') || (DataByte=='\n')) {
+    Serial_TxByte0('\r');
+    Serial_TxByte0('\n');
+  } else {
+    Serial_TxByte0(DataByte);
+  }
+}
+
+int StdioSerial_TxByte0(char DataByte, FILE *Stream)
+{
+	StdioSerial_TxByte(DataByte);
+	return 0;
+}
+
+void cls()
+{
+  logs(ESC_ERASE_DISPLAY);
+  logs(ESC_CURSOR_POS(0,0));
+}
+
+
+void USART_Init0(const uint32_t BaudRate)
+{
+#ifdef UCSR0A
+	UCSR0A = 0;
+	UCSR0B = ((1 << RXEN0) | (1 << TXEN0));
+	UCSR0C = ((1 << UCSZ01) | (1 << UCSZ00));
+
+	UBRR0  = SERIAL_UBBRVAL(BaudRate);
+#else
+	UCR = ((1 << RXEN)  | (1 << TXEN));
+
+	UBRR  	= SERIAL_UBBRVAL(BaudRate);
+#endif
+}
+
+/** Transmits a given byte through the USART.
+ *
+ *  \param DataByte  Byte to transmit through the USART
+ */
+void Serial_TxByte0(const char DataByte)
+{
+#ifdef UCSR0A
+	while ( !( UCSR0A & (1<<UDRE0)) )		;
+	UDR0=DataByte;
+#else
+	while ( !( USR & (1<<UDRE)) )		;
+	UDR=DataByte;
+#endif
+}
+
+/** Receives a byte from the USART.
+ *
+ *  \return Byte received from the USART
+ */
+char Serial_RxByte0(void)
+{
+#ifdef UCSR0A
+	while (!(USR & (1 << RXC0)))	;
+	return UDR0;
+#else
+	while (!(USR & (1<<RXC)))	;
+	return UDR;
+#endif
+}
+
+uint8_t Serial_ByteRecieved0(void)
+{
+#ifdef UCSR0A
+	return (UCSR0A & (1 << RXC0));
+#else
+	return (USR & (1<<RXC));
+#endif
+}
+
+void Serial_Init(const uint32_t BaudRate0)
+{
+	if (BaudRate0<=0)
+		USART_Init0(DefaultBaudRate);
+	else
+		USART_Init0(BaudRate0);
+
+	cls();
+}
+
+/********************************************************
+ * Simple string logger, as log0 is expensive
+ ********************************************************/
+
+void logc(char c) {
+  StdioSerial_TxByte(c);
+}
+
+void logs(const char *s) {
+  while (*s) {
+    logc(*s++);
+  }
+}
+
+void logpgmstr(const char *s) {
+  char c;
+  do {
+    c = pgm_read_byte(s++);
+    if (c) {
+      logc(c);
+    }
+  } while (c);
+}
+
+char hex1(uint8_t i) {
+  i &= 0x0f;
+  if (i < 10) {
+    i += '0';
+  } else {
+    i += ('A' - 10);
+  }
+  return i;
+}
+
+void loghex1(uint8_t i) {
+  logc(hex1(i));
+}
+
+void loghex2(uint8_t i) {
+  loghex1(i >> 4);
+  loghex1(i);
+}
+
+void loghex4(uint16_t i) {
+  loghex2(i >> 8);
+  loghex2(i);
+}
+
+void logint(int i) {
+  char buffer[16];
+  strint(buffer, i);
+  logs(buffer);
+}
+
+void loglong(long i) {
+  char buffer[16];
+  strlong(buffer, i);
+  logs(buffer);
+}
+
+char *strfill(char *buffer, char c, uint8_t i) {
+  while (i-- > 0) {
+    *buffer++ = c;
+  }
+  return buffer;
+}
+
+char *strhex1(char *buffer, uint8_t i) {
+  *buffer++ = hex1(i);
+  return buffer;
+}
+
+char *strhex2(char *buffer, uint8_t i) {
+  buffer = strhex1(buffer, i >> 4);
+  buffer = strhex1(buffer, i);
+  return buffer;
+}
+
+char *strhex4(char *buffer, uint16_t i) {
+  buffer = strhex2(buffer, i >> 8);
+  buffer = strhex2(buffer, i);
+  return buffer;
+}
+
+char *strint(char *buffer, int i) {
+  return itoa(i, buffer, 10);
+}
+
+char *strlong(char *buffer, long i) {
+  return ltoa(i, buffer, 10);
+}
+
+char *strinsert(char *buffer, const char *s) {
+  while (*s) {
+    *buffer++ = *s++;
+  }
+  return buffer;
+}
+
+int8_t convhex(char c) {
+  // Make range continuous
+  if (c >= 'a' && c <= 'f') {
+    c -= 'a' - '9' - 1;
+  } else if (c >= 'A' && c <= 'F') {
+    c -= 'A' - '9' - 1;
+  }
+  if (c >= '0' && c <= '0' + 15) {
+    return c & 0x0F;
+  } else {
+    return -1;
+  }
+}
+
+int8_t convdec(char c) {
+  if (c >= '0' && c <= '0' + 9) {
+    return c & 0x0F;
+  } else {
+    return -1;
+  }
+}
+
+char *parselong(char *params, long *val) {
+  long ret = 0;
+  int8_t sign = 1;
+  // Skip any spaces
+  if (params) {
+    while (*params == ' ') {
+      params++;
+    }
+    // Note sign
+    if (*params == '-') {
+      sign = -1;
+      params++;
+    }
+    do {
+      int8_t c = convhex(*params);
+      if (c < 0) {
+        break;
+      }
+      ret *= 10;
+      ret += c;
+      if (val) {
+        *val = sign * ret;
+      }
+      params++;
+    } while (1);
+  }
+  return params;
+}
+
+static char *parsehex4common(char *params, uint16_t *val, uint8_t required) {
+  uint16_t ret = 0;
+  if (params) {
+    // Skip any spaces
+    while (*params == ' ') {
+      params++;
+    }
+    char *tmp = params;
+    do {
+      int8_t c = convhex(*params);
+      if (c < 0) {
+        break;
+      }
+      ret <<= 4;
+      ret += c;
+      if (val) {
+        *val = ret;
+      }
+      params++;
+    } while (1);
+    if (required && params == tmp) {
+      return 0;
+    }
+  }
+  return params;
+}
+
+char *parsehex4(char *params, uint16_t *val) {
+  return parsehex4common(params, val, 0);
+}
+
+char *parsehex4required(char *params, uint16_t *val) {
+  return parsehex4common(params, val, 1);
+}
+
+char *parsehex2(char *params, uint8_t *val) {
+  uint16_t tmp = 0xffff;
+  params = parsehex4common(params, &tmp, 0);
+  if (tmp != 0xffff) {
+    *val = (tmp & 0xff);
+  }
+  return params;
+}
+
+char *parsehex2required(char *params, uint8_t *val) {
+  uint16_t tmp = 0xffff;
+  params = parsehex4common(params, &tmp, 1);
+  if (tmp != 0xffff) {
+    *val = (tmp & 0xff);
+  }
+  return params;
+}

firmware/status.h

@@ -1,85 +1,95 @@
-/*
-	Status.h
-	
-	Functions for logging program status to the serial port, to
-	be used for debugging pruposes etc.
-	
-	2008-03-21, P.Harvey-Smith.
-
-	Some functions and macros borrowed from Dean Camera's LURFA 
-	USB libraries.
-	
-*/
-
-#include <avr/io.h>
-#include <avr/pgmspace.h>
-#include <stdbool.h>
-#include <stdio.h>
-
-
-#ifndef __STATUS_DEFINES__
-#define __STATUS_DEFINES__
-
-#ifdef SERIAL_STATUS
-#define log0(format,...) fprintf_P(&ser0stream,PSTR(format),##__VA_ARGS__) 
-#define log1(format,...) fprintf_P(&ser1stream,PSTR(format),##__VA_ARGS__)
-#else
-#define log0(format,...) 
-#define log1(format,...) 
-#endif
-
-//
-// For stdio
-//
-
-extern FILE ser0stream;
-extern FILE ser1stream;
-
-/* Default baud rate if 0 passed to Serial_Init */
-  
-#define DefaultBaudRate	9600
-
-/** Indicates whether a character has been received through the USART - boolean false if no character
- *  has been received, or non-zero if a character is waiting to be read from the reception buffer.
- */
-#define Serial_IsCharReceived() ((UCSR1A & (1 << RXC1)) ? true : false)
-
-/** Macro for calculating the baud value from a given baud rate when the U2X (double speed) bit is
- *  not set.
- */
-#define SERIAL_UBBRVAL(baud)    (((F_CPU / 16) / baud) - 1)
-
-/** Macro for calculating the baud value from a given baud rate when the U2X (double speed) bit is
- *  set.
- */
-#define SERIAL_2X_UBBRVAL(baud) (((F_CPU / 8) / baud) - 1)
-
-#define SerEOL0()	{ Serial_TxByte0('\r'); Serial_TxByte0('\n'); } 
-
-#ifdef NOUSART1
-#undef UCSR1A
-#endif
-
-void USART_Init0(const uint32_t BaudRate);
-void Serial_TxByte0(const char DataByte);
-char Serial_RxByte0(void);
-uint8_t Serial_ByteRecieved0(void);
-
-void USART_Init1(const uint32_t BaudRate);
-void Serial_TxByte1(const char DataByte);
-char Serial_RxByte1(void);
-uint8_t Serial_ByteRecieved1(void);
-
-void Serial_Init(const uint32_t BaudRate0,
-				 const uint32_t BaudRate1);
-
-void cls(uint8_t	Port);
-
-void HexDump(const uint8_t 	*Buff, 
-				   uint16_t Length,
-				   uint8_t	Port);
-void HexDumpHead(const uint8_t 	*Buff, 
-				       uint16_t Length,
-				       uint8_t	Port);
-
-#endif
+/*
+	Status.h
+
+	Functions for logging program status to the serial port, to
+	be used for debugging pruposes etc.
+
+	2008-03-21, P.Harvey-Smith.
+
+	Some functions and macros borrowed from Dean Camera's LURFA
+	USB libraries.
+
+*/
+
+#include <avr/io.h>
+#include <avr/pgmspace.h>
+#include <stdbool.h>
+#include <stdio.h>
+
+
+#ifndef __STATUS_DEFINES__
+#define __STATUS_DEFINES__
+
+
+
+/********************************************************
+ * Simple string logger, as log0 is expensive
+ ********************************************************/
+
+#define logstr(s) logpgmstr(PSTR((s)))
+
+void logc(char c);
+void logs(const char *s);
+void logpgmstr(const char *s);
+void loghex1(uint8_t i);
+void loghex2(uint8_t i);
+void loghex4(uint16_t i);
+void logint(int i);
+void loglong(long i);
+char *strfill(char *buffer, char c, uint8_t i);
+char *strhex1(char *buffer, uint8_t i);
+char *strhex2(char *buffer, uint8_t i);
+char *strhex4(char *buffer, uint16_t i);
+char *strint(char *buffer, int i);
+char *strlong(char *buffer, long i);
+char *strinsert(char *buffer, const char *s);
+
+char *parselong(char *params,     long *val);
+char *parsehex2required(char *params,  uint8_t *val);
+char *parsehex4required(char *params, uint16_t *val);
+char *parsehex2(char *params,  uint8_t *val);
+char *parsehex4(char *params, uint16_t *val);
+
+#define log0(format,...) fprintf_P(&ser0stream,PSTR(format),##__VA_ARGS__)
+
+//
+// For stdio
+//
+
+extern FILE ser0stream;
+
+/* Default baud rate if 0 passed to Serial_Init */
+
+#define DefaultBaudRate	9600
+
+/** Indicates whether a character has been received through the USART - boolean false if no character
+ *  has been received, or non-zero if a character is waiting to be read from the reception buffer.
+ */
+#define Serial_IsCharReceived() ((UCSR1A & (1 << RXC1)) ? true : false)
+
+/** Macro for calculating the baud value from a given baud rate when the U2X (double speed) bit is
+ *  not set.
+ */
+#define SERIAL_UBBRVAL(baud)    (((F_CPU / 16) / baud) - 1)
+
+/** Macro for calculating the baud value from a given baud rate when the U2X (double speed) bit is
+ *  set.
+ */
+#define SERIAL_2X_UBBRVAL(baud) (((F_CPU / 8) / baud) - 1)
+
+#define SerEOL0()	{ Serial_TxByte0('\r'); Serial_TxByte0('\n'); }
+
+#ifdef NOUSART1
+#undef UCSR1A
+#endif
+
+void USART_Init0(const uint32_t BaudRate);
+void Serial_TxByte0(const char DataByte);
+char Serial_RxByte0(void);
+uint8_t Serial_ByteRecieved0(void);
+
+void Serial_Init(const uint32_t BaudRate0);
+
+void cls();
+
+#endif

firmware/terminalcodes.h

@@ -1,176 +1,176 @@
-/*
-             LUFA Library
-     Copyright (C) Dean Camera, 2008.
-              
-  dean [at] fourwalledcubicle [dot] com
-      www.fourwalledcubicle.com
-*/
-
-/*
-  Copyright 2008  Dean Camera (dean [at] fourwalledcubicle [dot] com)
-
-  Permission to use, copy, modify, and distribute this software
-  and its documentation for any purpose and without fee is hereby
-  granted, provided that the above copyright notice appear in all
-  copies and that both that the copyright notice and this
-  permission notice and warranty disclaimer appear in supporting
-  documentation, and that the name of the author not be used in
-  advertising or publicity pertaining to distribution of the
-  software without specific, written prior permission.
-
-  The author disclaim all warranties with regard to this
-  software, including all implied warranties of merchantability
-  and fitness.  In no event shall the author be liable for any
-  special, indirect or consequential damages or any damages
-  whatsoever resulting from loss of use, data or profits, whether
-  in an action of contract, negligence or other tortious action,
-  arising out of or in connection with the use or performance of
-  this software.
-*/
-
-/** \file
- *
- *  ANSI terminal compatible escape sequences. These escape sequences are designed to be concatenated with existing
- *  strings to modify their display on a compatible terminal application.
- *
- *  \note If desired, the macro DISABLE_TERMINAL_CODES can be defined in the project makefile and passed to the GCC
- *        compiler via the -D switch to disable the terminal codes without modifying the source, for use with non
- *        compatible terminals (any terminal code then equate to empty strings).
- *
- *  Example Usage:
- *  \code
- *      printf("Some String, " ESC_BOLD_ON " Some bold string");
- *  \endcode
- */
- 
-#ifndef __TERMINALCODES_H__
-#define __TERMINALCODES_H__
-
-	/* Public Interface - May be used in end-application: */
-		/* Macros: */
-			#if !defined(DISABLE_TERMINAL_CODES)
-				/** Creates an ANSII escape sequence with the payload specified by "c". */
-				#define ANSI_ESCAPE_SEQUENCE(c)  "\33[" c
-			#else
-				#define ANSI_ESCAPE_SEQUENCE(c)
-			#endif
-
-			/** Resets any escape sequence modifiers back to their defaults. */
-			#define ESC_RESET                ANSI_ESCAPE_SEQUENCE("0m")
-
-			/** Turns on bold so that any following text is printed to the terminal in bold. */
-			#define ESC_BOLD_ON              ANSI_ESCAPE_SEQUENCE("1m")
-
-			/** Turns on italics so that any following text is printed to the terminal in italics. */
-			#define ESC_ITALICS_ON           ANSI_ESCAPE_SEQUENCE("3m")
-
-			/** Turns on underline so that any following text is printed to the terminal underlined. */
-			#define ESC_UNDERLINE_ON         ANSI_ESCAPE_SEQUENCE("4m")
-
-			/** Turns on inverse so that any following text is printed to the terminal in inverted colours. */
-			#define ESC_INVERSE_ON           ANSI_ESCAPE_SEQUENCE("7m")
-
-			/** Turns on strikethrough so that any following text is printed to the terminal with a line through the
-			 *  center.
-			 */
-			#define ESC_STRIKETHROUGH_ON     ANSI_ESCAPE_SEQUENCE("9m")
-
-			/** Turns off bold so that any following text is printed to the terminal in non bold. */
-			#define ESC_BOLD_OFF             ANSI_ESCAPE_SEQUENCE("22m")
-
-			/** Turns off italics so that any following text is printed to the terminal in non italics. */
-			#define ESC_ITALICS_OFF          ANSI_ESCAPE_SEQUENCE("23m")
-			
-			/** Turns off underline so that any following text is printed to the terminal non underlined. */			
-			#define ESC_UNDERLINE_OFF        ANSI_ESCAPE_SEQUENCE("24m")
-
-			/** Turns off inverse so that any following text is printed to the terminal in non inverted colours. */
-			#define ESC_INVERSE_OFF          ANSI_ESCAPE_SEQUENCE("27m")
-
-			/** Turns off strikethrough so that any following text is printed to the terminal without a line through
-			 *  the center.
-			 */
-			#define ESC_STRIKETHROUGH_OFF    ANSI_ESCAPE_SEQUENCE("29m")
-
-			/** Sets the foreground (text) colour to black. */
-			#define ESC_FG_BLACK             ANSI_ESCAPE_SEQUENCE("30m")
-
-			/** Sets the foreground (text) colour to red. */
-			#define ESC_FG_RED               ANSI_ESCAPE_SEQUENCE("31m")
-
-			/** Sets the foreground (text) colour to green. */
-			#define ESC_FG_GREEN             ANSI_ESCAPE_SEQUENCE("32m")
-
-			/** Sets the foreground (text) colour to yellow. */
-			#define ESC_FG_YELLOW            ANSI_ESCAPE_SEQUENCE("33m")
-
-			/** Sets the foreground (text) colour to blue. */
-			#define ESC_FG_BLUE              ANSI_ESCAPE_SEQUENCE("34m")
-
-			/** Sets the foreground (text) colour to magenta. */
-			#define ESC_FG_MAGENTA           ANSI_ESCAPE_SEQUENCE("35m")
-
-			/** Sets the foreground (text) colour to cyan. */
-			#define ESC_FG_CYAN              ANSI_ESCAPE_SEQUENCE("36m")
-
-			/** Sets the foreground (text) colour to white. */
-			#define ESC_FG_WHITE             ANSI_ESCAPE_SEQUENCE("37m")
-
-			/** Sets the foreground (text) colour to the terminal's default. */
-			#define ESC_FG_DEFAULT           ANSI_ESCAPE_SEQUENCE("39m")
-
-			/** Sets the text background colour to black. */
-			#define ESC_BG_BLACK             ANSI_ESCAPE_SEQUENCE("40m")
-
-			/** Sets the text background colour to red. */
-			#define ESC_BG_RED               ANSI_ESCAPE_SEQUENCE("41m")
-
-			/** Sets the text background colour to green. */
-			#define ESC_BG_GREEN             ANSI_ESCAPE_SEQUENCE("42m")
-
-			/** Sets the text background colour to yellow. */
-			#define ESC_BG_YELLOW            ANSI_ESCAPE_SEQUENCE("43m")
-
-			/** Sets the text background colour to blue. */
-			#define ESC_BG_BLUE              ANSI_ESCAPE_SEQUENCE("44m")
-
-			/** Sets the text background colour to magenta. */
-			#define ESC_BG_MAGENTA           ANSI_ESCAPE_SEQUENCE("45m")
-
-			/** Sets the text background colour to cyan. */
-			#define ESC_BG_CYAN              ANSI_ESCAPE_SEQUENCE("46m")
-
-			/** Sets the text background colour to white. */
-			#define ESC_BG_WHITE             ANSI_ESCAPE_SEQUENCE("47m")
-
-			/** Sets the text background colour to the terminal's default. */
-			#define ESC_BG_DEFAULT           ANSI_ESCAPE_SEQUENCE("49m")
-			
-			/** Sets the cursor position to the given line and column. */
-			#define ESC_CURSOR_POS(L, C)     ANSI_ESCAPE_SEQUENCE(#L ";" #C "H")
-
-			/** Moves the cursor up the given number of lines. */
-			#define ESC_CURSOR_UP(L)         ANSI_ESCAPE_SEQUENCE(#L "A")
-
-			/** Moves the cursor down the given number of lines. */
-			#define ESC_CURSOR_DOWN(L)       ANSI_ESCAPE_SEQUENCE(#L "B")
-
-			/** Moves the cursor to the right the given number of columns. */
-			#define ESC_CURSOR_FORWARD(C)    ANSI_ESCAPE_SEQUENCE(#C "C")
-
-			/** Moves the cursor to the left the given number of columns. */
-			#define ESC_CURSOR_BACKWARD(C)   ANSI_ESCAPE_SEQUENCE(#C "D")
-
-			/** Saves the current cursor position so that it may be restored with ESC_CURSOR_POS_RESTORE. */
-			#define ESC_CURSOR_POS_SAVE      ANSI_ESCAPE_SEQUENCE("s")
-
-			/** Restores the cursor position to the last position saved with ESC_CURSOR_POS_SAVE. */
-			#define ESC_CURSOR_POS_RESTORE   ANSI_ESCAPE_SEQUENCE("u")
-			
-			/** Erases the entire display, returning the cursor to the top left. */
-			#define ESC_ERASE_DISPLAY        ANSI_ESCAPE_SEQUENCE("2J")
-
-			/** Erases the current line, returning the cursor to the far left. */
-			#define ESC_ERASE_LINE           ANSI_ESCAPE_SEQUENCE("K")
-
-#endif
+/*
+             LUFA Library
+     Copyright (C) Dean Camera, 2008.
+              
+  dean [at] fourwalledcubicle [dot] com
+      www.fourwalledcubicle.com
+*/
+
+/*
+  Copyright 2008  Dean Camera (dean [at] fourwalledcubicle [dot] com)
+
+  Permission to use, copy, modify, and distribute this software
+  and its documentation for any purpose and without fee is hereby
+  granted, provided that the above copyright notice appear in all
+  copies and that both that the copyright notice and this
+  permission notice and warranty disclaimer appear in supporting
+  documentation, and that the name of the author not be used in
+  advertising or publicity pertaining to distribution of the
+  software without specific, written prior permission.
+
+  The author disclaim all warranties with regard to this
+  software, including all implied warranties of merchantability
+  and fitness.  In no event shall the author be liable for any
+  special, indirect or consequential damages or any damages
+  whatsoever resulting from loss of use, data or profits, whether
+  in an action of contract, negligence or other tortious action,
+  arising out of or in connection with the use or performance of
+  this software.
+*/
+
+/** \file
+ *
+ *  ANSI terminal compatible escape sequences. These escape sequences are designed to be concatenated with existing
+ *  strings to modify their display on a compatible terminal application.
+ *
+ *  \note If desired, the macro DISABLE_TERMINAL_CODES can be defined in the project makefile and passed to the GCC
+ *        compiler via the -D switch to disable the terminal codes without modifying the source, for use with non
+ *        compatible terminals (any terminal code then equate to empty strings).
+ *
+ *  Example Usage:
+ *  \code
+ *      printf("Some String, " ESC_BOLD_ON " Some bold string");
+ *  \endcode
+ */
+ 
+#ifndef __TERMINALCODES_H__
+#define __TERMINALCODES_H__
+
+	/* Public Interface - May be used in end-application: */
+		/* Macros: */
+			#if !defined(DISABLE_TERMINAL_CODES)
+				/** Creates an ANSII escape sequence with the payload specified by "c". */
+				#define ANSI_ESCAPE_SEQUENCE(c)  "\33[" c
+			#else
+				#define ANSI_ESCAPE_SEQUENCE(c)
+			#endif
+
+			/** Resets any escape sequence modifiers back to their defaults. */
+			#define ESC_RESET                ANSI_ESCAPE_SEQUENCE("0m")
+
+			/** Turns on bold so that any following text is printed to the terminal in bold. */
+			#define ESC_BOLD_ON              ANSI_ESCAPE_SEQUENCE("1m")
+
+			/** Turns on italics so that any following text is printed to the terminal in italics. */
+			#define ESC_ITALICS_ON           ANSI_ESCAPE_SEQUENCE("3m")
+
+			/** Turns on underline so that any following text is printed to the terminal underlined. */
+			#define ESC_UNDERLINE_ON         ANSI_ESCAPE_SEQUENCE("4m")
+
+			/** Turns on inverse so that any following text is printed to the terminal in inverted colours. */
+			#define ESC_INVERSE_ON           ANSI_ESCAPE_SEQUENCE("7m")
+
+			/** Turns on strikethrough so that any following text is printed to the terminal with a line through the
+			 *  center.
+			 */
+			#define ESC_STRIKETHROUGH_ON     ANSI_ESCAPE_SEQUENCE("9m")
+
+			/** Turns off bold so that any following text is printed to the terminal in non bold. */
+			#define ESC_BOLD_OFF             ANSI_ESCAPE_SEQUENCE("22m")
+
+			/** Turns off italics so that any following text is printed to the terminal in non italics. */
+			#define ESC_ITALICS_OFF          ANSI_ESCAPE_SEQUENCE("23m")
+			
+			/** Turns off underline so that any following text is printed to the terminal non underlined. */			
+			#define ESC_UNDERLINE_OFF        ANSI_ESCAPE_SEQUENCE("24m")
+
+			/** Turns off inverse so that any following text is printed to the terminal in non inverted colours. */
+			#define ESC_INVERSE_OFF          ANSI_ESCAPE_SEQUENCE("27m")
+
+			/** Turns off strikethrough so that any following text is printed to the terminal without a line through
+			 *  the center.
+			 */
+			#define ESC_STRIKETHROUGH_OFF    ANSI_ESCAPE_SEQUENCE("29m")
+
+			/** Sets the foreground (text) colour to black. */
+			#define ESC_FG_BLACK             ANSI_ESCAPE_SEQUENCE("30m")
+
+			/** Sets the foreground (text) colour to red. */
+			#define ESC_FG_RED               ANSI_ESCAPE_SEQUENCE("31m")
+
+			/** Sets the foreground (text) colour to green. */
+			#define ESC_FG_GREEN             ANSI_ESCAPE_SEQUENCE("32m")
+
+			/** Sets the foreground (text) colour to yellow. */
+			#define ESC_FG_YELLOW            ANSI_ESCAPE_SEQUENCE("33m")
+
+			/** Sets the foreground (text) colour to blue. */
+			#define ESC_FG_BLUE              ANSI_ESCAPE_SEQUENCE("34m")
+
+			/** Sets the foreground (text) colour to magenta. */
+			#define ESC_FG_MAGENTA           ANSI_ESCAPE_SEQUENCE("35m")
+
+			/** Sets the foreground (text) colour to cyan. */
+			#define ESC_FG_CYAN              ANSI_ESCAPE_SEQUENCE("36m")
+
+			/** Sets the foreground (text) colour to white. */
+			#define ESC_FG_WHITE             ANSI_ESCAPE_SEQUENCE("37m")
+
+			/** Sets the foreground (text) colour to the terminal's default. */
+			#define ESC_FG_DEFAULT           ANSI_ESCAPE_SEQUENCE("39m")
+
+			/** Sets the text background colour to black. */
+			#define ESC_BG_BLACK             ANSI_ESCAPE_SEQUENCE("40m")
+
+			/** Sets the text background colour to red. */
+			#define ESC_BG_RED               ANSI_ESCAPE_SEQUENCE("41m")
+
+			/** Sets the text background colour to green. */
+			#define ESC_BG_GREEN             ANSI_ESCAPE_SEQUENCE("42m")
+
+			/** Sets the text background colour to yellow. */
+			#define ESC_BG_YELLOW            ANSI_ESCAPE_SEQUENCE("43m")
+
+			/** Sets the text background colour to blue. */
+			#define ESC_BG_BLUE              ANSI_ESCAPE_SEQUENCE("44m")
+
+			/** Sets the text background colour to magenta. */
+			#define ESC_BG_MAGENTA           ANSI_ESCAPE_SEQUENCE("45m")
+
+			/** Sets the text background colour to cyan. */
+			#define ESC_BG_CYAN              ANSI_ESCAPE_SEQUENCE("46m")
+
+			/** Sets the text background colour to white. */
+			#define ESC_BG_WHITE             ANSI_ESCAPE_SEQUENCE("47m")
+
+			/** Sets the text background colour to the terminal's default. */
+			#define ESC_BG_DEFAULT           ANSI_ESCAPE_SEQUENCE("49m")
+			
+			/** Sets the cursor position to the given line and column. */
+			#define ESC_CURSOR_POS(L, C)     ANSI_ESCAPE_SEQUENCE(#L ";" #C "H")
+
+			/** Moves the cursor up the given number of lines. */
+			#define ESC_CURSOR_UP(L)         ANSI_ESCAPE_SEQUENCE(#L "A")
+
+			/** Moves the cursor down the given number of lines. */
+			#define ESC_CURSOR_DOWN(L)       ANSI_ESCAPE_SEQUENCE(#L "B")
+
+			/** Moves the cursor to the right the given number of columns. */
+			#define ESC_CURSOR_FORWARD(C)    ANSI_ESCAPE_SEQUENCE(#C "C")
+
+			/** Moves the cursor to the left the given number of columns. */
+			#define ESC_CURSOR_BACKWARD(C)   ANSI_ESCAPE_SEQUENCE(#C "D")
+
+			/** Saves the current cursor position so that it may be restored with ESC_CURSOR_POS_RESTORE. */
+			#define ESC_CURSOR_POS_SAVE      ANSI_ESCAPE_SEQUENCE("s")
+
+			/** Restores the cursor position to the last position saved with ESC_CURSOR_POS_SAVE. */
+			#define ESC_CURSOR_POS_RESTORE   ANSI_ESCAPE_SEQUENCE("u")
+			
+			/** Erases the entire display, returning the cursor to the top left. */
+			#define ESC_ERASE_DISPLAY        ANSI_ESCAPE_SEQUENCE("2J")
+
+			/** Erases the current line, returning the cursor to the far left. */
+			#define ESC_ERASE_LINE           ANSI_ESCAPE_SEQUENCE("K")
+
+#endif

kicad/6502/v1/6502_adapter.sch

@@ -1,5 +1,4 @@
 EESchema Schematic File Version 4
-LIBS:6502_adapter-cache
 EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
@@ -199,32 +198,30 @@ Text Label 7300 1300 0    60   ~ 0
 3V3
 Text Label 7300 2300 0    60   ~ 0
 GND
-Text Label 2600 1300 0    60   ~ 0
+Text Label 2500 1300 0    60   ~ 0
 nVP
-Text Label 2600 1400 0    60   ~ 0
+Text Label 2500 1400 0    60   ~ 0
 PHI2OUT
-Text Label 2600 1500 0    60   ~ 0
+Text Label 2500 1500 0    60   ~ 0
 PHI1OUT
-Text Label 2600 1600 0    60   ~ 0
+Text Label 2500 1600 0    60   ~ 0
 nML
 Text Label 10250 5950 0    60   ~ 0
 RnW
-Text Label 2600 1800 0    60   ~ 0
+Text Label 2500 1800 0    60   ~ 0
 SYNC
-Text Label 5800 1500 2    60   ~ 0
+Text Label 5900 1500 2    60   ~ 0
 nRST
-Text Label 5800 1600 2    60   ~ 0
+Text Label 5900 1600 2    60   ~ 0
 RDY
-Text Label 5800 1800 2    60   ~ 0
+Text Label 5900 1800 2    60   ~ 0
 nIRQ
-Text Label 4350 1100 2    60   ~ 0
-PHI2
-Text Label 5800 2000 2    60   ~ 0
+Text Label 5900 2000 2    60   ~ 0
 BE
-Text Label 5800 2100 2    60   ~ 0
+Text Label 5900 2100 2    60   ~ 0
 nNMI
 NoConn ~ 4950 3000
-Text Label 3850 1050 0    60   ~ 0
+Text Label 3400 1050 0    60   ~ 0
 GND
 Text Label 1050 3200 2    60   ~ 0
 LV_A0
@@ -614,10 +611,6 @@ Wire Wire Line
 	3450 2700 3450 1500
 Wire Wire Line
 	3450 1500 2500 1500
-Wire Wire Line
-	3650 3100 2750 3100
-Wire Wire Line
-	4950 2500 5400 2500
 Wire Wire Line
 	3650 2600 3550 2600
 Wire Wire Line
@@ -625,11 +618,7 @@ Wire Wire Line
 Wire Wire Line
 	3350 2800 3350 1800
 Wire Wire Line
-	3350 1800 5900 1800
-Wire Wire Line
-	4950 2800 5200 2800
-Wire Wire Line
-	5200 2800 5200 1900
+	3350 1800 4500 1800
 Wire Wire Line
 	4950 2900 5500 2900
 Wire Wire Line
@@ -643,13 +632,13 @@ Wire Wire Line
 Wire Wire Line
 	2750 1800 2500 1800
 Wire Wire Line
-	3550 1300 3550 1050
+	3100 1300 3100 1050
 Wire Wire Line
-	3650 1050 3650 2500
+	3200 1050 3200 1300
 Wire Wire Line
-	3750 1050 3850 1050
+	3300 1050 3400 1050
 Wire Wire Line
-	2500 1300 3550 1300
+	2500 1300 3100 1300
 Wire Wire Line
 	3250 1600 2500 1600
 Wire Wire Line
@@ -783,8 +772,8 @@ L Device:D_Schottky D4
 U 1 1 5D7BB685
 P 9600 1700
 F 0 "D4" H 9600 1600 50  0000 C CNN
-F 1 "MBR130" H 9600 1800 50  0000 C CNN
-F 2 "Diode_SMD:D_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 9600 1700 50  0001 C CNN
+F 1 "PMEG3010BEA" H 9600 1800 50  0000 C CNN
+F 2 "Diode_SMD:D_SOD-323_HandSoldering" H 9600 1700 50  0001 C CNN
 F 3 "~" H 9600 1700 50  0001 C CNN
 	1    9600 1700
 	-1   0    0    1   
@@ -798,8 +787,8 @@ L Device:D_Schottky D5
 U 1 1 5D7DCB4D
 P 8050 1700
 F 0 "D5" H 8050 1600 50  0000 C CNN
-F 1 "MBR130" H 8050 1800 50  0000 C CNN
-F 2 "Diode_SMD:D_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 8050 1700 50  0001 C CNN
+F 1 "PMEG3010BEA" H 8050 1800 50  0000 C CNN
+F 2 "Diode_SMD:D_SOD-323_HandSoldering" H 8050 1700 50  0001 C CNN
 F 3 "~" H 8050 1700 50  0001 C CNN
 	1    8050 1700
 	-1   0    0    1   
@@ -888,8 +877,6 @@ Wire Wire Line
 Connection ~ 6700 4950
 Wire Wire Line
 	6700 4850 6700 4950
-Wire Wire Line
-	2750 3100 2750 1800
 Wire Wire Line
 	3250 1600 3250 2600
 Text Label 9250 5750 2    60   ~ 0
@@ -1012,10 +999,6 @@ F 3 "" H 6700 4750 50  0000 C CNN
 $EndComp
 Wire Wire Line
 	6700 4650 6700 4550
-Wire Wire Line
-	3750 1400 3750 2350
-Wire Wire Line
-	3750 1400 2500 1400
 Wire Wire Line
 	8800 4350 8800 4950
 Wire Wire Line
@@ -1033,7 +1016,7 @@ GND
 Text Label 7300 1800 0    60   ~ 0
 LV_nSO
 Connection ~ 3650 7200
-Text Label 5800 1700 2    60   ~ 0
+Text Label 5900 1700 2    60   ~ 0
 nSO
 $Comp
 L Device:R_Small R7
@@ -1182,11 +1165,7 @@ Wire Wire Line
 Wire Wire Line
 	9050 4600 9050 4850
 Wire Wire Line
-	5900 1500 5400 1500
-Wire Wire Line
-	5400 1500 5400 2500
-Wire Wire Line
-	5900 1600 3550 1600
+	5900 1600 4750 1600
 Wire Wire Line
 	3550 1600 3550 2600
 NoConn ~ 5900 1400
@@ -1244,12 +1223,12 @@ $EndComp
 $Comp
 L Connector_Generic:Conn_01x03 LK1
 U 1 1 5D79BE74
-P 3650 850
-F 0 "LK1" V 3850 900 50  0000 R CNN
-F 1 "Conn_01x03" V 3750 1100 50  0000 R CNN
-F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Horizontal" H 3650 850 50  0001 C CNN
-F 3 "~" H 3650 850 50  0001 C CNN
-	1    3650 850 
+P 3200 850
+F 0 "LK1" V 3400 900 50  0000 R CNN
+F 1 "Conn_01x03" V 3300 1100 50  0000 R CNN
+F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Horizontal" H 3200 850 50  0001 C CNN
+F 3 "~" H 3200 850 50  0001 C CNN
+	1    3200 850 
 	0    1    -1   0   
 $EndComp
 $Comp
@@ -1307,10 +1286,8 @@ Text Label 10550 1600 0    60   ~ 0
 LV_RnW2
 Wire Wire Line
 	2500 1700 2900 1700
-Text Label 2600 1700 0    60   ~ 0
+Text Label 2500 1700 0    60   ~ 0
 RnW2
-Wire Wire Line
-	3750 2350 5000 2350
 Wire Wire Line
 	4950 2600 5000 2600
 Wire Wire Line
@@ -1320,20 +1297,6 @@ Wire Wire Line
 	4950 3100 5100 3100
 Wire Wire Line
 	5100 3100 5100 2150
-Wire Wire Line
-	5600 2100 5900 2100
-Wire Wire Line
-	2850 2250 5600 2250
-Wire Wire Line
-	5600 2250 5600 2100
-Wire Wire Line
-	4950 2700 5300 2700
-Wire Wire Line
-	5900 1700 5300 1700
-Wire Wire Line
-	5300 1700 5300 2700
-Text Label 4900 2150 0    60   ~ 0
-RnW
 Text Notes 8600 3850 0    118  ~ 0
 Optional Components
 Wire Wire Line
@@ -1383,23 +1346,8 @@ Wire Wire Line
 Connection ~ 10700 4500
 Wire Wire Line
 	10700 4500 10850 4500
-$Comp
-L Jumper:Jumper_2_Open JP1
-U 1 1 5D981286
-P 4200 2150
-F 0 "JP1" H 4200 2385 50  0000 C CNN
-F 1 "Jumper_2_Open" H 4200 2294 50  0000 C CNN
-F 2 "Jumper:SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm" H 4200 2150 50  0001 C CNN
-F 3 "~" H 4200 2150 50  0001 C CNN
-	1    4200 2150
-	1    0    0    -1  
-$EndComp
 Wire Wire Line
-	2900 2150 4000 2150
-Wire Wire Line
-	2900 1700 2900 2150
-Wire Wire Line
-	4400 2150 5100 2150
+	2900 2150 5100 2150
 Wire Wire Line
 	10250 5950 10250 6350
 Wire Wire Line
@@ -1504,47 +1452,203 @@ ID1
 Text Label 8500 2500 2    60   ~ 0
 ID3
 NoConn ~ 9650 3250
-$Comp
-L Device:R_Small R14
-U 1 1 5D90172A
-P 4550 1100
-F 0 "R14" V 4450 1050 50  0000 L TNN
-F 1 "0" V 4550 1100 50  0000 C CNN
-F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4550 1100 50  0001 C CNN
-F 3 "" H 4550 1100 50  0000 C CNN
-	1    4550 1100
-	0    1    1    0   
-$EndComp
-$Comp
-L Device:C_Small C15
-U 1 1 5D902442
-P 4750 1300
-F 0 "C15" H 4760 1370 50  0000 L CNN
-F 1 "0" H 4760 1220 50  0000 L CNN
-F 2 "Capacitor_SMD:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4750 1300 50  0001 C CNN
-F 3 "" H 4750 1300 50  0000 C CNN
-	1    4750 1300
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4450 1100 4350 1100
-Wire Wire Line
-	4350 1100 4350 1900
-Wire Wire Line
-	4350 1900 5200 1900
-Text Label 4750 1400 3    60   ~ 0
-GND
-Wire Wire Line
-	4650 1100 4750 1100
-Wire Wire Line
-	4750 1100 4750 1200
 Wire Wire Line
 	5900 1900 5600 1900
 Wire Wire Line
-	5600 1900 5600 1100
+	3200 1300 3650 1300
 Wire Wire Line
-	5600 1100 4750 1100
-Connection ~ 4750 1100
-Text Label 5450 1100 2    60   ~ 0
+	3650 1300 3650 2500
+Text Label 5600 2550 0    60   ~ 0
 FILTERED_PHI2
+Text Label 6200 2700 0    60   ~ 0
+GND
+$Comp
+L Device:R_Small R14
+U 1 1 5D90172A
+P 5750 2700
+F 0 "R14" V 5850 2650 50  0000 L TNN
+F 1 "0" V 5750 2700 50  0000 C CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 5750 2700 50  0001 C CNN
+F 3 "" H 5750 2700 50  0000 C CNN
+	1    5750 2700
+	0    1    1    0   
+$EndComp
+$Comp
+L Device:R_Small R18
+U 1 1 5DB24834
+P 4750 800
+F 0 "R18" H 4780 820 50  0000 L CNN
+F 1 "22K" H 4780 760 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4750 800 50  0001 C CNN
+F 3 "" H 4750 800 50  0000 C CNN
+	1    4750 800 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5500 600  5250 600 
+Wire Wire Line
+	5250 600  5250 700 
+Connection ~ 5500 600 
+Wire Wire Line
+	4750 900  4750 1600
+Connection ~ 4750 1600
+Wire Wire Line
+	4750 1600 3550 1600
+$Comp
+L Device:R_Small R19
+U 1 1 5DB400D0
+P 4500 800
+F 0 "R19" H 4530 820 50  0000 L CNN
+F 1 "22K" H 4530 760 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4500 800 50  0001 C CNN
+F 3 "" H 4500 800 50  0000 C CNN
+	1    4500 800 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5250 600  5000 600 
+Connection ~ 5250 600 
+Wire Wire Line
+	5000 700  5000 600 
+Connection ~ 5000 600 
+Wire Wire Line
+	4500 900  4500 1800
+Connection ~ 4500 1800
+Wire Wire Line
+	4500 1800 5900 1800
+Wire Wire Line
+	5000 600  4750 600 
+Connection ~ 4250 2250
+Wire Wire Line
+	2850 2250 4250 2250
+Wire Wire Line
+	4750 600  4750 700 
+$Comp
+L Device:R_Small R20
+U 1 1 5DB3FF21
+P 4250 800
+F 0 "R20" H 4280 820 50  0000 L CNN
+F 1 "22K" H 4280 760 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4250 800 50  0001 C CNN
+F 3 "" H 4250 800 50  0000 C CNN
+	1    4250 800 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5850 2700 5950 2700
+Wire Wire Line
+	5600 1900 5600 2550
+Wire Wire Line
+	5600 2550 5950 2550
+Wire Wire Line
+	5950 2550 5950 2700
+Connection ~ 5950 2700
+Wire Wire Line
+	5950 2700 6000 2700
+$Comp
+L Device:C_Small C15
+U 1 1 5D902442
+P 6100 2700
+F 0 "C15" V 5950 2650 50  0000 L CNN
+F 1 "0" V 6000 2600 50  0000 L CNN
+F 2 "Capacitor_SMD:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 6100 2700 50  0001 C CNN
+F 3 "" H 6100 2700 50  0000 C CNN
+	1    6100 2700
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:R_Small R16
+U 1 1 5DC52DDE
+P 5000 800
+F 0 "R16" H 5030 820 50  0000 L CNN
+F 1 "22K" H 5030 760 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 5000 800 50  0001 C CNN
+F 3 "" H 5000 800 50  0000 C CNN
+	1    5000 800 
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R_Small R17
+U 1 1 5DC531BF
+P 5250 800
+F 0 "R17" H 5280 820 50  0000 L CNN
+F 1 "22K" H 5280 760 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 5250 800 50  0001 C CNN
+F 3 "" H 5250 800 50  0000 C CNN
+	1    5250 800 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4250 700  4250 600 
+Wire Wire Line
+	4250 600  4500 600 
+Connection ~ 4750 600 
+Wire Wire Line
+	4500 700  4500 600 
+Connection ~ 4500 600 
+Wire Wire Line
+	4500 600  4750 600 
+Wire Wire Line
+	3750 2350 5000 2350
+Wire Wire Line
+	3750 1400 2500 1400
+Wire Wire Line
+	3750 1400 3750 2350
+Wire Wire Line
+	2750 3100 3650 3100
+$Comp
+L Jumper:Jumper_2_Open JP1
+U 1 1 5D981286
+P 2900 1900
+F 0 "JP1" H 2900 2135 50  0000 C CNN
+F 1 "Jumper_2_Open" H 2900 2044 50  0000 C CNN
+F 2 "Jumper:SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm" H 2900 1900 50  0001 C CNN
+F 3 "~" H 2900 1900 50  0001 C CNN
+	1    2900 1900
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	2750 1800 2750 3100
+Wire Wire Line
+	2900 2100 2900 2150
+Wire Wire Line
+	5000 900  5000 1700
+Wire Wire Line
+	4250 900  4250 2250
+Wire Wire Line
+	5200 2100 5900 2100
+Wire Wire Line
+	4250 2250 5200 2250
+Wire Wire Line
+	5200 2250 5200 2100
+Wire Wire Line
+	4950 2700 5300 2700
+Connection ~ 5300 1700
+Wire Wire Line
+	5000 1700 5300 1700
+Wire Wire Line
+	5900 1700 5300 1700
+Wire Wire Line
+	5300 1700 5300 2700
+Wire Wire Line
+	5400 2700 5650 2700
+Wire Wire Line
+	4950 2800 5400 2800
+Text Label 5400 2800 2    60   ~ 0
+PHI2
+Wire Wire Line
+	5400 2800 5400 2700
+Text Label 4900 2150 0    60   ~ 0
+RnW
+Wire Wire Line
+	4950 2500 5400 2500
+Wire Wire Line
+	5900 1500 5400 1500
+Wire Wire Line
+	5400 1500 5400 2500
+Wire Wire Line
+	5250 900  5250 1500
+Wire Wire Line
+	5250 1500 5400 1500
+Connection ~ 5400 1500
 $EndSCHEMATC

kicad/6502/v1/manufacturing/6502_adapter.gko

@@ -1,11 +1,11 @@
 G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.1.4-e60b266~84~ubuntu18.04.1*
-G04 #@! TF.CreationDate,2019-09-22T15:45:03+01:00*
+G04 #@! TF.CreationDate,2019-10-24T10:36:49+01:00*
 G04 #@! TF.ProjectId,6502_adapter,36353032-5f61-4646-9170-7465722e6b69,rev?*
 G04 #@! TF.SameCoordinates,PX9fdfbc0PY791ddc0*
 G04 #@! TF.FileFunction,Profile,NP*
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 5.1.4-e60b266~84~ubuntu18.04.1) date 2019-09-22 15:45:03*
+G04 Created by KiCad (PCBNEW 5.1.4-e60b266~84~ubuntu18.04.1) date 2019-10-24 10:36:49*
 %MOMM*%
 %LPD*%
 G04 APERTURE LIST*

kicad/6502/v1/manufacturing/6502_adapter.gto

@@ -1,12 +1,12 @@
 G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.1.4-e60b266~84~ubuntu18.04.1*
-G04 #@! TF.CreationDate,2019-09-22T15:45:03+01:00*
+G04 #@! TF.CreationDate,2019-10-24T10:36:49+01:00*
 G04 #@! TF.ProjectId,6502_adapter,36353032-5f61-4646-9170-7465722e6b69,rev?*
 G04 #@! TF.SameCoordinates,PX9fdfbc0PY791ddc0*
 G04 #@! TF.FileFunction,Legend,Top*
 G04 #@! TF.FilePolarity,Positive*
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 5.1.4-e60b266~84~ubuntu18.04.1) date 2019-09-22 15:45:03*
+G04 Created by KiCad (PCBNEW 5.1.4-e60b266~84~ubuntu18.04.1) date 2019-10-24 10:36:49*
 %MOMM*%
 %LPD*%
 G04 APERTURE LIST*
@@ -950,6 +950,18 @@ X37740000Y72540000D01*
 X28740000Y76540000D02*
 X37740000Y76540000D01*
 D12*
+X43810000Y27090000D02*
+X40660000Y27090000D01*
+X43810000Y28790000D02*
+X40660000Y28790000D01*
+X43810000Y27090000D02*
+X43810000Y28790000D01*
+X7108000Y45935000D02*
+X10258000Y45935000D01*
+X7108000Y44235000D02*
+X10258000Y44235000D01*
+X7108000Y45935000D02*
+X7108000Y44235000D01*
 X27253000Y53468748D02*
 X27253000Y53991252D01*
 X25833000Y53468748D02*
@@ -1182,22 +1194,6 @@ X42918748Y5155000D02*
 X43441252Y5155000D01*
 X42918748Y3735000D02*
 X43441252Y3735000D01*
-X27380000Y45458748D02*
-X27380000Y45981252D01*
-X25960000Y45458748D02*
-X25960000Y45981252D01*
-X43770000Y28900000D02*
-X40910000Y28900000D01*
-X43770000Y26980000D02*
-X43770000Y28900000D01*
-X40910000Y26980000D02*
-X43770000Y26980000D01*
-X7148000Y44125000D02*
-X10008000Y44125000D01*
-X7148000Y46045000D02*
-X7148000Y44125000D01*
-X10008000Y46045000D02*
-X7148000Y46045000D01*
 X24055000Y60586252D02*
 X24055000Y60063748D01*
 X25475000Y60586252D02*
@@ -1307,6 +1303,53 @@ X37530000Y62485000D02*
 X37530000Y62120000D01*
 X29780000Y62485000D02*
 X29780000Y62210000D01*
+X41171904Y29075120D02*
+X41171904Y30075120D01*
+X41410000Y30075120D01*
+X41552857Y30027500D01*
+X41648095Y29932262D01*
+X41695714Y29837024D01*
+X41743333Y29646548D01*
+X41743333Y29503691D01*
+X41695714Y29313215D01*
+X41648095Y29217977D01*
+X41552857Y29122739D01*
+X41410000Y29075120D01*
+X41171904Y29075120D01*
+X42648095Y30075120D02*
+X42171904Y30075120D01*
+X42124285Y29598929D01*
+X42171904Y29646548D01*
+X42267142Y29694167D01*
+X42505238Y29694167D01*
+X42600476Y29646548D01*
+X42648095Y29598929D01*
+X42695714Y29503691D01*
+X42695714Y29265596D01*
+X42648095Y29170358D01*
+X42600476Y29122739D01*
+X42505238Y29075120D01*
+X42267142Y29075120D01*
+X42171904Y29122739D01*
+X42124285Y29170358D01*
+X7770904Y42727620D02*
+X7770904Y43727620D01*
+X8009000Y43727620D01*
+X8151857Y43680000D01*
+X8247095Y43584762D01*
+X8294714Y43489524D01*
+X8342333Y43299048D01*
+X8342333Y43156191D01*
+X8294714Y42965715D01*
+X8247095Y42870477D01*
+X8151857Y42775239D01*
+X8009000Y42727620D01*
+X7770904Y42727620D01*
+X9199476Y43394286D02*
+X9199476Y42727620D01*
+X8961380Y43775239D02*
+X8723285Y43060953D01*
+X9342333Y43060953D01*
 X25519142Y55935620D02*
 X25185809Y56411810D01*
 X24947714Y55935620D02*
@@ -1983,89 +2026,6 @@ X47140714Y4706905D01*
 X47093095Y4564048D01*
 X46521666Y3992620D01*
 X47140714Y3992620D01*
-X28567142Y44759620D02*
-X28233809Y45235810D01*
-X27995714Y44759620D02*
-X27995714Y45759620D01*
-X28376666Y45759620D01*
-X28471904Y45712000D01*
-X28519523Y45664381D01*
-X28567142Y45569143D01*
-X28567142Y45426286D01*
-X28519523Y45331048D01*
-X28471904Y45283429D01*
-X28376666Y45235810D01*
-X27995714Y45235810D01*
-X29519523Y44759620D02*
-X28948095Y44759620D01*
-X29233809Y44759620D02*
-X29233809Y45759620D01*
-X29138571Y45616762D01*
-X29043333Y45521524D01*
-X28948095Y45473905D01*
-X30424285Y45759620D02*
-X29948095Y45759620D01*
-X29900476Y45283429D01*
-X29948095Y45331048D01*
-X30043333Y45378667D01*
-X30281428Y45378667D01*
-X30376666Y45331048D01*
-X30424285Y45283429D01*
-X30471904Y45188191D01*
-X30471904Y44950096D01*
-X30424285Y44854858D01*
-X30376666Y44807239D01*
-X30281428Y44759620D01*
-X30043333Y44759620D01*
-X29948095Y44807239D01*
-X29900476Y44854858D01*
-X41171904Y29265620D02*
-X41171904Y30265620D01*
-X41410000Y30265620D01*
-X41552857Y30218000D01*
-X41648095Y30122762D01*
-X41695714Y30027524D01*
-X41743333Y29837048D01*
-X41743333Y29694191D01*
-X41695714Y29503715D01*
-X41648095Y29408477D01*
-X41552857Y29313239D01*
-X41410000Y29265620D01*
-X41171904Y29265620D01*
-X42648095Y30265620D02*
-X42171904Y30265620D01*
-X42124285Y29789429D01*
-X42171904Y29837048D01*
-X42267142Y29884667D01*
-X42505238Y29884667D01*
-X42600476Y29837048D01*
-X42648095Y29789429D01*
-X42695714Y29694191D01*
-X42695714Y29456096D01*
-X42648095Y29360858D01*
-X42600476Y29313239D01*
-X42505238Y29265620D01*
-X42267142Y29265620D01*
-X42171904Y29313239D01*
-X42124285Y29360858D01*
-X7516904Y42473620D02*
-X7516904Y43473620D01*
-X7755000Y43473620D01*
-X7897857Y43426000D01*
-X7993095Y43330762D01*
-X8040714Y43235524D01*
-X8088333Y43045048D01*
-X8088333Y42902191D01*
-X8040714Y42711715D01*
-X7993095Y42616477D01*
-X7897857Y42521239D01*
-X7755000Y42473620D01*
-X7516904Y42473620D01*
-X8945476Y43140286D02*
-X8945476Y42473620D01*
-X8707380Y43521239D02*
-X8469285Y42806953D01*
-X9088333Y42806953D01*
 X24598333Y63047620D02*
 X24265000Y63523810D01*
 X24026904Y63047620D02*

kicad/6502/v1/manufacturing/6502_adapter.xln

@@ -1,7 +1,7 @@
 M48
-; DRILL file {KiCad 5.1.4-e60b266~84~ubuntu18.04.1} date Sun 22 Sep 2019 15:45:06 BST
+; DRILL file {KiCad 5.1.4-e60b266~84~ubuntu18.04.1} date Thu 24 Oct 2019 10:36:55 BST
 ; FORMAT={-:-/ absolute / inch / decimal}
-; #@! TF.CreationDate,2019-09-22T15:45:06+01:00
+; #@! TF.CreationDate,2019-10-24T10:36:55+01:00
 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.4-e60b266~84~ubuntu18.04.1
 FMAT,2
 INCH
@@ -62,15 +62,16 @@ X1.4751Y1.09
 T2
 X0.4Y2.01
 X0.4Y1.7
-X0.4Y1.04
+X0.4Y1.0525
+X0.4Y0.975
 X0.425Y2.425
-X0.425Y0.975
 X0.455Y0.37
 X0.5Y1.8
 X0.5Y1.75
 X0.68Y1.85
 X0.68Y1.75
 X0.68Y1.65
+X0.7Y2.25
 X0.72Y1.85
 X0.72Y1.75
 X0.72Y1.65
@@ -93,6 +94,7 @@ X1.075Y1.2
 X1.075Y1.15
 X1.28Y1.05
 X1.28Y0.95
+X1.3Y2.15
 X1.3Y0.4
 X1.32Y1.05
 X1.32Y0.95
@@ -102,8 +104,8 @@ X1.5Y1.02
 X1.5Y0.98
 X1.575Y1.875
 X1.575Y1.15
-X1.6Y2.26
 X1.6Y1.8
+X1.62Y2.26
 X1.69Y0.98
 X1.69Y0.9
 X1.69Y0.725
@@ -114,56 +116,15 @@ X1.79Y0.39
 T3
 X0.925Y2.925
 X1.025Y2.925
-X0.725Y2.925
-X0.825Y2.925
 X0.525Y2.925
 X0.625Y2.925
+X0.725Y2.925
+X0.825Y2.925
 T4
+X1.6478Y2.925
+X1.825Y2.925
 X0.1675Y2.925
 X0.3447Y2.925
-X0.1Y2.4
-X0.1Y2.3
-X0.1Y2.2
-X0.1Y2.1
-X0.1Y2.0
-X0.1Y1.9
-X0.1Y1.8
-X0.1Y1.7
-X0.1Y1.6
-X0.1Y1.5
-X0.1Y1.4
-X0.1Y1.3
-X0.1Y1.2
-X0.1Y1.1
-X0.1Y1.0
-X0.1Y0.9
-X0.1Y0.8
-X0.1Y0.7
-X0.1Y0.6
-X0.1Y0.5
-X0.2Y2.4
-X0.2Y2.3
-X0.2Y2.2
-X0.2Y2.1
-X0.2Y2.0
-X0.2Y1.9
-X0.2Y1.8
-X0.2Y1.7
-X0.2Y1.6
-X0.2Y1.5
-X0.2Y1.4
-X0.2Y1.3
-X0.2Y1.2
-X0.2Y1.1
-X0.2Y1.0
-X0.2Y0.9
-X0.2Y0.8
-X0.2Y0.7
-X0.2Y0.6
-X0.2Y0.5
-X0.475Y2.725
-X0.475Y2.625
-X0.475Y2.525
 X1.8Y2.4
 X1.8Y2.3
 X1.8Y2.2
@@ -207,12 +168,53 @@ X1.9Y0.5
 X1.55Y0.35
 X1.55Y0.25
 X1.55Y0.15
-X1.5Y2.675
-X1.5Y2.575
+X0.1Y2.4
+X0.1Y2.3
+X0.1Y2.2
+X0.1Y2.1
+X0.1Y2.0
+X0.1Y1.9
+X0.1Y1.8
+X0.1Y1.7
+X0.1Y1.6
+X0.1Y1.5
+X0.1Y1.4
+X0.1Y1.3
+X0.1Y1.2
+X0.1Y1.1
+X0.1Y1.0
+X0.1Y0.9
+X0.1Y0.8
+X0.1Y0.7
+X0.1Y0.6
+X0.1Y0.5
+X0.2Y2.4
+X0.2Y2.3
+X0.2Y2.2
+X0.2Y2.1
+X0.2Y2.0
+X0.2Y1.9
+X0.2Y1.8
+X0.2Y1.7
+X0.2Y1.6
+X0.2Y1.5
+X0.2Y1.4
+X0.2Y1.3
+X0.2Y1.2
+X0.2Y1.1
+X0.2Y1.0
+X0.2Y0.9
+X0.2Y0.8
+X0.2Y0.7
+X0.2Y0.6
+X0.2Y0.5
+X0.475Y2.725
+X0.475Y2.625
+X0.475Y2.525
 X0.475Y0.25
 X0.475Y0.15
-X1.6478Y2.925
-X1.825Y2.925
+X1.5Y2.675
+X1.5Y2.575
 T5
 X1.5986Y2.8266
 X1.8742Y2.8266

kicad/6809e/v1/6809e_adapter.sch

@@ -1,4 +1,5 @@
 EESchema Schematic File Version 4
+LIBS:6809e_adapter-cache
 EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
@@ -615,7 +616,7 @@ U 1 1 5D7BB685
 P 9600 1700
 F 0 "D4" H 9600 1600 50  0000 C CNN
 F 1 "MBR130" H 9600 1800 50  0000 C CNN
-F 2 "Diode_SMD:D_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 9600 1700 50  0001 C CNN
+F 2 "Diode_SMD:D_SOD-323_HandSoldering" H 9600 1700 50  0001 C CNN
 F 3 "~" H 9600 1700 50  0001 C CNN
 	1    9600 1700
 	-1   0    0    1   
@@ -630,7 +631,7 @@ U 1 1 5D7DCB4D
 P 8050 1700
 F 0 "D5" H 8050 1600 50  0000 C CNN
 F 1 "MBR130" H 8050 1800 50  0000 C CNN
-F 2 "Diode_SMD:D_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 8050 1700 50  0001 C CNN
+F 2 "Diode_SMD:D_SOD-323_HandSoldering" H 8050 1700 50  0001 C CNN
 F 3 "~" H 8050 1700 50  0001 C CNN
 	1    8050 1700
 	-1   0    0    1   
@@ -1213,7 +1214,6 @@ Text Label 8500 2400 2    60   ~ 0
 ID1
 Text Label 8500 2500 2    60   ~ 0
 ID3
-NoConn ~ 9650 3250
 $Comp
 L Device:R_Small R14
 U 1 1 5D90172A
@@ -1410,4 +1410,120 @@ Wire Wire Line
 Connection ~ 5300 6350
 Wire Wire Line
 	5300 6350 5300 4700
+$Comp
+L Device:R_Small R17
+U 1 1 5DAF3EB5
+P 5250 800
+F 0 "R17" H 5280 820 50  0000 L CNN
+F 1 "22K" H 5280 760 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 5250 800 50  0001 C CNN
+F 3 "" H 5250 800 50  0000 C CNN
+	1    5250 800 
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R_Small R16
+U 1 1 5DAF42B0
+P 5250 2200
+F 0 "R16" H 5280 2220 50  0000 L CNN
+F 1 "22K" H 5280 2160 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 5250 2200 50  0001 C CNN
+F 3 "" H 5250 2200 50  0000 C CNN
+	1    5250 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R_Small R19
+U 1 1 5DAF4773
+P 4750 800
+F 0 "R19" H 4780 820 50  0000 L CNN
+F 1 "22K" H 4780 760 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4750 800 50  0001 C CNN
+F 3 "" H 4750 800 50  0000 C CNN
+	1    4750 800 
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R_Small R15
+U 1 1 5DAF4ADB
+P 4500 800
+F 0 "R15" H 4530 820 50  0000 L CNN
+F 1 "22K" H 4530 760 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4500 800 50  0001 C CNN
+F 3 "" H 4500 800 50  0000 C CNN
+	1    4500 800 
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R_Small R20
+U 1 1 5DAF4E82
+P 4250 800
+F 0 "R20" H 4280 820 50  0000 L CNN
+F 1 "22K" H 4280 760 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 4250 800 50  0001 C CNN
+F 3 "" H 4250 800 50  0000 C CNN
+	1    4250 800 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5900 1400 5250 1400
+Wire Wire Line
+	5250 1400 5250 900 
+Wire Wire Line
+	5900 1500 5250 1500
+Wire Wire Line
+	5250 1500 5250 2100
+Wire Wire Line
+	5900 1600 5000 1600
+Wire Wire Line
+	5000 1600 5000 900 
+Wire Wire Line
+	5900 1700 4750 1700
+Wire Wire Line
+	4750 1700 4750 900 
+Wire Wire Line
+	5900 1800 4500 1800
+Wire Wire Line
+	4500 1800 4500 900 
+Wire Wire Line
+	5900 1900 4250 1900
+Wire Wire Line
+	4250 1900 4250 900 
+Wire Wire Line
+	4250 700  4250 600 
+Wire Wire Line
+	4250 600  4500 600 
+Wire Wire Line
+	5250 700  5250 600 
+Connection ~ 5250 600 
+Wire Wire Line
+	5250 600  5750 600 
+Wire Wire Line
+	5000 700  5000 600 
+Connection ~ 5000 600 
+Wire Wire Line
+	4750 700  4750 600 
+Connection ~ 4750 600 
+Wire Wire Line
+	4750 600  5000 600 
+Wire Wire Line
+	4500 700  4500 600 
+Connection ~ 4500 600 
+Wire Wire Line
+	4500 600  4750 600 
+Text Label 5250 2300 3    60   ~ 0
+GND
+Wire Wire Line
+	5000 600  5250 600 
+$Comp
+L Device:R_Small R18
+U 1 1 5DAF4507
+P 5000 800
+F 0 "R18" H 5030 820 50  0000 L CNN
+F 1 "22K" H 5030 760 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder" H 5000 800 50  0001 C CNN
+F 3 "" H 5000 800 50  0000 C CNN
+	1    5000 800 
+	1    0    0    -1  
+$EndComp
 $EndSCHEMATC

kicad/6809e/v1/manufacturing/6809e_adapter.gko

@@ -0,0 +1,23 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.1.4-e60b266~84~ubuntu18.04.1*
+G04 #@! TF.CreationDate,2019-10-24T14:21:48+01:00*
+G04 #@! TF.ProjectId,6809e_adapter,36383039-655f-4616-9461-707465722e6b,rev?*
+G04 #@! TF.SameCoordinates,PX9fdfbc0PY791ddc0*
+G04 #@! TF.FileFunction,Profile,NP*
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 5.1.4-e60b266~84~ubuntu18.04.1) date 2019-10-24 14:21:48*
+%MOMM*%
+%LPD*%
+G04 APERTURE LIST*
+%ADD10C,0.150000*%
+G04 APERTURE END LIST*
+D10*
+X49911000Y77216000D02*
+X49911000Y2032000D01*
+X49911000Y2032000D02*
+X889000Y2032000D01*
+X889000Y2032000D02*
+X889000Y77216000D01*
+X889000Y77216000D02*
+X49911000Y77216000D01*
+M02*

kicad/6809e/v1/manufacturing/6809e_adapter.xln

@@ -0,0 +1,212 @@
+M48
+; DRILL file {KiCad 5.1.4-e60b266~84~ubuntu18.04.1} date Thu 24 Oct 2019 14:21:52 BST
+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2019-10-24T14:21:52+01:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.4-e60b266~84~ubuntu18.04.1
+FMAT,2
+INCH
+T1C0.0118
+T2C0.0157
+T3C0.0354
+T4C0.0394
+T5C0.0512
+%
+G90
+G05
+T1
+X0.775Y2.275
+X0.775Y2.2
+X0.775Y2.125
+X0.775Y2.025
+X0.775Y1.925
+X0.775Y1.0
+X0.775Y0.9
+X0.775Y0.8
+X0.775Y0.7
+X0.775Y0.6
+X0.775Y0.5
+X0.79Y1.6
+X0.79Y1.55
+X0.79Y1.5
+X0.79Y1.45
+X0.79Y1.4
+X0.79Y1.35
+X0.79Y1.3
+X1.2Y1.625
+X1.2Y1.45
+X1.225Y2.4
+X1.225Y2.275
+X1.225Y2.2
+X1.225Y2.125
+X1.225Y2.0
+X1.225Y1.9
+X1.225Y1.79
+X1.225Y1.74
+X1.225Y1.65
+X1.225Y1.595
+X1.225Y1.55
+X1.225Y1.5
+X1.225Y1.07
+X1.225Y1.015
+X1.225Y0.88
+X1.225Y0.8
+X1.225Y0.7
+X1.225Y0.6
+X1.225Y0.5
+X1.475Y1.775
+X1.4751Y1.09
+T2
+X0.325Y1.98
+X0.4Y1.7
+X0.4Y1.04
+X0.4Y0.975
+X0.425Y2.425
+X0.455Y0.37
+X0.525Y1.825
+X0.525Y1.775
+X0.68Y1.85
+X0.68Y1.75
+X0.7Y2.25
+X0.72Y1.85
+X0.72Y1.75
+X0.9Y0.15
+X0.92Y2.425
+X0.92Y2.375
+X0.925Y1.7
+X0.925Y1.65
+X0.925Y0.975
+X0.925Y0.925
+X0.95Y1.275
+X0.95Y0.55
+X1.01Y1.97
+X1.05Y2.28
+X1.05Y1.525
+X1.05Y0.55
+X1.075Y1.9
+X1.075Y1.2
+X1.075Y1.15
+X1.28Y1.05
+X1.28Y0.95
+X1.3Y2.25
+X1.3Y0.4
+X1.32Y1.05
+X1.32Y0.95
+X1.45Y0.3
+X1.465Y0.925
+X1.5Y1.02
+X1.5Y0.98
+X1.575Y1.875
+X1.575Y1.15
+X1.6Y1.8
+X1.675Y2.35
+X1.69Y0.98
+X1.69Y0.9
+X1.69Y0.725
+X1.69Y0.65
+X1.69Y0.475
+X1.6902Y0.5498
+X1.79Y0.39
+T3
+X0.925Y2.925
+X1.025Y2.925
+X0.725Y2.925
+X0.825Y2.925
+X0.525Y2.925
+X0.625Y2.925
+T4
+X0.475Y0.25
+X0.475Y0.15
+X1.8Y2.4
+X1.8Y2.3
+X1.8Y2.2
+X1.8Y2.1
+X1.8Y2.0
+X1.8Y1.9
+X1.8Y1.8
+X1.8Y1.7
+X1.8Y1.6
+X1.8Y1.5
+X1.8Y1.4
+X1.8Y1.3
+X1.8Y1.2
+X1.8Y1.1
+X1.8Y1.0
+X1.8Y0.9
+X1.8Y0.8
+X1.8Y0.7
+X1.8Y0.6
+X1.8Y0.5
+X1.9Y2.4
+X1.9Y2.3
+X1.9Y2.2
+X1.9Y2.1
+X1.9Y2.0
+X1.9Y1.9
+X1.9Y1.8
+X1.9Y1.7
+X1.9Y1.6
+X1.9Y1.5
+X1.9Y1.4
+X1.9Y1.3
+X1.9Y1.2
+X1.9Y1.1
+X1.9Y1.0
+X1.9Y0.9
+X1.9Y0.8
+X1.9Y0.7
+X1.9Y0.6
+X1.9Y0.5
+X0.1Y2.4
+X0.1Y2.3
+X0.1Y2.2
+X0.1Y2.1
+X0.1Y2.0
+X0.1Y1.9
+X0.1Y1.8
+X0.1Y1.7
+X0.1Y1.6
+X0.1Y1.5
+X0.1Y1.4
+X0.1Y1.3
+X0.1Y1.2
+X0.1Y1.1
+X0.1Y1.0
+X0.1Y0.9
+X0.1Y0.8
+X0.1Y0.7
+X0.1Y0.6
+X0.1Y0.5
+X0.2Y2.4
+X0.2Y2.3
+X0.2Y2.2
+X0.2Y2.1
+X0.2Y2.0
+X0.2Y1.9
+X0.2Y1.8
+X0.2Y1.7
+X0.2Y1.6
+X0.2Y1.5
+X0.2Y1.4
+X0.2Y1.3
+X0.2Y1.2
+X0.2Y1.1
+X0.2Y1.0
+X0.2Y0.9
+X0.2Y0.8
+X0.2Y0.7
+X0.2Y0.6
+X0.2Y0.5
+X1.55Y0.35
+X1.55Y0.25
+X1.55Y0.15
+X1.6478Y2.925
+X1.825Y2.925
+X0.1675Y2.925
+X0.3447Y2.925
+T5
+X1.5986Y2.8266
+X1.8742Y2.8266
+X0.1183Y2.8266
+X0.3939Y2.8266
+T0
+M30

release.sh

@@ -16,8 +16,9 @@ pushd target
 make clean
 make
 
-cp --parents */*/*.bit ../${DIR}
-cp --parents */*/*.mcs ../${DIR}
+cp --parents */*/ice*.bit ../${DIR}
+cp --parents */*/ice*.bin ../${DIR}
+cp --parents */*/ice*.mcs ../${DIR}
 
 popd
 
@@ -27,5 +28,3 @@ popd
 
 echo "Built release in: "${DIR}
 unzip -l releases/${NAME}.zip
-
- 

src/AtomBusMon.vhd

@@ -1,161 +0,0 @@
---------------------------------------------------------------------------------
--- Copyright (c) 2015 David Banks
---
---------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /
--- \   \   \/
---  \   \
---  /   /         Filename  : AtomBusMon.vhd
--- /___/   /\     Timestamp : 30/05/2015
--- \   \  /  \
---  \___\/\___\
---
---Design Name: AtomBusMon
---Device: XC3S250E
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity AtomBusMon is
-    generic (
-       LEDsActiveHigh : boolean := false;    -- default value correct for GODIL
-       SW1ActiveHigh  : boolean := true;     -- default value correct for GODIL
-       SW2ActiveHigh  : boolean := false;    -- default value correct for GODIL
-       ClkMult        : integer := 10;       -- default value correct for GODIL
-       ClkDiv         : integer := 31;       -- default value correct for GODIL
-       ClkPer         : real    := 20.345    -- default value correct for GODIL
-       );
-    port (
-        clock49         : in    std_logic;
-
-        -- 6502 Signals
-        Addr             : in    std_logic_vector(15 downto 0);
-        Phi2             : in    std_logic;
-        RNW              : in    std_logic;
-        Sync             : in    std_logic;
-        Rdy              : out   std_logic;
-        nRST             : inout std_logic;
-
-        -- External trigger inputs
-        trig             : in    std_logic_vector(1 downto 0);
-
-        -- HD44780 LCD
-        --lcd_rs           : out   std_logic;
-        --lcd_rw           : out   std_logic;
-        --lcd_e            : out   std_logic;
-        --lcd_db           : inout std_logic_vector(7 downto 4);
-
-        -- AVR Serial Port
-        avr_RxD          : in    std_logic;
-        avr_TxD          : out   std_logic;
-
-        -- GODIL Switches
-        sw1              : in    std_logic;
-        sw2              : in    std_logic;
-
-        -- GODIL LEDs
-        led3             : out   std_logic;
-        led6             : out   std_logic;
-        led8             : out   std_logic;
-
-        -- OHO_DY1 connected to test connector
-        tmosi            : out   std_logic;
-        tdin             : out   std_logic;
-        tcclk            : out   std_logic
-    );
-end AtomBusMon;
-
-architecture behavioral of AtomBusMon is
-
-signal clock_avr : std_logic;
-signal Rdy_int   : std_logic;
-signal nRSTin    : std_logic;
-signal nRSTout   : std_logic;
-
-    signal led3_n         : std_logic;  -- led to indicate ext trig 0 is active
-    signal led6_n         : std_logic;  -- led to indicate ext trig 1 is active
-    signal led8_n         : std_logic;  -- led to indicate CPU has hit a breakpoint (and is stopped)
-    signal sw_interrupt_n : std_logic;  -- switch to pause the CPU
-    signal sw_reset_n     : std_logic;  -- switch to reset the CPU
-
-begin
-
-    -- Generics allows polarity of switches/LEDs to be tweaked from the project file
-    sw_interrupt_n <= not sw1 when SW1ActiveHigh else sw1;
-    sw_reset_n     <= not sw2 when SW2ActiveHigh else sw2;
-    led3           <= not led3_n when LEDsActiveHigh else led3_n;
-    led6           <= not led6_n when LEDsActiveHigh else led6_n;
-    led8           <= not led8_n when LEDsActiveHigh else led8_n;
-
-    inst_dcm0 : entity work.DCM0
-      generic map (
-        ClkMult      => ClkMult,
-        ClkDiv       => ClkDiv,
-        ClkPer       => ClkPer
-      )
-      port map(
-        CLKIN_IN     => clock49,
-        CLKFX_OUT    => clock_avr
-      );
-
-    mon : entity work.BusMonCore
-    generic map (
-        avr_prog_mem_size => 1024 * 8
-    )
-    port map (
-        clock_avr    => clock_avr,
-        busmon_clk   => Phi2,
-        busmon_clken => '1',
-        cpu_clk      => not Phi2,
-        cpu_clken    => '1',
-        Addr         => Addr,
-        Data         => (others => '0'),
-        Rd_n         => not RNW,
-        Wr_n         => RNW,
-        RdIO_n       => '1',
-        WrIO_n       => '1',
-        Sync         => Sync,
-        Rdy          => Rdy_int,
-        nRSTin       => nRSTin,
-        nRSTout      => nRSTout,
-        CountCycle   => Rdy_int,
-        Regs         => (others => '0'),
-        RdMemOut     => open,
-        WrMemOut     => open,
-        RdIOOut      => open,
-        WrIOOut      => open,
-        AddrOut      => open,
-        DataOut      => open,
-        DataIn       => (others => '0'),
-        Done         => '1',
-        trig         => trig,
-        lcd_rs       => open,
-        lcd_rw       => open,
-        lcd_e        => open,
-        lcd_db       => open,
-        avr_RxD      => avr_RxD,
-        avr_TxD      => avr_TxD,
-        sw1          => not sw_interrupt_n,
-        nsw2         => sw_reset_n,
-        led3         => led3_n,
-        led6         => led6_n,
-        led8         => led8_n,
-        tmosi        => tmosi,
-        tdin         => tdin,
-        tcclk        => tcclk,
-        SS_Step      => open,
-        SS_Single    => open
-    );
-    Rdy <= Rdy_int;
-
-    -- Tristate buffer driving reset back out
-    nRSTin <= nRST;
-    nRST <= '0' when nRSTout <= '0' else 'Z';
-
-end behavioral;
-
-

src/AtomFast6502.vhd

@@ -1,281 +0,0 @@
---------------------------------------------------------------------------------
--- Copyright (c) 2015 David Banks
---
---------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /
--- \   \   \/
---  \   \
---  /   /         Filename  : AtomBusMon.vhd
--- /___/   /\     Timestamp : 30/05/2015
--- \   \  /  \
---  \___\/\___\
---
---Design Name: AtomBusMon
---Device: XC3S250E
---
--- This desing uses a DCM to generate a 16x internal clock from Phi0
--- Output signals can be placed in units of 1/16th Phi0
---
--- There are two constraints to be aware of:
---
--- 1. There is no defined phase relationship between Phi0 and Phi1/2
--- This is because Phi is typically too slow for a Spartan -6 DLL
--- If the host system also uses Phi0, then this may cause problems.
---
--- 2. Phi0 must be a single frequency clock, or the DCM will not lock
--- This will not, therefore, work in a Beeb because of the clock
--- stretching when IO devices are accessed.
---
--- The Atom satisfies both of these constraints.
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-use work.OhoPack.all ;
-
-entity AtomFast6502 is
-    generic (
-       UseT65Core     : boolean := true;
-       UseAlanDCore   : boolean := false;
-       LEDsActiveHigh : boolean := false;    -- default value correct for GODIL
-       SW1ActiveHigh  : boolean := true;     -- default value correct for GODIL
-       SW2ActiveHigh  : boolean := false;    -- default value correct for GODIL
-       ClkMult        : integer := 10;       -- default value correct for GODIL
-       ClkDiv         : integer := 31;       -- default value correct for GODIL
-       ClkPer         : real    := 20.345    -- default value correct for GODIL
-       );
-    port (
-        clock49         : in    std_logic;
-
-        -- 6502 Signals
-        --Rdy             : in    std_logic;
-        Phi0            : in    std_logic;
-        Phi1            : out   std_logic;
-        Phi2            : out   std_logic;
-        IRQ_n           : in    std_logic;
-        NMI_n           : in    std_logic;
-        Sync            : out   std_logic;
-        Addr            : out   std_logic_vector(15 downto 0);
-        R_W_n           : out   std_logic;
-        Data            : inout std_logic_vector(7 downto 0);
-        SO_n            : in    std_logic;
-        Res_n           : inout std_logic;
-
-        -- External trigger inputs
-        trig             : in    std_logic_vector(1 downto 0);
-
-        -- Serial Console
-        avr_RxD         : in     std_logic;
-        avr_TxD         : out    std_logic;
-
-        -- GODIL Switches
-        sw1              : in    std_logic;
-        sw2              : in    std_logic;
-
-        -- GODIL LEDs
-        led3             : out   std_logic;
-        led6             : out   std_logic;
-        led8             : out   std_logic;
-
-        -- OHO_DY1 connected to test connector
-        tmosi            : out   std_logic;
-        tdin             : out   std_logic;
-        tcclk            : out   std_logic
-
-    );
-end AtomFast6502;
-
-architecture behavioral of AtomFast6502 is
-
-    -- Clocking
-    signal clock_avr     : std_logic;
-    signal clock_16x     : std_logic;
-    signal clk_div       : std_logic_vector(3 downto 0);
-    signal cpu_clken     : std_logic;
-    signal cpu_dataen    : std_logic;
-    signal busmon_clken  : std_logic;
-
-    -- DCM watchdog
-    signal dcm_reset     : std_logic;
-    signal dcm_locked    : std_logic;
-    signal dcm_count     : std_logic_vector(9 downto 0);
-    signal edge0         : std_logic;
-    signal edge1         : std_logic;
-
-    signal Din           : std_logic_vector(7 downto 0);
-
-    signal Addr0         : std_logic_vector(15 downto 0);
-    signal R_W_n0        : std_logic;
-    signal Sync0         : std_logic;
-    signal Dout0         : std_logic_vector(7 downto 0);
-
-    signal Addr1         : std_logic_vector(15 downto 0);
-    signal R_W_n1        : std_logic;
-    signal Sync1         : std_logic;
-    signal Dout1         : std_logic_vector(7 downto 0);
-
-    signal IRQ_n_sync    : std_logic;
-    signal NMI_n_sync    : std_logic;
-
-    signal Res_n_in      : std_logic;
-    signal Res_n_out     : std_logic;
-
-    signal led3_n         : std_logic;  -- led to indicate ext trig 0 is active
-    signal led6_n         : std_logic;  -- led to indicate ext trig 1 is active
-    signal led8_n         : std_logic;  -- led to indicate CPU has hit a breakpoint (and is stopped)
-    signal sw_interrupt_n : std_logic;  -- switch to pause the CPU
-    signal sw_reset_n     : std_logic;  -- switch to reset the CPU
-
-begin
-
-    -- Generics allows polarity of switches/LEDs to be tweaked from the project file
-    sw_interrupt_n <= not sw1 when SW1ActiveHigh else sw1;
-    sw_reset_n     <= not sw2 when SW2ActiveHigh else sw2;
-    led3           <= not led3_n when LEDsActiveHigh else led3_n;
-    led6           <= not led6_n when LEDsActiveHigh else led6_n;
-    led8           <= not led8_n when LEDsActiveHigh else led8_n;
-
-    inst_dcm0 : entity work.DCM0
-      generic map (
-        ClkMult      => ClkMult,
-        ClkDiv       => ClkDiv,
-        ClkPer       => ClkPer
-      )
-      port map(
-        CLKIN_IN     => clock49,
-        CLKFX_OUT    => clock_avr
-      );
-
-    inst_dcm2 : entity work.DCM2 port map(
-        CLKIN_IN          => Phi0,
-        CLKFX_OUT         => clock_16x,
-        LOCKED            => dcm_locked,
-        RESET             => dcm_reset
-    );
-
-    core : entity work.MOS6502CpuMonCore
-    generic map (
-        UseT65Core        => UseT65Core,
-        UseAlanDCore      => UseAlanDCore,
-        avr_prog_mem_size => 1024 * 8
-    )
-    port map (
-        clock_avr    => clock_avr,
-        busmon_clk   => clock_16x,
-        busmon_clken => busmon_clken,
-        cpu_clk      => clock_16x,
-        cpu_clken    => cpu_clken,
-        IRQ_n        => IRQ_n_sync,
-        NMI_n        => NMI_n_sync,
-        Sync         => Sync0,
-        Addr         => Addr0,
-        R_W_n        => R_W_n0,
-        Din          => Din,
-        Dout         => Dout0,
-        SO_n         => SO_n,
-        Res_n_in     => Res_n_in,
-        Res_n_out    => Res_n_out,
-        Rdy          => '1',
-        trig         => trig,
-        avr_RxD      => avr_RxD,
-        avr_TxD      => avr_TxD,
-        sw1          => not sw_interrupt_n,
-        nsw2         => sw_reset_n,
-        led3         => led3_n,
-        led6         => led6_n,
-        led8         => led8_n,
-        tmosi        => tmosi,
-        tdin         => tdin,
-        tcclk        => tcclk
-    );
-
-    -- Tristate buffer driving reset back out
-    Res_n_in <= Res_n;
-    Res_n <= '0' when Res_n_out <= '0' else 'Z';
-
-    sync_gen : process(clock_16x)
-    begin
-        if rising_edge(clock_16x) then
-          NMI_n_sync <= NMI_n;
-          IRQ_n_sync <= IRQ_n;
-        end if;
-    end process;
-
-    Addr  <= Addr1;
-    R_W_n <= R_W_n1;
-    Sync  <= Sync1;
-    Data  <= Dout1 when cpu_dataen = '1' and R_W_n1 = '0' else (others => 'Z');
-
-    -- Din is registered in cpu_clken in BusMonCore
-    Din <= Data;
-
-    process(clock_16x)
-    begin
-        if rising_edge(clock_16x) then
-            -- internal clock running 16x Phi0
-            clk_div <= clk_div + 1;
-            -- clock the CPU on cycle 0
-            if (clk_div = "1111") then
-                cpu_clken <= '1';
-            else
-                cpu_clken <= '0';
-            end if;
-            -- clock the Busmon out of phase with the cpu
-            -- exactly which cycle is not critical
-            if (clk_div = "0111") then
-                busmon_clken <= '1';
-            else
-                busmon_clken <= '0';
-            end if;
-            -- toggle Phi1/2 on cycles 0 and 8
-            if (clk_div = "0000") then
-                Phi1 <= '1';
-                Phi2 <= '0';
-            elsif (clk_div = "1000") then
-                Phi1 <= '0';
-                Phi2 <= '1';
-            end if;
-            -- Skew address by one cycle wrt Phi1/2
-            -- and hold for a complete cycle
-            if (clk_div = "0001") then
-                Addr1  <= Addr0;
-                R_W_n1 <= R_W_n0;
-                Sync1  <= Sync0;
-            end if;
-            -- Skew data release by one cycle wrt Phi1/2
-            if (clk_div = "1000") then
-                cpu_dataen <= '1';
-                Dout1  <= Dout0;
-            elsif (clk_div = "0001") then
-                cpu_dataen <= '0';
-                Dout1  <= (others => '1');
-            end if;
-        end if;
-    end process;
-
-    -- This reset the DCM if is seems to have stopped outputting a clock
-    process(clock49)
-    begin
-        if rising_edge(clock49) then
-            edge0 <= clk_div(0);
-            edge1 <= edge0;
-            -- Look for an edge on the clock
-            if (edge0 /= edge1) then
-                dcm_count <= (others => '0');
-            elsif (dcm_count = "1111001111") then
-                dcm_reset <= '0';
-            elsif (dcm_count = "1000000000") then
-                dcm_reset <= '1';
-                dcm_count <= dcm_count + 1;
-            else
-                dcm_count <= dcm_count + 1;
-            end if;
-        end if;
-    end process;
-
-end behavioral;
-

src/BusMonCore.vhd

@@ -56,19 +56,23 @@ entity BusMonCore is
         -- unused in pure bus monitor mode
         Regs             : in    std_logic_vector(255 downto 0);
 
+        -- CPI Specific data
+        PdcData          : in    std_logic_vector(7 downto 0) := x"00";
+
         -- CPU Memory Read/Write
         -- unused in pure bus monitor mode
         RdMemOut         : out std_logic;
         WrMemOut         : out std_logic;
         RdIOOut          : out std_logic;
         WrIOOut          : out std_logic;
+        ExecOut          : out std_logic;
         AddrOut          : out std_logic_vector(15 downto 0);
         DataOut          : out std_logic_vector(7 downto 0);
         DataIn           : in std_logic_vector(7 downto 0);
         Done             : in std_logic;
 
-        -- Special outputs (function is CPU specific)
-        Special          : out std_logic_vector(1 downto 0);
+        -- External Interrupt Control
+        int_ctrl         : out std_logic_vector(7 downto 0) := x"00";
 
         -- Single Step interface
         SS_Single        : out std_logic;
@@ -77,24 +81,18 @@ entity BusMonCore is
         -- External trigger inputs
         trig             : in    std_logic_vector(1 downto 0);
 
-        -- HD44780 LCD
-        lcd_rs           : out   std_logic;
-        lcd_rw           : out   std_logic;
-        lcd_e            : out   std_logic;
-        lcd_db           : inout std_logic_vector(7 downto 4);
-
         -- AVR Serial Port
         avr_RxD          : in    std_logic;
         avr_TxD          : out   std_logic;
 
-        -- GODIL Switches
-        sw1              : in    std_logic;
-        nsw2             : in    std_logic;
+        -- Switches
+        sw_reset_cpu    : in    std_logic;
+        sw_reset_avr    : in    std_logic;
 
-        -- GODIL LEDs
-        led3             : out   std_logic;
-        led6             : out   std_logic;
-        led8             : out   std_logic;
+        -- LEDs
+        led_bkpt        : out   std_logic;
+        led_trig0       : out   std_logic;
+        led_trig1       : out   std_logic;
 
         -- OHO_DY1 connected to test connector
         tmosi            : out   std_logic;
@@ -105,11 +103,16 @@ end BusMonCore;
 
 architecture behavioral of BusMonCore is
 
-    signal nrst_avr        : std_logic;
 
-    signal lcd_rw_int      : std_logic;
-    signal lcd_db_in       : std_logic_vector(7 downto 4);
-    signal lcd_db_out      : std_logic_vector(7 downto 4);
+    signal cpu_reset_n     : std_logic;
+    signal nrst_avr        : std_logic;
+    signal nrst1           : std_logic;
+    signal nrst2           : std_logic;
+    signal nrst3           : std_logic;
+
+    -- debounce time is 2^17 / 16MHz = 8.192ms
+    signal nrst_counter    : unsigned(17 downto 0);
+
     signal dy_counter      : std_logic_vector(31 downto 0);
     signal dy_data         : y2d_type ;
 
@@ -118,15 +121,21 @@ architecture behavioral of BusMonCore is
     signal cmd_edge        : std_logic;
     signal cmd_edge1       : std_logic;
     signal cmd_edge2       : std_logic;
-    signal cmd             : std_logic_vector(4 downto 0);
+    signal cmd_ack         : std_logic;
+    signal cmd_ack1        : std_logic;
+    signal cmd_ack2        : std_logic;
+    signal cmd             : std_logic_vector(5 downto 0);
 
     signal addr_sync       : std_logic_vector(15 downto 0);
     signal addr_inst       : std_logic_vector(15 downto 0);
     signal Addr1           : std_logic_vector(15 downto 0);
     signal Data1           : std_logic_vector(7 downto 0);
 
+    signal ext_clk         : std_logic;
+    signal timer0Count     : std_logic_vector(23 downto 0);
+    signal timer1Count     : std_logic_vector(23 downto 0);
     signal cycleCount      : std_logic_vector(23 downto 0);
-    signal cycleCount_inst : std_logic_vector(23 downto 0);
+    signal instrCount      : std_logic_vector(23 downto 0);
 
     signal single          : std_logic;
     signal reset           : std_logic;
@@ -146,7 +155,9 @@ architecture behavioral of BusMonCore is
     signal fifo_din        : std_logic_vector(fifo_width - 1 downto 0);
     signal fifo_dout       : std_logic_vector(fifo_width - 1 downto 0);
     signal fifo_empty      : std_logic;
-    signal fifo_empty_n    : std_logic;
+    signal fifo_full       : std_logic;
+    signal fifo_not_empty1 : std_logic;
+    signal fifo_not_empty2 : std_logic;
     signal fifo_rd         : std_logic;
     signal fifo_rd_en      : std_logic;
     signal fifo_wr         : std_logic;
@@ -157,17 +168,24 @@ architecture behavioral of BusMonCore is
     signal memory_wr       : std_logic;
     signal io_rd           : std_logic;
     signal io_wr           : std_logic;
+    signal exec            : std_logic;
     signal addr_dout_reg   : std_logic_vector(23 downto 0);
     signal din_reg         : std_logic_vector(7 downto 0);
 
     signal Rdy_int         : std_logic;
 
-    signal unused_a3       : std_logic;
-    signal unused_b6       : std_logic;
-    signal unused_b7       : std_logic;
     signal unused_d6       : std_logic;
     signal unused_d7       : std_logic;
 
+    signal last_done       : std_logic;
+    signal cmd_done        : std_logic;
+
+    signal reset_counter   : std_logic_vector(9 downto 0);
+
+    signal dropped_counter : std_logic_vector(3 downto 0);
+
+    signal timer_mode      : std_logic_vector(1 downto 0);
+
 begin
 
     inst_oho_dy1 : entity work.Oho_Dy1 port map (
@@ -194,23 +212,8 @@ begin
         clk16M               => clock_avr,
         nrst                 => nrst_avr,
 
-        portain(0)           => '0',
-        portain(1)           => '0',
-        portain(2)           => '0',
-        portain(3)           => '0',
-        portain(4)           => lcd_db_in(4),
-        portain(5)           => lcd_db_in(5),
-        portain(6)           => lcd_db_in(6),
-        portain(7)           => lcd_db_in(7),
-
-        portaout(0)          => lcd_rs,
-        portaout(1)          => lcd_rw_int,
-        portaout(2)          => lcd_e,
-        portaout(3)          => unused_a3,
-        portaout(4)          => lcd_db_out(4),
-        portaout(5)          => lcd_db_out(5),
-        portaout(6)          => lcd_db_out(6),
-        portaout(7)          => lcd_db_out(7),
+        portain              => PdcData,
+        portaout             => open,
 
         -- Command Port
         portbin(0)           => '0',
@@ -226,9 +229,9 @@ begin
         portbout(2)          => cmd(2),
         portbout(3)          => cmd(3),
         portbout(4)          => cmd(4),
-        portbout(5)          => cmd_edge,
-        portbout(6)          => Special(0),
-        portbout(7)          => Special(1),
+        portbout(5)          => cmd(5),
+        portbout(6)          => cmd_edge,
+        portbout(7)          => open,
 
         -- Status Port
         portdin(0)           => '0',
@@ -237,8 +240,8 @@ begin
         portdin(3)           => '0',
         portdin(4)           => '0',
         portdin(5)           => '0',
-        portdin(6)           => sw1,
-        portdin(7)           => fifo_empty_n,
+        portdin(6)           => cmd_ack2,
+        portdin(7)           => fifo_not_empty2,
 
         portdout(0)           => muxsel(0),
         portdout(1)           => muxsel(1),
@@ -259,8 +262,19 @@ begin
 
         rxd                  => avr_RxD,
         txd                  => avr_TxD
-    );
-    fifo_empty_n <= not fifo_empty;
+        );
+
+    -- Syncronise signals crossing busmon_clk / clock_avr boundary
+    process (clock_avr)
+    begin
+        if rising_edge(clock_avr) then
+            fifo_not_empty1 <= not fifo_empty;
+            fifo_not_empty2 <= fifo_not_empty1;
+            cmd_ack1        <= cmd_ack;
+            cmd_ack2        <= cmd_ack1;
+        end if;
+    end process;
+
 
     WatchEvents_inst : entity work.WatchEvents port map(
         clk    => busmon_clk,
@@ -269,7 +283,7 @@ begin
         wr_en  => fifo_wr_en,
         rd_en  => fifo_rd_en,
         dout   => fifo_dout,
-        full   => open,
+        full   => fifo_full,
         empty  => fifo_empty
     );
     fifo_wr_en <= fifo_wr and busmon_clken;
@@ -280,29 +294,45 @@ begin
     -- DataWr1 is the data being written delayed by 1 cycle
     -- DataRd is the data being read, that is already one cycle late
     -- bw_state1(1) is 1 for writes, and 0 for reads
-    fifo_din <= cycleCount_inst & "0000" & bw_status1 & Data1 & Addr1 & addr_inst;
+    fifo_din <= instrCount & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
 
-    lcd_rw    <= lcd_rw_int;
-    lcd_db    <= lcd_db_out when lcd_rw_int = '0' else (others => 'Z');
-    lcd_db_in <= lcd_db;
+    -- Implement a 4-bit saturating counter of the number of dropped events
+    process (busmon_clk)
+    begin
+        if rising_edge(busmon_clk) then
+            if busmon_clken = '1' then
+                if fifo_rst = '1' then
+                    dropped_counter <= x"0";
+                elsif fifo_wr_en = '1' then
+                    if fifo_full = '1' then
+                        if dropped_counter /= x"F" then
+                            dropped_counter <= dropped_counter + 1;
+                        end if;
+                    else
+                        dropped_counter <= x"0";
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
 
-    led3 <= not trig(0);       -- red
-    led6 <= not trig(1);       -- red
-    led8 <= not brkpt_active;  -- green
+    led_trig0 <= trig(0);
+    led_trig1 <= trig(1);
+    led_bkpt  <= brkpt_active;
 
-    nrst_avr <= nsw2;
+    nrst_avr <= not sw_reset_avr;
 
     -- OHO DY1 Display for Testing
     dy_data(0) <= hex & "0000" & Addr(3 downto 0);
     dy_data(1) <= hex & "0000" & Addr(7 downto 4);
-    dy_data(2) <= hex & "0000" & "00" & (not nsw2) & sw1;
+    dy_data(2) <= hex & "0000" & "00" & sw_reset_avr & sw_reset_cpu;
 
     mux <= addr_inst(7 downto 0)            when muxsel = 0 else
            addr_inst(15 downto 8)           when muxsel = 1 else
            din_reg                          when muxsel = 2 else
-           cycleCount(23 downto 16)         when muxsel = 3 else
-           cycleCount(7 downto 0)           when muxsel = 4 else
-           cycleCount(15 downto 8)          when muxsel = 5 else
+           instrCount(23 downto 16)         when muxsel = 3 else
+           instrCount(7 downto 0)           when muxsel = 4 else
+           instrCount(15 downto 8)          when muxsel = 5 else
 
            fifo_dout(7 downto 0)            when muxsel = 6 else
            fifo_dout(15 downto 8)           when muxsel = 7 else
@@ -407,38 +437,55 @@ begin
     end process;
 
     -- CPU Control Commands
-    -- 0000x Enable/Disable single strpping
-    -- 0001x Enable/Disable breakpoints / watches
-    -- 0010x Load breakpoint / watch register
-    -- 0011x Reset CPU
-    -- 01000 Singe Step CPU
-    -- 01001 Read FIFO
-    -- 01010 Reset FIFO
-    -- 01011 Unused
-    -- 0110x Load address/data register
-    -- 0111x Unused
-    -- 10000 Read Memory
-    -- 10001 Read Memory and Auto Inc Address
-    -- 10010 Write Memory
-    -- 10011 Write Memory and Auto Inc Address
-    -- 10000 Read Memory
-    -- 10001 Read Memory and Auto Inc Address
-    -- 10010 Write Memory
-    -- 10011 Write Memory and Auto Inc Address
-    -- 1x1xx Unused
-    -- 11xxx Unused
+    -- 00000x Enable/Disable single stepping
+    -- 00001x Enable/Disable breakpoints / watches
+    -- 00010x Load breakpoint / watch register
+    -- 00011x Reset CPU
+    -- 001000 Singe Step CPU
+    -- 001001 Read FIFO
+    -- 001010 Reset FIFO
+    -- 001011 Unused
+    -- 00110x Load address/data register
+    -- 00111x Unused
+    -- 010000 Read Memory
+    -- 010001 Read Memory and Auto Inc Address
+    -- 010010 Write Memory
+    -- 010011 Write Memory and Auto Inc Address
+    -- 010100 Read IO
+    -- 010101 Read IO and Auto Inc Address
+    -- 010110 Write IO
+    -- 010111 Write IO and Auto Inc Address
+    -- 011000 Execute 6502 instruction
+    -- 0111xx Unused
+    -- 011x1x Unused
+    -- 011xx1 Unused
+    -- 10xxxx Int Ctrl
+    -- 1100xx Timer Mode
+    --     00 - count cpu cycles where clken = 1 and CountCycle = 1
+    --     01 - count cpu cycles where clken = 1 (ignoring CountCycle)
+    --     10 - free running timer, using busmon_clk as the source
+    --     11 - free running timer, using trig0 as the source
+
+    -- Use trig0 to drive a free running counter for absolute timings
+    ext_clk <= trig(0);
+    timer1Process: process (ext_clk)
+    begin
+        if rising_edge(ext_clk) then
+            timer1Count <= timer1Count + 1;
+        end if;
+    end process;
 
     cpuProcess: process (busmon_clk)
     begin
         if rising_edge(busmon_clk) then
+            timer0Count <= timer0Count + 1;
             if busmon_clken = '1' then
-                -- Cycle counter, wraps every 16s at 1MHz
-                if (nRSTin = '0') then
+                -- Cycle counter
+                if (cpu_reset_n = '0') then
                     cycleCount <= (others => '0');
-                elsif (CountCycle = '1') then
+                elsif (CountCycle = '1' or timer_mode(0) = '1') then
                     cycleCount <= cycleCount + 1;
                 end if;
-
                 -- Command processing
                 cmd_edge1 <= cmd_edge;
                 cmd_edge2 <= cmd_edge1;
@@ -449,61 +496,83 @@ begin
                 memory_wr <= '0';
                 io_rd     <= '0';
                 io_wr     <= '0';
+                exec      <= '0';
                 SS_Step   <= '0';
-                if (cmd_edge2 = '0' and cmd_edge1 = '1') then
-                    if (cmd(4 downto 1) = "0000") then
+                if (cmd_edge2 /= cmd_edge1) then
+                    if (cmd(5 downto 1) = "00000") then
                         single <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 1) = "0001") then
+                    if (cmd(5 downto 1) = "00001") then
                         brkpt_enable <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 1) = "0010") then
+                    if (cmd(5 downto 1) = "00010") then
                         brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
                     end if;
 
-                    if (cmd(4 downto 1) = "0110") then
+                    if (cmd(5 downto 1) = "00110") then
                         addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
                     end if;
 
-                    if (cmd(4 downto 1) = "0011") then
+                    if (cmd(5 downto 1) = "00011") then
                         reset <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 0) = "01001") then
+                    if (cmd(5 downto 0) = "01001") then
                         fifo_rd <= '1';
                     end if;
 
-                    if (cmd(4 downto 0) = "01010") then
+                    if (cmd(5 downto 0) = "01010") then
                         fifo_rst <= '1';
                     end if;
 
-                    if (cmd(4 downto 1) = "1000") then
+                    if (cmd(5 downto 1) = "01000") then
                         memory_rd <= '1';
                         auto_inc  <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 1) = "1001") then
+                    if (cmd(5 downto 1) = "01001") then
                         memory_wr <= '1';
                         auto_inc  <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 1) = "1010") then
+                    if (cmd(5 downto 1) = "01010") then
                         io_rd <= '1';
                         auto_inc  <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 1) = "1011") then
+                    if (cmd(5 downto 1) = "01011") then
                         io_wr <= '1';
                         auto_inc  <= cmd(0);
                     end if;
 
+                    if (cmd(5 downto 0) = "011000") then
+                        exec <= '1';
+                    end if;
+
+                    if (cmd(5 downto 4) = "10") then
+                        int_ctrl(to_integer(unsigned(cmd(3 downto 2))) * 2 + 1 downto to_integer(unsigned(cmd(3 downto 2))) * 2) <= cmd(1 downto 0);
+                    end if;
+
+                    if (cmd(5 downto 2) = "1100") then
+                        timer_mode <= cmd(1 downto 0);
+                    end if;
+
+                    -- Acknowlege certain commands immediately
+                    if cmd(5 downto 4) /= "01" then
+                        cmd_ack <= not cmd_ack;
+                    end if;
+
                 end if;
 
-                -- Auto increment the memory address reg the cycle after a rd/wr
-                if (auto_inc = '1' and Done = '1') then
-                    addr_dout_reg(23 downto 8) <= addr_dout_reg(23 downto 8) + 1;
+                if cmd_done = '1' then
+                    -- Acknowlege memory access commands when thet complete
+                    cmd_ack <= not cmd_ack;
+                    -- Auto increment the memory address reg the cycle after a rd/wr
+                    if auto_inc = '1' then
+                        addr_dout_reg(23 downto 8) <= addr_dout_reg(23 downto 8) + 1;
+                    end if;
                 end if;
 
                 -- Single Stepping
@@ -511,19 +580,23 @@ begin
                     single <= '1';
                 end if;
 
-                if ((single = '0') or (cmd_edge2 = '0' and cmd_edge1 = '1' and cmd = "01000")) then
+                if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "001000")) then
                     Rdy_int <= (not brkpt_active);
                     SS_Step <= (not brkpt_active);
                 else
                     Rdy_int <= (not Sync);
                 end if;
 
-                nRSTout <= not reset;
-
                 -- Latch instruction address for the whole cycle
                 if (Sync = '1') then
                     addr_inst <= Addr;
-                    cycleCount_inst <= cycleCount;
+                    if timer_mode = "10" then
+                        instrCount <= timer0Count;
+                    elsif timer_mode = "11" then
+                        instrCount <= timer1Count;
+                    else
+                        instrCount <= cycleCount;
+                    end if;
                 end if;
 
                 -- Breakpoints and Watches written to the FIFO
@@ -547,6 +620,13 @@ begin
                 if (Done = '1') then
                     din_reg <= DataIn;
                 end if;
+                -- Delay the increnting of the address by one cycle
+                last_done <= Done;
+                if Done = '1' and last_done = '0' then
+                    cmd_done <= '1';
+                else
+                    cmd_done <= '0';
+                end if;
             end if;
         end if;
     end process;
@@ -559,5 +639,53 @@ begin
     AddrOut <= addr_dout_reg(23 downto 8);
     DataOut <= addr_dout_reg(7 downto 0);
     SS_Single <= single;
+    ExecOut <= exec;
+
+    -- Reset Logic
+    -- Generate a short (~1ms @ 1MHz) power up reset pulse
+    --
+    -- This is in case FPGA configuration takes longer than
+    -- the length of the host system reset pulse.
+    --
+    -- Some 6502 cores (particularly the AlanD core) needs
+    -- reset to be asserted to start.
+
+
+
+    -- Debounce nRSTin using clock_avr as this is always 16MHz
+    --    nrst1 is the possibly glitchy input
+    --    nrst2 is the filtered output
+    process(clock_avr)
+    begin
+        if rising_edge(clock_avr) then
+            -- Syncronise nRSTin
+            nrst1 <= nRSTin and (not sw_reset_cpu);
+            -- De-glitch NRST
+            if nrst1 = '0' then
+                nrst_counter <= to_unsigned(0, nrst_counter'length);
+                nrst2 <= '0';
+            elsif nrst_counter(nrst_counter'high) = '0' then
+                nrst_counter <= nrst_counter + 1;
+            else
+                nrst2 <= '1';
+            end if;
+        end if;
+    end process;
+
+
+    process(cpu_clk)
+    begin
+        if rising_edge(cpu_clk) then
+            if cpu_clken = '1' then
+                if reset_counter(reset_counter'high) = '0' then
+                    reset_counter <= reset_counter + 1;
+                end if;
+                nrst3 <= nrst2 and reset_counter(reset_counter'high) and (not reset);
+                cpu_reset_n <= nrst3;
+            end if;
+        end if;
+    end process;
+
+    nRSTout <= cpu_reset_n;
 
 end behavioral;

src/DCM/DCM2.vhd

@@ -1,59 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.Vcomponents.all;
-
-entity DCM2 is
-    port (CLKIN_IN  : in  std_logic;
-          RESET     : in  std_logic;
-          CLKFX_OUT  : out std_logic;
-          LOCKED    : out std_logic); 
-end DCM2;
-
-architecture BEHAVIORAL of DCM2 is
-    signal CLKFX_BUF   : std_logic;
-    signal CLKIN_IBUFG : std_logic;
-    signal GND_BIT     : std_logic;
-begin
-
-    GND_BIT <= '0';
-    CLKFX_BUFG_INST : BUFG
-        port map (I => CLKFX_BUF, O => CLKFX_OUT);
-    
-    DCM_INST : DCM
-        generic map(CLK_FEEDBACK          => "NONE",
-                    CLKDV_DIVIDE          => 4.0,
-                    CLKFX_DIVIDE          => 1,
-                    CLKFX_MULTIPLY        => 16,
-                    CLKIN_DIVIDE_BY_2     => false,
-                    CLKIN_PERIOD          => 1000.00,
-                    CLKOUT_PHASE_SHIFT    => "NONE",
-                    DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
-                    DFS_FREQUENCY_MODE    => "LOW",
-                    DLL_FREQUENCY_MODE    => "LOW",
-                    DUTY_CYCLE_CORRECTION => true,
-                    FACTORY_JF            => x"C080",
-                    PHASE_SHIFT           => 0,
-                    STARTUP_WAIT          => false)
-        port map (CLKFB    => GND_BIT,
-                  CLKIN    => CLKIN_IN,
-                  DSSEN    => GND_BIT,
-                  PSCLK    => GND_BIT,
-                  PSEN     => GND_BIT,
-                  PSINCDEC => GND_BIT,
-                  RST      => RESET,
-                  CLKDV    => open,
-                  CLKFX    => CLKFX_BUF,
-                  CLKFX180 => open,
-                  CLK0     => open,
-                  CLK2X    => open,
-                  CLK2X180 => open,
-                  CLK90    => open,
-                  CLK180   => open,
-                  CLK270   => open,
-                  LOCKED   => LOCKED,
-                  PSDONE   => open,
-                  STATUS   => open);
-
-end BEHAVIORAL;

src/MC6809CpuMon.vhd

@@ -1,5 +1,5 @@
---------------------------------------------------------------------------------
--- Copyright (c) 2015 David Banks
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
 --
 --------------------------------------------------------------------------------
 --   ____  ____
@@ -7,51 +7,43 @@
 -- /___/  \  /
 -- \   \   \/
 --  \   \
---  /   /         Filename  : MC6808ECpuMon.vhd
--- /___/   /\     Timestamp : 02/07/2015
+--  /   /         Filename  : MC6808CpuMon.vhd
+-- /___/   /\     Timestamp : 24/10/2019
 -- \   \  /  \
 --  \___\/\___\
 --
---Design Name: MC6808ECpuMon
---Device: XC3S250E
+--Design Name: MC6808CpuMon
+--Device: multiple
 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
-use work.OhoPack.all ;
 
-entity MC6809ECpuMon is
+entity MC6809CpuMon is
     generic (
-       UseCPU09Core   : boolean := true;
-       LEDsActiveHigh : boolean := false;    -- default value correct for GODIL
-       SW1ActiveHigh  : boolean := true;     -- default value correct for GODIL
-       SW2ActiveHigh  : boolean := false;    -- default value correct for GODIL
-       ClkMult        : integer := 10;       -- default value correct for GODIL
-       ClkDiv         : integer := 31;       -- default value correct for GODIL
-       ClkPer         : real    := 20.345    -- default value correct for GODIL
+       ClkMult           : integer;
+       ClkDiv            : integer;
+       ClkPer            : real;
+       num_comparators   : integer;
+       avr_prog_mem_size : integer
        );
     port (
-        clock49         : in    std_logic;
+        -- Fast clock
+        clock           : in    std_logic;
 
-        -- A locally generated test clock
-        -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
-        -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
-        clock_test      : out   std_logic;
-
-        -- 6809/6809E mode selection
-        -- Jumper is between pins B1 and D1
-        -- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
-        -- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
-        EMode_n         : in   std_logic;
+        -- Quadrature clocks
+        E               : in    std_logic;
+        Q               : in    std_logic;
 
         --6809 Signals
-        PIN33           : inout std_logic;
-        PIN34           : inout std_logic;
-        PIN35           : inout std_logic;
-        PIN36           : inout std_logic;
-        PIN38           : inout std_logic;
-        PIN39           : in    std_logic;
+        DMA_n_BREQ_n    : in   std_logic;
+
+        -- 6809E Sig
+        TSC             : in    std_logic;
+        LIC             : out   std_logic;
+        AVMA            : out   std_logic;
+        BUSY            : out   std_logic;
 
         -- Signals common to both 6809 and 6809E
         RES_n           : in    std_logic;
@@ -73,14 +65,14 @@ entity MC6809ECpuMon is
         avr_RxD         : in    std_logic;
         avr_TxD         : out   std_logic;
 
-        -- GODIL Switches
-        sw1             : in    std_logic;
-        sw2             : in    std_logic;
+        -- Switches
+        sw_reset_cpu    : in    std_logic;
+        sw_reset_avr    : in    std_logic;
 
-        -- GODIL LEDs
-        led3            : out   std_logic;
-        led6            : out   std_logic;
-        led8            : out   std_logic;
+        -- LEDs
+        led_bkpt        : out   std_logic;
+        led_trig0       : out   std_logic;
+        led_trig1       : out   std_logic;
 
         -- OHO_DY1 connected to test connector
         tmosi           : out   std_logic;
@@ -92,25 +84,25 @@ entity MC6809ECpuMon is
         test2           : out   std_logic
 
     );
-end MC6809ECpuMon;
+end MC6809CpuMon;
 
-architecture behavioral of MC6809ECpuMon is
+architecture behavioral of MC6809CpuMon is
 
     signal clock_avr      : std_logic;
 
     signal cpu_clk        : std_logic;
+    signal cpu_reset_n    : std_logic;
     signal busmon_clk     : std_logic;
     signal R_W_n_int      : std_logic;
     signal NMI_sync       : std_logic;
     signal IRQ_sync       : std_logic;
     signal FIRQ_sync      : std_logic;
-    signal nRST_sync      : std_logic;
     signal HALT_sync      : std_logic;
     signal Addr_int       : std_logic_vector(15 downto 0);
     signal Din            : std_logic_vector(7 downto 0);
     signal Dout           : std_logic_vector(7 downto 0);
+    signal Dbusmon        : std_logic_vector(7 downto 0);
     signal Sync_int       : std_logic;
-    signal Rdy_int        : std_logic;
     signal hold           : std_logic;
 
     signal memory_rd      : std_logic;
@@ -132,22 +124,9 @@ architecture behavioral of MC6809ECpuMon is
     signal SS_Single      : std_logic;
     signal SS_Step        : std_logic;
     signal CountCycle     : std_logic;
-    signal special       : std_logic_vector(1 downto 0);
+    signal int_ctrl       : std_logic_vector(7 downto 0);
 
-    signal clk_count      : std_logic_vector(1 downto 0);
-    signal quadrature     : std_logic_vector(1 downto 0);
-    signal LIC            : std_logic;
-    signal AVMA           : std_logic;
-    signal XTAL           : std_logic;
-    signal EXTAL          : std_logic;
-    signal MRDY           : std_logic;
-    signal TSC            : std_logic;
-    signal BUSY           : std_logic;
-    signal Q              : std_logic;
-    signal E              : std_logic;
-    signal DMA_n_BREQ_n   : std_logic;
-
-    signal clock7_3728    : std_logic;
+    signal LIC_int        : std_logic;
 
     signal E_a            : std_logic; -- E delayed by 0..20ns
     signal E_b            : std_logic; -- E delayed by 20..40ns
@@ -161,24 +140,20 @@ architecture behavioral of MC6809ECpuMon is
     signal data_wr        : std_logic;
     signal nRSTout        : std_logic;
 
-    signal led3_n         : std_logic;  -- led to indicate ext trig 0 is active
-    signal led6_n         : std_logic;  -- led to indicate ext trig 1 is active
-    signal led8_n         : std_logic;  -- led to indicate CPU has hit a breakpoint (and is stopped)
-    signal sw_interrupt_n : std_logic;  -- switch to pause the CPU
-    signal sw_reset_n     : std_logic;  -- switch to reset the CPU
-
-    signal NMI_n_masked   : std_logic;
-    signal IRQ_n_masked   : std_logic;
     signal FIRQ_n_masked  : std_logic;
+    signal IRQ_n_masked   : std_logic;
+    signal NMI_n_masked   : std_logic;
+    signal RES_n_masked   : std_logic;
 
 begin
 
-    -- Generics allows polarity of switches/LEDs to be tweaked from the project file
-    sw_interrupt_n <= not sw1 when SW1ActiveHigh else sw1;
-    sw_reset_n     <= not sw2 when SW2ActiveHigh else sw2;
-    led3           <= not led3_n when LEDsActiveHigh else led3_n;
-    led6           <= not led6_n when LEDsActiveHigh else led6_n;
-    led8           <= not led8_n when LEDsActiveHigh else led8_n;
+    LIC     <= LIC_int;
+    -- The following outputs are not implemented
+    -- BUSY          (6809E mode)
+    BUSY    <= '0';
+
+    -- The following inputs are not implemented
+    -- DMA_n_BREQ_n  (6809 mode)
 
     inst_dcm0 : entity work.DCM0
       generic map (
@@ -187,14 +162,14 @@ begin
         ClkPer       => ClkPer
       )
       port map(
-        CLKIN_IN     => clock49,
+        CLKIN_IN     => clock,
         CLKFX_OUT    => clock_avr
       );
 
     mon : entity work.BusMonCore
       generic map (
-        num_comparators => 8,
-        avr_prog_mem_size => 1024 * 9
+        num_comparators => num_comparators,
+        avr_prog_mem_size => avr_prog_mem_size
       )
       port map (
         clock_avr    => clock_avr,
@@ -203,28 +178,24 @@ begin
         cpu_clk      => cpu_clk,
         cpu_clken    => '1',
         Addr         => Addr_int,
-        Data         => Data,
+        Data         => Dbusmon,
         Rd_n         => not R_W_n_int,
         Wr_n         => R_W_n_int,
         RdIO_n       => '1',
         WrIO_n       => '1',
         Sync         => Sync_int,
-        Rdy          => Rdy_int,
-        nRSTin       => nRST_sync,
-        nRSTout      => nRSTout,
+        Rdy          => open,
+        nRSTin       => RES_n_masked,
+        nRSTout      => cpu_reset_n,
         CountCycle   => CountCycle,
         trig         => trig,
-        lcd_rs       => open,
-        lcd_rw       => open,
-        lcd_e        => open,
-        lcd_db       => open,
         avr_RxD      => avr_RxD,
         avr_TxD      => avr_TxD,
-        sw1          => not sw_interrupt_n,
-        nsw2         => sw_reset_n,
-        led3         => led3_n,
-        led6         => led6_n,
-        led8         => led8_n,
+        sw_reset_cpu => sw_reset_cpu,
+        sw_reset_avr => sw_reset_avr,
+        led_bkpt     => led_bkpt,
+        led_trig0    => led_trig0,
+        led_trig1    => led_trig1,
         tmosi        => tmosi,
         tdin         => tdin,
         tcclk        => tcclk,
@@ -237,14 +208,28 @@ begin
         DataOut      => memory_dout,
         DataIn       => memory_din,
         Done         => memory_done,
-        Special      => special,
+        int_ctrl     => int_ctrl,
         SS_Step      => SS_Step,
         SS_Single    => SS_Single
     );
 
-    NMI_n_masked  <= NMI_n  or special(1);
-    FIRQ_n_masked <= FIRQ_n or special(1);
-    IRQ_n_masked  <= IRQ_n  or special(0);
+    -- The two int control bits work as follows
+    -- 00 -> IRQ_n                (enabled)
+    -- 01 -> IRQ_n or SS_Single   (enabled when free-running)
+    -- 10 -> 0                    (forced)
+    -- 11 -> 1                    (disabled)
+
+    FIRQ_n_masked <= int_ctrl(0) when int_ctrl(1) = '1' else
+                     FIRQ_n or (int_ctrl(0) and SS_single);
+
+    IRQ_n_masked  <= int_ctrl(2) when int_ctrl(3) = '1' else
+                     IRQ_n or (int_ctrl(2) and SS_single);
+
+    NMI_n_masked  <= int_ctrl(4) when int_ctrl(5) = '1' else
+                     NMI_n or (int_ctrl(4) and SS_single);
+
+    RES_n_masked  <= int_ctrl(6) when int_ctrl(7) = '1' else
+                     RES_n or (int_ctrl(6) and SS_single);
 
     -- The CPU is slightly pipelined and the register update of the last
     -- instruction overlaps with the opcode fetch of the next instruction.
@@ -272,28 +257,26 @@ begin
     Regs1(111 downto  96) <= Regs(111 downto  96);
     Regs1(255 downto 112) <= (others => '0');
 
-    GenCPU09Core: if UseCPU09Core generate
-        inst_cpu09: entity work.cpu09 port map (
-            clk      => cpu_clk,
-            rst      => not nRST_sync,
-            vma      => AVMA,
-            lic_out  => LIC,
-            ifetch   => ifetch,
-            opfetch  => open,
-            ba       => BA,
-            bs       => BS,
-            addr     => Addr_int,
-            rw       => R_W_n_int,
-            data_out => Dout,
-            data_in  => Din,
-            irq      => IRQ_sync,
-            firq     => FIRQ_sync,
-            nmi      => NMI_sync,
-            halt     => HALT_sync,
-            hold     => hold,
-            Regs     => Regs
+    inst_cpu09: entity work.cpu09 port map (
+        clk      => cpu_clk,
+        rst      => not cpu_reset_n,
+        vma      => AVMA,
+        lic_out  => LIC_int,
+        ifetch   => ifetch,
+        opfetch  => open,
+        ba       => BA,
+        bs       => BS,
+        addr     => Addr_int,
+        rw       => R_W_n_int,
+        data_out => Dout,
+        data_in  => Din,
+        irq      => IRQ_sync,
+        firq     => FIRQ_sync,
+        nmi      => NMI_sync,
+        halt     => HALT_sync,
+        hold     => hold,
+        Regs     => Regs
         );
-    end generate;
 
 
     -- Synchronize all external inputs, to avoid subtle bugs like missed interrupts
@@ -303,7 +286,6 @@ begin
             NMI_sync   <= not NMI_n_masked;
             IRQ_sync   <= not IRQ_n_masked;
             FIRQ_sync  <= not FIRQ_n_masked;
-            nRST_sync  <= RES_n and nRSTout;
             HALT_sync  <= not HALT_n;
         end if;
     end process;
@@ -315,7 +297,7 @@ begin
     begin
         if rising_edge(cpu_clk) then
             if (hold = '0') then
-                ifetch1 <= ifetch and not LIC;
+                ifetch1 <= ifetch and not LIC_int;
             end if;
         end if;
     end process;
@@ -373,43 +355,19 @@ begin
                          Dout when TSC = '0' and data_wr = '1' and R_W_n_int = '0' and memory_rd1 = '0' else
                   (others => 'Z');
 
+    -- Version of data seen by the Bus Mon need to use Din rather than the
+    -- external bus value as by the rising edge of cpu_clk we will have stopped driving
+    -- the external bus. On the ALS version we get away way this, but on the GODIL
+    -- version, due to the pullups, we don't. So all write watch breakpoints see
+    -- the data bus as 0xFF.
+    Dbusmon   <= Din when R_W_n_int = '1' else Dout;
+
     memory_done <= memory_rd1 or memory_wr1;
 
-    -- The following outputs are not implemented
-    -- BUSY          (6809E mode)
-    BUSY    <= '0';
-
-    -- The following inputs are not implemented
-    -- DMA_n_BREQ_n  (6809 mode)
-
-    -- Pins whose functions are dependent on "E" mode
-    PIN33        <= BUSY  when EMode_n = '0' else 'Z';
-    DMA_n_BREQ_n <= '1'   when EMode_n = '0' else PIN33;
-
-    PIN34        <= 'Z'   when EMode_n = '0' else E;
-    E            <= PIN34 when EMode_n = '0' else quadrature(1);
-
-    PIN35        <= 'Z'   when EMode_n = '0' else Q;
-    Q            <= PIN35 when EMode_n = '0' else quadrature(0);
-
-    PIN36        <= AVMA  when EMode_n = '0' else 'Z';
-    MRDY         <= '1'   when EMode_n = '0' else PIN36;
-
-    PIN38        <= LIC   when EMode_n = '0' else 'Z';
-    EXTAL        <= '0'   when EMode_n = '0' else PIN38;
-
-    TSC          <= PIN39 when EMode_n = '0' else '0';
-    XTAL         <= '0'   when EMode_n = '0' else PIN39;
-
-    -- A locally generated test clock
-    -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
-    -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
-    clock_test   <= clk_count(1) when EMode_n = '0' else clock7_3728;
-
     -- Delayed/Deglitched version of the E clock
-    e_gen : process(clock49)
+    e_gen : process(clock)
     begin
-        if rising_edge(clock49) then
+        if rising_edge(clock) then
             E_a <= E;
             E_b <= E_a;
             if E_b /= E_i then
@@ -440,42 +398,9 @@ begin
     -- Note: on the dragon this is not critical; setting to '1' seemed to work
     data_wr    <= Q or E;
 
-    -- Quadrature clock generator, unused in 6809E mode
-    quadrature_gen : process(EXTAL)
-    begin
-        if rising_edge(EXTAL) then
-            if (MRDY = '1') then
-                if (quadrature = "00") then
-                    quadrature <= "01";
-                elsif (quadrature = "01") then
-                    quadrature <= "11";
-                elsif (quadrature = "11") then
-                    quadrature <= "10";
-                else
-                    quadrature <= "00";
-                end if;
-            end if;
-        end if;
-    end process;
-
-    -- Seperate piece of circuitry that emits a 7.3728MHz clock
-
-    inst_dcm1 : entity work.DCM1 port map(
-        CLKIN_IN          => clock49,
-        CLK0_OUT          => clock7_3728,
-        CLK0_OUT1         => open,
-        CLK2X_OUT         => open
-    );
-
-    clk_gen : process(clock7_3728)
-    begin
-        if rising_edge(clock7_3728) then
-            clk_count <= clk_count + 1;
-        end if;
-    end process;
-
     -- Spare pins used for testing
     test1   <= E_a;
     test2   <= E_c;
 
+
 end behavioral;

src/MC6809CpuMonALS.vhd

@@ -0,0 +1,175 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : MC6809CpuMonALS.vhd
+-- /___/   /\     Timestamp : 24/10/2019
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: MC6809CpuMonALS
+--Device: XC6SLX9
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MC6809CpuMonALS is
+    generic (
+       num_comparators   : integer := 8;        -- default value correct for ALS
+       avr_prog_mem_size : integer := 1024 * 9  -- default value correct for ALS
+       );
+    port (
+        clock            : in    std_logic;
+
+        --6809 Signals
+        BUSY             : out    std_logic;
+        E                : in     std_logic;
+        Q                : in     std_logic;
+        AVMA             : out    std_logic;
+        LIC              : out    std_logic;
+        TSC              : in     std_logic;
+
+        -- Signals common to both 6809 and 6809E
+        RES_n            : in    std_logic;
+        NMI_n            : in    std_logic;
+        IRQ_n            : in    std_logic;
+        FIRQ_n           : in    std_logic;
+        HALT_n           : in    std_logic;
+        BS               : out   std_logic;
+        BA               : out   std_logic;
+        R_W_n            : out   std_logic_vector(1 downto 0);
+
+        Addr             : out   std_logic_vector(15 downto 0);
+        Data             : inout std_logic_vector(7 downto 0);
+
+        -- Level Shifers Controls
+        OERW_n           : out   std_logic;
+        OEAL_n           : out   std_logic;
+        OEAH_n           : out   std_logic;
+        OED_n            : out   std_logic;
+        DIRD             : out   std_logic;
+
+        -- External trigger inputs
+        trig             : in    std_logic_vector(1 downto 0);
+
+        -- ID/mode inputs
+        mode            : in    std_logic;
+        id              : in    std_logic_vector(3 downto 0);
+
+        -- Serial Console
+        avr_RxD          : in    std_logic;
+        avr_TxD          : out   std_logic;
+
+        -- Switches
+        sw1              : in    std_logic;
+        sw2              : in    std_logic;
+
+        -- LEDs
+        led1             : out   std_logic;
+        led2             : out   std_logic;
+        led3             : out   std_logic
+
+    );
+end MC6809CpuMonALS;
+
+architecture behavioral of MC6809CpuMonALS is
+
+    signal R_W_n_int     : std_logic;
+
+    signal sw_reset_cpu : std_logic;
+    signal sw_reset_avr : std_logic;
+    signal led_bkpt     : std_logic;
+    signal led_trig0    : std_logic;
+    signal led_trig1    : std_logic;
+
+begin
+
+    sw_reset_cpu <= not sw1;
+    sw_reset_avr <= not sw2;
+    led1         <= led_bkpt;
+    led2         <= led_trig0;
+    led3         <= led_trig1;
+
+    wrapper : entity work.MC6809CpuMon
+      generic map (
+          ClkMult           => 12,
+          ClkDiv            => 25,
+          ClkPer            => 20.000,
+          num_comparators   => num_comparators,
+          avr_prog_mem_size => avr_prog_mem_size
+      )
+      port map (
+
+        -- Fast clock
+        clock           => clock,
+
+        -- Quadrature clocks
+        E               => E,
+        Q               => Q,
+
+        --6809 Signals
+        DMA_n_BREQ_n    => '1',
+
+        -- 6809E Signals
+        TSC             => TSC,
+        LIC             => LIC,
+        AVMA            => AVMA,
+        BUSY            => BUSY,
+
+        -- Signals common to both 6809 and 6809E
+        RES_n           => RES_n,
+        NMI_n           => NMI_n,
+        IRQ_n           => IRQ_n,
+        FIRQ_n          => FIRQ_n,
+        HALT_n          => HALT_n,
+        BS              => BS,
+        BA              => BA,
+        R_W_n           => R_W_n_int,
+
+        Addr            => Addr,
+        Data            => Data,
+
+        -- External trigger inputs
+        trig            => trig,
+
+        -- Serial Console
+        avr_RxD         => avr_RxD,
+        avr_TxD         => avr_TxD,
+
+        -- Switches
+        sw_reset_cpu    => sw_reset_cpu,
+        sw_reset_avr    => sw_reset_avr,
+
+        -- LEDs
+        led_bkpt        => led_bkpt,
+        led_trig0       => led_trig0,
+        led_trig1       => led_trig1,
+
+        -- OHO_DY1 connected to test connector
+        tmosi           => open,
+        tdin            => open,
+        tcclk           => open,
+
+        -- Debugging signals
+        test1           => open,
+        test2           => open
+    );
+
+    -- 6809 Outputs
+    R_W_n <= R_W_n_int & R_W_n_int;
+
+    -- Level Shifter Controls
+    OERW_n  <= TSC;
+    OEAH_n  <= TSC;
+    OEAL_n  <= TSC;
+    OED_n   <= TSC or not (Q or E);
+    DIRD    <= R_W_n_int;
+
+end behavioral;

src/MC6809CpuMonGODIL.vhd

@@ -0,0 +1,247 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : MC6808CpuMonGODIL.vhd
+-- /___/   /\     Timestamp : 24/10/2019
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: MC6808CpuMonGODIL
+--Device: XC3S250E/XC3S500E
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MC6809CpuMonGODIL is
+    generic (
+       num_comparators   : integer := 8;        -- default value correct for GODIL
+       avr_prog_mem_size : integer := 1024 * 9  -- default value correct for GODIL
+       );
+    port (
+        clock49         : in    std_logic;
+
+        -- A locally generated test clock
+        -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
+        -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
+        clock_test      : out   std_logic;
+
+        -- 6809/6809E mode selection
+        -- Jumper is between pins B1 and D1
+        -- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
+        -- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
+        EMode_n         : in   std_logic;
+
+        --6809 Signals
+        PIN33           : inout std_logic;
+        PIN34           : inout std_logic;
+        PIN35           : inout std_logic;
+        PIN36           : inout std_logic;
+        PIN38           : inout std_logic;
+        PIN39           : in    std_logic;
+
+        -- Signals common to both 6809 and 6809E
+        RES_n           : in    std_logic;
+        NMI_n           : in    std_logic;
+        IRQ_n           : in    std_logic;
+        FIRQ_n          : in    std_logic;
+        HALT_n          : in    std_logic;
+        BS              : out   std_logic;
+        BA              : out   std_logic;
+        R_W_n           : out   std_logic;
+
+        Addr            : out   std_logic_vector(15 downto 0);
+        Data            : inout std_logic_vector(7 downto 0);
+
+        -- External trigger inputs
+        trig            : in    std_logic_vector(1 downto 0);
+
+        -- Serial Console
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
+
+        -- GODIL Switches
+        sw1             : in    std_logic;
+        sw2             : in    std_logic;
+
+        -- GODIL LEDs
+        led3            : out   std_logic;
+        led6            : out   std_logic;
+        led8            : out   std_logic;
+
+        -- OHO_DY1 connected to test connector
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
+
+        -- Debugging signals
+        test1           : out   std_logic;
+        test2           : out   std_logic
+
+    );
+end MC6809CpuMonGODIL;
+
+architecture behavioral of MC6809CpuMonGODIL is
+
+    signal clk_count      : std_logic_vector(1 downto 0);
+    signal quadrature     : std_logic_vector(1 downto 0);
+
+    signal clock7_3728    : std_logic;
+
+    signal sw_reset_avr   : std_logic;
+    signal sw_reset_cpu   : std_logic;
+    signal led_bkpt       : std_logic;
+    signal led_trig0      : std_logic;
+    signal led_trig1      : std_logic;
+
+    signal E              : std_logic;
+    signal Q              : std_logic;
+    signal DMA_n_BREQ_n   : std_logic;
+    signal MRDY           : std_logic;
+    signal TSC            : std_logic;
+    signal LIC            : std_logic;
+    signal AVMA           : std_logic;
+    signal BUSY           : std_logic;
+
+    signal XTAL           : std_logic;
+    signal EXTAL          : std_logic;
+
+begin
+
+    -- Generics allows polarity of switches/LEDs to be tweaked from the project file
+    sw_reset_cpu <= sw1;
+    sw_reset_avr <= not sw2;
+    led3         <= not led_trig0;
+    led6         <= not led_trig1;
+    led8         <= not led_bkpt;
+
+    wrapper : entity work.MC6809CpuMon
+      generic map (
+          ClkMult           => 10,
+          ClkDiv            => 31,
+          ClkPer            => 20.345,
+          num_comparators   => num_comparators,
+          avr_prog_mem_size => avr_prog_mem_size
+      )
+      port map (
+
+        -- Fast clock
+        clock           => clock49,
+
+        -- Quadrature clocks
+        E               => E,
+        Q               => Q,
+
+        --6809 Signals
+        DMA_n_BREQ_n    => DMA_n_BREQ_n,
+
+        -- 6809E Sig
+        TSC             => TSC,
+        LIC             => LIC,
+        AVMA            => AVMA,
+        BUSY            => BUSY,
+
+        -- Signals common to both 6809 and 6809E
+        RES_n           => RES_n,
+        NMI_n           => NMI_n,
+        IRQ_n           => IRQ_n,
+        FIRQ_n          => FIRQ_n,
+        HALT_n          => HALT_n,
+        BS              => BS,
+        BA              => BA,
+        R_W_n           => R_W_n,
+
+        Addr            => Addr,
+        Data            => Data,
+
+        -- External trigger inputs
+        trig            => trig,
+
+        -- Serial Console
+        avr_RxD         => avr_RxD,
+        avr_TxD         => avr_TxD,
+
+        -- Switches
+        sw_reset_cpu    => sw_reset_cpu,
+        sw_reset_avr    => sw_reset_avr,
+
+        -- LEDs
+        led_bkpt        => led_bkpt,
+        led_trig0       => led_trig0,
+        led_trig1       => led_trig1,
+
+        -- OHO_DY1 connected to test connector
+        tmosi           => tmosi,
+        tdin            => tdin,
+        tcclk           => tcclk,
+
+        -- Debugging signals
+        test1           => test1,
+        test2           => test2
+    );
+
+    -- Pins whose functions are dependent on "E" mode
+    PIN33        <= BUSY  when EMode_n = '0' else 'Z';
+    DMA_n_BREQ_n <= '1'   when EMode_n = '0' else PIN33;
+
+    PIN34        <= 'Z'   when EMode_n = '0' else E;
+    E            <= PIN34 when EMode_n = '0' else quadrature(1);
+
+    PIN35        <= 'Z'   when EMode_n = '0' else Q;
+    Q            <= PIN35 when EMode_n = '0' else quadrature(0);
+
+    PIN36        <= AVMA  when EMode_n = '0' else 'Z';
+    MRDY         <= '1'   when EMode_n = '0' else PIN36;
+
+    PIN38        <= LIC   when EMode_n = '0' else 'Z';
+    EXTAL        <= '0'   when EMode_n = '0' else PIN38;
+
+    TSC          <= PIN39 when EMode_n = '0' else '0';
+    XTAL         <= '0'   when EMode_n = '0' else PIN39;
+
+    -- A locally generated test clock
+    -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
+    -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
+    clock_test   <= clk_count(1) when EMode_n = '0' else clock7_3728;
+
+    -- Quadrature clock generator, unused in 6809E mode
+    quadrature_gen : process(EXTAL)
+    begin
+        if rising_edge(EXTAL) then
+            if (MRDY = '1') then
+                if (quadrature = "00") then
+                    quadrature <= "01";
+                elsif (quadrature = "01") then
+                    quadrature <= "11";
+                elsif (quadrature = "11") then
+                    quadrature <= "10";
+                else
+                    quadrature <= "00";
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Seperate piece of circuitry that emits a 7.3728MHz clock
+    inst_dcm1 : entity work.DCM1 port map(
+        CLKIN_IN          => clock49,
+        CLK0_OUT          => clock7_3728,
+        CLK0_OUT1         => open,
+        CLK2X_OUT         => open
+    );
+
+    clk_gen : process(clock7_3728)
+    begin
+        if rising_edge(clock7_3728) then
+            clk_count <= clk_count + 1;
+        end if;
+    end process;
+
+end behavioral;

src/MC6809CpuMonLX9.vhd

@@ -0,0 +1,246 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : MC6808CpuMonLX9.vhd
+-- /___/   /\     Timestamp : 24/10/2019
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: MC6808CpuMonLX9
+--Device: XC3S250E/XC3S500E
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MC6809CpuMonLX9 is
+    generic (
+       num_comparators   : integer := 8;        -- default value correct for LX9
+       avr_prog_mem_size : integer := 1024 * 9  -- default value correct for LX9
+       );
+    port (
+        clock           : in    std_logic;
+
+        -- A locally generated test clock
+        -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
+        -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
+        clock_test      : out   std_logic;
+
+        -- 6809/6809E mode selection
+        -- Jumper is between pins B1 and D1
+        -- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
+        -- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
+        EMode_n         : in   std_logic;
+
+        --6809 Signals
+        PIN33           : inout std_logic;
+        PIN34           : inout std_logic;
+        PIN35           : inout std_logic;
+        PIN36           : inout std_logic;
+        PIN38           : inout std_logic;
+        PIN39           : in    std_logic;
+
+        -- Signals common to both 6809 and 6809E
+        RES_n           : in    std_logic;
+        NMI_n           : in    std_logic;
+        IRQ_n           : in    std_logic;
+        FIRQ_n          : in    std_logic;
+        HALT_n          : in    std_logic;
+        BS              : out   std_logic;
+        BA              : out   std_logic;
+        R_W_n           : out   std_logic;
+
+        Addr            : out   std_logic_vector(15 downto 0);
+        Data            : inout std_logic_vector(7 downto 0);
+
+        -- External trigger inputs
+        trig            : in    std_logic_vector(1 downto 0);
+
+        -- Serial Console
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
+
+        -- LX9 Switches
+        sw1             : in    std_logic;
+        sw2             : in    std_logic;
+
+        -- LX9 LEDs
+        led3            : out   std_logic;
+        led6            : out   std_logic;
+        led8            : out   std_logic;
+
+        -- OHO_DY1 connected to test connector
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
+
+        -- Debugging signals
+        test1           : out   std_logic;
+        test2           : out   std_logic
+
+    );
+end MC6809CpuMonLX9;
+
+architecture behavioral of MC6809CpuMonLX9 is
+
+    signal clk_count      : std_logic_vector(1 downto 0);
+    signal quadrature     : std_logic_vector(1 downto 0);
+
+    signal clock7_3728    : std_logic;
+
+    signal sw_reset_avr   : std_logic;
+    signal sw_reset_cpu   : std_logic;
+    signal led_bkpt       : std_logic;
+    signal led_trig0      : std_logic;
+    signal led_trig1      : std_logic;
+
+    signal E              : std_logic;
+    signal Q              : std_logic;
+    signal DMA_n_BREQ_n   : std_logic;
+    signal MRDY           : std_logic;
+    signal TSC            : std_logic;
+    signal LIC            : std_logic;
+    signal AVMA           : std_logic;
+    signal BUSY           : std_logic;
+
+    signal XTAL           : std_logic;
+    signal EXTAL          : std_logic;
+
+begin
+
+    sw_reset_cpu <= sw1;
+    sw_reset_avr <= sw2;
+    led3         <= led_trig0;
+    led6         <= led_trig1;
+    led8         <= led_bkpt;
+
+    wrapper : entity work.MC6809CpuMon
+      generic map (
+          ClkMult           => 8,
+          ClkDiv            => 25,
+          ClkPer            => 20.000,
+          num_comparators   => num_comparators,
+          avr_prog_mem_size => avr_prog_mem_size
+      )
+      port map (
+
+        -- Fast clock
+        clock           => clock,
+
+        -- Quadrature clocks
+        E               => E,
+        Q               => Q,
+
+        --6809 Signals
+        DMA_n_BREQ_n    => DMA_n_BREQ_n,
+
+        -- 6809E Sig
+        TSC             => TSC,
+        LIC             => LIC,
+        AVMA            => AVMA,
+        BUSY            => BUSY,
+
+        -- Signals common to both 6809 and 6809E
+        RES_n           => RES_n,
+        NMI_n           => NMI_n,
+        IRQ_n           => IRQ_n,
+        FIRQ_n          => FIRQ_n,
+        HALT_n          => HALT_n,
+        BS              => BS,
+        BA              => BA,
+        R_W_n           => R_W_n,
+
+        Addr            => Addr,
+        Data            => Data,
+
+        -- External trigger inputs
+        trig            => trig,
+
+        -- Serial Console
+        avr_RxD         => avr_RxD,
+        avr_TxD         => avr_TxD,
+
+        -- Switches
+        sw_reset_cpu    => sw_reset_cpu,
+        sw_reset_avr    => sw_reset_avr,
+
+        -- LEDs
+        led_bkpt        => led_bkpt,
+        led_trig0       => led_trig0,
+        led_trig1       => led_trig1,
+
+        -- OHO_DY1 connected to test connector
+        tmosi           => tmosi,
+        tdin            => tdin,
+        tcclk           => tcclk,
+
+        -- Debugging signals
+        test1           => test1,
+        test2           => test2
+    );
+
+    -- Pins whose functions are dependent on "E" mode
+    PIN33        <= BUSY  when EMode_n = '0' else 'Z';
+    DMA_n_BREQ_n <= '1'   when EMode_n = '0' else PIN33;
+
+    PIN34        <= 'Z'   when EMode_n = '0' else E;
+    E            <= PIN34 when EMode_n = '0' else quadrature(1);
+
+    PIN35        <= 'Z'   when EMode_n = '0' else Q;
+    Q            <= PIN35 when EMode_n = '0' else quadrature(0);
+
+    PIN36        <= AVMA  when EMode_n = '0' else 'Z';
+    MRDY         <= '1'   when EMode_n = '0' else PIN36;
+
+    PIN38        <= LIC   when EMode_n = '0' else 'Z';
+    EXTAL        <= '0'   when EMode_n = '0' else PIN38;
+
+    TSC          <= PIN39 when EMode_n = '0' else '0';
+    XTAL         <= '0'   when EMode_n = '0' else PIN39;
+
+    -- A locally generated test clock
+    -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
+    -- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
+    clock_test   <= clk_count(1) when EMode_n = '0' else clock7_3728;
+
+    -- Quadrature clock generator, unused in 6809E mode
+    quadrature_gen : process(EXTAL)
+    begin
+        if rising_edge(EXTAL) then
+            if (MRDY = '1') then
+                if (quadrature = "00") then
+                    quadrature <= "01";
+                elsif (quadrature = "01") then
+                    quadrature <= "11";
+                elsif (quadrature = "11") then
+                    quadrature <= "10";
+                else
+                    quadrature <= "00";
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Seperate piece of circuitry that emits a 7.3728MHz clock
+    inst_dcm1 : entity work.DCM1 port map(
+        CLKIN_IN          => clock,
+        CLK0_OUT          => clock7_3728,
+        CLK0_OUT1         => open,
+        CLK2X_OUT         => open
+    );
+
+    clk_gen : process(clock7_3728)
+    begin
+        if rising_edge(clock7_3728) then
+            clk_count <= clk_count + 1;
+        end if;
+    end process;
+
+end behavioral;

src/MOS6502CpuMon.vhd

@@ -1,5 +1,5 @@
---------------------------------------------------------------------------------
--- Copyright (c) 2015 David Banks
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
 --
 --------------------------------------------------------------------------------
 --   ____  ____
@@ -7,34 +7,31 @@
 -- /___/  \  /
 -- \   \   \/
 --  \   \
---  /   /         Filename  : AtomBusMon.vhd
--- /___/   /\     Timestamp : 30/05/2015
+--  /   /         Filename  : MOS6502CpuMon.vhd
+-- /___/   /\     Timestamp : 03/11/2019
 -- \   \  /  \
 --  \___\/\___\
 --
---Design Name: AtomBusMon
---Device: XC3S250E
+--Design Name: MOS6502CpuMon
+--Device: multiple
 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
-use work.OhoPack.all ;
 
-
-entity AtomCpuMon is
+entity MOS6502CpuMon is
     generic (
-       UseT65Core     : boolean := true;
-       UseAlanDCore   : boolean := false;
-       LEDsActiveHigh : boolean := false;    -- default value correct for GODIL
-       SW1ActiveHigh  : boolean := true;     -- default value correct for GODIL
-       SW2ActiveHigh  : boolean := false;    -- default value correct for GODIL
-       ClkMult        : integer := 10;       -- default value correct for GODIL
-       ClkDiv         : integer := 31;       -- default value correct for GODIL
-       ClkPer         : real    := 20.345    -- default value correct for GODIL
+       UseT65Core        : boolean;
+       UseAlanDCore      : boolean;
+       ClkMult           : integer;
+       ClkDiv            : integer;
+       ClkPer            : real;
+       num_comparators   : integer;
+       avr_prog_mem_size : integer
        );
     port (
-        clock49         : in    std_logic;
+        clock           : in    std_logic;
 
         -- 6502 Signals
         Phi0            : in    std_logic;
@@ -47,42 +44,47 @@ entity AtomCpuMon is
         R_W_n           : out   std_logic;
         Data            : inout std_logic_vector(7 downto 0);
         SO_n            : in    std_logic;
-        Res_n           : inout std_logic;
+        Res_n           : in    std_logic;
         Rdy             : in    std_logic;
 
         -- External trigger inputs
-        trig             : in    std_logic_vector(1 downto 0);
+        trig            : in    std_logic_vector(1 downto 0);
 
         -- Jumpers
-        fakeTube_n      : in     std_logic;
+        fakeTube_n      : in    std_logic;
 
         -- Serial Console
-        avr_RxD         : in     std_logic;
-        avr_TxD         : out    std_logic;
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
 
-        -- GODIL Switches
-        sw1              : in    std_logic;
-        sw2              : in    std_logic;
+        -- Switches
+        sw_reset_cpu    : in    std_logic;
+        sw_reset_avr    : in    std_logic;
 
-        -- GODIL LEDs
-        led3             : out   std_logic;
-        led6             : out   std_logic;
-        led8             : out   std_logic;
+        -- LEDs
+        led_bkpt        : out   std_logic;
+        led_trig0       : out   std_logic;
+        led_trig1       : out   std_logic;
 
         -- OHO_DY1 connected to test connector
-        tmosi            : out   std_logic;
-        tdin             : out   std_logic;
-        tcclk            : out   std_logic
-    );
-end AtomCpuMon;
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
 
-architecture behavioral of AtomCpuMon is
+        -- Test connector signals
+        test            : inout std_logic_vector(3 downto 0)
+    );
+end MOS6502CpuMon;
+
+architecture behavioral of MOS6502CpuMon is
 
     signal clock_avr     : std_logic;
 
     signal Din           : std_logic_vector(7 downto 0);
     signal Dout          : std_logic_vector(7 downto 0);
 
+    signal Rdy_latched   : std_logic;
+
     signal IRQ_n_sync    : std_logic;
     signal NMI_n_sync    : std_logic;
 
@@ -96,24 +98,8 @@ architecture behavioral of AtomCpuMon is
     signal cpu_clk       : std_logic;
     signal busmon_clk    : std_logic;
 
-    signal Res_n_in      : std_logic;
-    signal Res_n_out     : std_logic;
-
-    signal led3_n         : std_logic;  -- led to indicate ext trig 0 is active
-    signal led6_n         : std_logic;  -- led to indicate ext trig 1 is active
-    signal led8_n         : std_logic;  -- led to indicate CPU has hit a breakpoint (and is stopped)
-    signal sw_interrupt_n : std_logic;  -- switch to pause the CPU
-    signal sw_reset_n     : std_logic;  -- switch to reset the CPU
-
 begin
 
-    -- Generics allows polarity of switches/LEDs to be tweaked from the project file
-    sw_interrupt_n <= not sw1 when SW1ActiveHigh else sw1;
-    sw_reset_n     <= not sw2 when SW2ActiveHigh else sw2;
-    led3           <= not led3_n when LEDsActiveHigh else led3_n;
-    led6           <= not led6_n when LEDsActiveHigh else led6_n;
-    led8           <= not led8_n when LEDsActiveHigh else led8_n;
-
     inst_dcm0 : entity work.DCM0
       generic map (
         ClkMult      => ClkMult,
@@ -121,7 +107,7 @@ begin
         ClkPer       => ClkPer
       )
       port map(
-        CLKIN_IN     => clock49,
+        CLKIN_IN     => clock,
         CLKFX_OUT    => clock_avr
       );
 
@@ -129,7 +115,8 @@ begin
     generic map (
        UseT65Core        => UseT65Core,
        UseAlanDCore      => UseAlanDCore,
-       avr_prog_mem_size => 1024 * 8
+       num_comparators   => num_comparators,
+       avr_prog_mem_size => avr_prog_mem_size
     )
     port map (
         clock_avr    => clock_avr,
@@ -145,26 +132,22 @@ begin
         Din          => Din,
         Dout         => Dout,
         SO_n         => SO_n,
-        Res_n_in     => Res_n_in,
-        Res_n_out    => Res_n_out,
-        Rdy          => Rdy,
+        Res_n        => Res_n,
+        Rdy          => Rdy_latched,
         trig         => trig,
         avr_RxD      => avr_RxD,
         avr_TxD      => avr_TxD,
-        sw1          => not sw_interrupt_n,
-        nsw2         => sw_reset_n,
-        led3         => led3_n,
-        led6         => led6_n,
-        led8         => led8_n,
+        sw_reset_cpu => sw_reset_cpu,
+        sw_reset_avr => sw_reset_avr,
+        led_bkpt     => led_bkpt,
+        led_trig0    => led_trig0,
+        led_trig1    => led_trig1,
         tmosi        => tmosi,
         tdin         => tdin,
-        tcclk        => tcclk
+        tcclk        => tcclk,
+        test         => test
     );
 
-    -- Tristate buffer driving reset back out
-    Res_n_in <= Res_n;
-    Res_n <= '0' when Res_n_out <= '0' else 'Z';
-
     sync_gen : process(cpu_clk)
     begin
         if rising_edge(cpu_clk) then
@@ -173,6 +156,27 @@ begin
         end if;
     end process;
 
+    -- 6502: Sample Rdy on the rising edge of Phi0
+    rdy_6502: if UseT65Core generate
+        process(Phi0)
+        begin
+            if rising_edge(Phi0) then
+                Rdy_latched <= Rdy;
+            end if;
+        end process;
+    end generate;
+
+    -- 65C02: Sample Rdy on the falling edge of Phi0
+    rdy_65c02: if UseAlanDCore generate
+        process(Phi0)
+        begin
+            if falling_edge(Phi0) then
+                Rdy_latched <= Rdy;
+            end if;
+        end process;
+    end generate;
+
+    -- Sample Data on the falling edge of Phi0_a
     data_latch : process(Phi0_a)
     begin
         if falling_edge(Phi0_a) then
@@ -188,9 +192,9 @@ begin
     R_W_n <= R_W_n_int;
     Addr  <= Addr_int;
 
-    clk_gen : process(clock49)
+    clk_gen : process(clock)
     begin
-        if rising_edge(clock49) then
+        if rising_edge(clock) then
           Phi0_a <= Phi0;
           Phi0_b <= Phi0_a;
           Phi0_c <= Phi0_b;

src/MOS6502CpuMonALS.vhd

@@ -0,0 +1,203 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : MOS6502CpuMonALS.vhd
+-- /___/   /\     Timestamp : 20/09/2019
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: MOS6502CpuMonALS
+--Device: XC6SLX9
+--
+--
+-- This is a small wrapper around MOS6502CpuMon that add the following signals:
+--   OEAH_n
+--   OEAL_n
+--   OED_n
+--   DIRD
+--   BE
+--   ML_n
+--   VP_n
+-- (these are not fully implemented yet)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MOS6502CpuMonALS is
+   generic (
+       UseT65Core        : boolean := true;
+       UseAlanDCore      : boolean := false;
+       num_comparators   : integer := 8;
+       avr_prog_mem_size : integer := 8 * 1024
+       );
+    port (
+        clock            : in    std_logic;
+
+        -- 6502 Signals
+        PhiIn            : in    std_logic;
+        Phi1Out          : out   std_logic;
+        Phi2Out          : out   std_logic;
+        IRQ_n            : in    std_logic;
+        NMI_n            : in    std_logic;
+        Sync             : out   std_logic;
+        Addr             : out   std_logic_vector(15 downto 0);
+        R_W_n            : out   std_logic_vector(1 downto 0);
+        Data             : inout std_logic_vector(7 downto 0);
+        SO_n             : in    std_logic;
+        Res_n            : in    std_logic;
+        Rdy              : in    std_logic;
+
+        -- 65C02 Signals
+        BE               : in    std_logic;
+        ML_n             : out   std_logic;
+        VP_n             : out   std_logic;
+
+        -- Level Shifter Controls
+        OERW_n           : out   std_logic;
+        OEAH_n           : out   std_logic;
+        OEAL_n           : out   std_logic;
+        OED_n            : out   std_logic;
+        DIRD             : out   std_logic;
+
+        -- External trigger inputs
+        trig             : in    std_logic_vector(1 downto 0);
+
+        -- ID/mode inputs
+        mode             : in    std_logic;
+        id               : in    std_logic_vector(3 downto 0);
+
+        -- Serial Console
+        avr_RxD          : in    std_logic;
+        avr_TxD          : out   std_logic;
+
+        -- Switches
+        sw1              : in   std_logic;
+        sw2              : in   std_logic;
+
+        -- LEDs
+        led1             : out  std_logic;
+        led2             : out  std_logic;
+        led3             : out  std_logic;
+
+        -- OHO_DY1 LED display
+        tmosi            : out  std_logic;
+        tdin             : out  std_logic;
+        tcclk            : out  std_logic;
+
+        -- Test connector signals
+        test             : inout std_logic_vector(3 downto 0)
+    );
+end MOS6502CpuMonALS;
+
+architecture behavioral of MOS6502CpuMonALS is
+
+    signal R_W_n_int    : std_logic;
+
+    signal sw_reset_cpu : std_logic;
+    signal sw_reset_avr : std_logic;
+    signal led_bkpt     : std_logic;
+    signal led_trig0    : std_logic;
+    signal led_trig1    : std_logic;
+
+    signal PhiIn1       : std_logic;
+    signal PhiIn2       : std_logic;
+    signal PhiIn3       : std_logic;
+    signal PhiIn4       : std_logic;
+
+begin
+
+    sw_reset_cpu <= not sw1;
+    sw_reset_avr <= not sw2;
+    led1         <= led_bkpt;
+    led2         <= led_trig0;
+    led3         <= led_trig1;
+
+    wrapper : entity work.MOS6502CpuMon
+        generic map (
+            UseT65Core        => UseT65Core,
+            UseAlanDCore      => UseAlanDCore,
+            ClkMult           => 12,
+            ClkDiv            => 25,
+            ClkPer            => 20.000,
+            num_comparators   => num_comparators,
+            avr_prog_mem_size => avr_prog_mem_size
+            )
+        port map (
+            clock             => clock,
+
+            -- 6502 Signals
+            Phi0              => PhiIn,
+            Phi1              => Phi1Out,
+            Phi2              => Phi2Out,
+            IRQ_n             => IRQ_n,
+            NMI_n             => NMI_n,
+            Sync              => Sync,
+            Addr              => Addr,
+            R_W_n             => R_W_n_int,
+            Data              => Data,
+            SO_n              => SO_n,
+            Res_n             => Res_n,
+            Rdy               => Rdy,
+
+            -- External trigger inputs
+            trig              => trig,
+
+            -- Jumpers
+            fakeTube_n        => '1',
+
+            -- Serial Console
+            avr_RxD           => avr_RxD,
+            avr_TxD           => avr_TxD,
+
+            -- Switches
+            sw_reset_cpu      => sw_reset_cpu,
+            sw_reset_avr      => sw_reset_avr,
+
+            -- LEDs
+            led_bkpt          => led_bkpt,
+            led_trig0         => led_trig0,
+            led_trig1         => led_trig1,
+
+            -- OHO_DY1 LED display
+            tmosi            => tmosi,
+            tdin             => tdin,
+            tcclk            => tcclk,
+
+            -- Test signals
+            test             => test
+            );
+
+    -- 6502 Outputs
+    R_W_n <= R_W_n_int & R_W_n_int;
+
+    -- 65C02 Outputs
+    ML_n   <= '1';
+    VP_n   <= '1';
+
+    process(clock)
+    begin
+        if rising_edge(clock) then
+            PhiIn1 <= PhiIn;
+            PhiIn2 <= PhiIn1;
+            PhiIn3 <= PhiIn2;
+            PhiIn4 <= PhiIn3;
+        end if;
+
+    end process;
+
+    -- Level Shifter Controls
+    OERW_n <= '0'; -- not (BE);
+    OEAH_n <= '0'; -- not (BE);
+    OEAL_n <= '0'; -- not (BE);
+    OED_n  <= not (BE and PhiIn and PhiIn4); -- TODO: might need to use a slightly delayed version of Phi2 here
+    DIRD   <= R_W_n_int;
+
+end behavioral;

src/MOS6502CpuMonCore.vhd

@@ -1,5 +1,5 @@
---------------------------------------------------------------------------------
--- Copyright (c) 2015 David Banks
+------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
 --
 --------------------------------------------------------------------------------
 --   ____  ____
@@ -7,34 +7,34 @@
 -- /___/  \  /
 -- \   \   \/
 --  \   \
---  /   /         Filename  : AtomBusMon.vhd
--- /___/   /\     Timestamp : 30/05/2015
+--  /   /         Filename  : MOS6502CpuMonCore.vhd
+-- /___/   /\     Timestamp : 3/11/2019
 -- \   \  /  \
 --  \___\/\___\
 --
---Design Name: AtomBusMon
---Device: XC3S250E
+--Design Name: MOS6502CpuMonCore
+--Device: multiple
 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
-use work.OhoPack.all ;
 
 entity MOS6502CpuMonCore is
     generic (
        UseT65Core        : boolean;
        UseAlanDCore      : boolean;
-       avr_data_mem_size : integer := 1024 * 2; -- 2K is the mimimum
-       avr_prog_mem_size : integer := 1024 * 8  -- 6502 fits in 8K, others need 9K
+       -- default sizing is used by Electron/Beeb Fpga
+       num_comparators   : integer := 8;
+       avr_prog_mem_size : integer := 1024 * 8
     );
     port (
-        clock_avr        : in    std_logic;
+        clock_avr       : in    std_logic;
 
-        busmon_clk       : in    std_logic;
-        busmon_clken     : in    std_logic;
-        cpu_clk          : in    std_logic;
-        cpu_clken        : in    std_logic;
+        busmon_clk      : in    std_logic;
+        busmon_clken    : in    std_logic;
+        cpu_clk         : in    std_logic;
+        cpu_clken       : in    std_logic;
 
         -- 6502 Signals
         IRQ_n           : in    std_logic;
@@ -45,74 +45,90 @@ entity MOS6502CpuMonCore is
         Din             : in    std_logic_vector(7 downto 0);
         Dout            : out   std_logic_vector(7 downto 0);
         SO_n            : in    std_logic;
-        Res_n_in        : in    std_logic;
-        Res_n_out       : out   std_logic;
+        Res_n           : in    std_logic;
         Rdy             : in    std_logic;
 
         -- External trigger inputs
-        trig             : in    std_logic_vector(1 downto 0);
+        trig            : in    std_logic_vector(1 downto 0);
 
         -- Serial Console
         avr_RxD         : in     std_logic;
         avr_TxD         : out    std_logic;
 
-        -- GODIL Switches
-        sw1              : in    std_logic;
-        nsw2             : in    std_logic;
+        -- Switches
+        sw_reset_cpu    : in    std_logic;
+        sw_reset_avr    : in    std_logic;
 
-        -- GODIL LEDs
-        led3             : out   std_logic;
-        led6             : out   std_logic;
-        led8             : out   std_logic;
+        -- LEDs
+        led_bkpt        : out   std_logic;
+        led_trig0       : out   std_logic;
+        led_trig1       : out   std_logic;
 
         -- OHO_DY1 connected to test connector
-        tmosi            : out   std_logic;
-        tdin             : out   std_logic;
-        tcclk            : out   std_logic
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
+
+        -- Test connector signals
+        test            : inout std_logic_vector(3 downto 0)
     );
 end MOS6502CpuMonCore;
 
 architecture behavioral of MOS6502CpuMonCore is
 
+    type state_type is (idle, nop0, nop1, rd, wr, exec1, exec2);
+
+    signal state  : state_type;
+
     signal cpu_clken_ss  : std_logic;
     signal Data          : std_logic_vector(7 downto 0);
+    signal Din_int       : std_logic_vector(7 downto 0);
     signal Dout_int      : std_logic_vector(7 downto 0);
     signal R_W_n_int     : std_logic;
-    signal Rd_n_int      : std_logic;
-    signal Wr_n_int      : std_logic;
+    signal Rd_n_mon      : std_logic;
+    signal Wr_n_mon      : std_logic;
+    signal Sync_mon      : std_logic;
+    signal Done_mon      : std_logic;
     signal Sync_int      : std_logic;
-    signal hold          : std_logic;
     signal Addr_int      : std_logic_vector(23 downto 0);
 
-    signal cpu_addr_us: unsigned (15 downto 0);
-    signal cpu_dout_us: unsigned (7 downto 0);
+    signal cpu_addr_us   : unsigned (15 downto 0);
+    signal cpu_dout_us   : unsigned (7 downto 0);
+    signal cpu_reset_n   : std_logic;
 
     signal Regs          : std_logic_vector(63 downto 0);
     signal Regs1         : std_logic_vector(255 downto 0);
     signal last_PC       : std_logic_vector(15 downto 0);
     signal SS_Single     : std_logic;
     signal SS_Step       : std_logic;
+    signal SS_Step_held  : std_logic;
     signal CountCycle    : std_logic;
-    signal special       : std_logic_vector(1 downto 0);
+    signal int_ctrl      : std_logic_vector(7 downto 0);
 
     signal memory_rd     : std_logic;
     signal memory_rd1    : std_logic;
     signal memory_wr     : std_logic;
     signal memory_wr1    : std_logic;
     signal memory_addr   : std_logic_vector(15 downto 0);
-    signal memory_addr1  : std_logic_vector(15 downto 0);
     signal memory_dout   : std_logic_vector(7 downto 0);
     signal memory_din    : std_logic_vector(7 downto 0);
     signal memory_done   : std_logic;
 
-    signal NMI_n_masked  : std_logic;
+
     signal IRQ_n_masked  : std_logic;
+    signal NMI_n_masked  : std_logic;
+    signal Res_n_masked  : std_logic;
+    signal SO_n_masked   : std_logic;
+
+    signal exec          : std_logic;
+    signal exec_held     : std_logic;
+    signal op3           : std_logic;
 
 begin
 
     mon : entity work.BusMonCore
     generic map (
-        avr_data_mem_size => avr_data_mem_size,
+        num_comparators   => num_comparators,
         avr_prog_mem_size => avr_prog_mem_size
     )
     port map (
@@ -123,27 +139,23 @@ begin
         cpu_clken    => cpu_clken,
         Addr         => Addr_int(15 downto 0),
         Data         => Data,
-        Rd_n         => Rd_n_int,
-        Wr_n         => Wr_n_int,
+        Rd_n         => Rd_n_mon,
+        Wr_n         => Wr_n_mon,
         RdIO_n       => '1',
         WrIO_n       => '1',
-        Sync         => Sync_int,
+        Sync         => Sync_mon,
         Rdy          => open,
-        nRSTin       => Res_n_in,
-        nRSTout      => Res_n_out,
+        nRSTin       => Res_n_masked,
+        nRSTout      => cpu_reset_n,
         CountCycle   => CountCycle,
         trig         => trig,
-        lcd_rs       => open,
-        lcd_rw       => open,
-        lcd_e        => open,
-        lcd_db       => open,
         avr_RxD      => avr_RxD,
         avr_TxD      => avr_TxD,
-        sw1          => sw1,
-        nsw2         => nsw2,
-        led3         => led3,
-        led6         => led6,
-        led8         => led8,
+        sw_reset_cpu => sw_reset_cpu,
+        sw_reset_avr => sw_reset_avr,
+        led_bkpt     => led_bkpt,
+        led_trig0    => led_trig0,
+        led_trig1    => led_trig1,
         tmosi        => tmosi,
         tdin         => tdin,
         tcclk        => tcclk,
@@ -152,19 +164,39 @@ begin
         WrMemOut     => memory_wr,
         RdIOOut      => open,
         WrIOOut      => open,
+        ExecOut      => exec,
         AddrOut      => memory_addr,
         DataOut      => memory_dout,
         DataIn       => memory_din,
-        Done         => memory_done,
-        Special      => special,
+        Done         => Done_mon,
+        int_ctrl     => int_ctrl,
         SS_Step      => SS_Step,
         SS_Single    => SS_Single
     );
-    Wr_n_int <= R_W_n_int;
-    Rd_n_int <= not R_W_n_int;
+    Wr_n_mon <= Rdy and R_W_n_int;
+    Rd_n_mon <= Rdy and not R_W_n_int;
+    Sync_mon <= Rdy and Sync_int;
+    Done_mon <= Rdy and memory_done;
+
     Data <= Din when R_W_n_int = '1' else Dout_int;
-    NMI_n_masked <= NMI_n or special(1);
-    IRQ_n_masked <= IRQ_n or special(0);
+
+    -- The two int control bits work as follows
+    -- 00 -> IRQ_n                (enabled)
+    -- 01 -> IRQ_n or SS_Single   (enabled when free-running)
+    -- 10 -> 0                    (forced)
+    -- 11 -> 1                    (disabled)
+
+    IRQ_n_masked <= int_ctrl(0) when int_ctrl(1) = '1' else
+                    IRQ_n or (int_ctrl(0) and SS_single);
+
+    NMI_n_masked <= int_ctrl(2) when int_ctrl(3) = '1' else
+                    NMI_n or (int_ctrl(2) and SS_single);
+
+    Res_n_masked <= int_ctrl(4) when int_ctrl(5) = '1' else
+                     Res_n or (int_ctrl(4) and SS_single);
+
+    SO_n_masked  <= int_ctrl(6) when int_ctrl(7) = '1' else
+                    SO_n or (int_ctrl(6) and SS_single);
 
     -- The CPU is slightly pipelined and the register update of the last
     -- instruction overlaps with the opcode fetch of the next instruction.
@@ -181,8 +213,8 @@ begin
     last_pc_gen : process(cpu_clk)
     begin
         if rising_edge(cpu_clk) then
-            if (cpu_clken = '1') then
-                if (hold = '0') then
+            if cpu_clken = '1' then
+                if state = idle then
                     last_PC <= Regs(63 downto 48);
                 end if;
             end if;
@@ -193,14 +225,14 @@ begin
     Regs1( 63 downto 48) <= last_PC;
     Regs1(255 downto 64) <= (others => '0');
 
-    cpu_clken_ss <= (not hold) and cpu_clken;
+    cpu_clken_ss <= '1' when Rdy = '1' and (state = idle or state = exec1 or state = exec2) and cpu_clken = '1' else '0';
 
     GenT65Core: if UseT65Core generate
         inst_t65: entity work.T65 port map (
             mode            => "00",
             Abort_n         => '1',
-            SO_n            => SO_n,
-            Res_n           => Res_n_in,
+            SO_n            => SO_n_masked,
+            Res_n           => cpu_reset_n,
             Enable          => cpu_clken_ss,
             Clk             => cpu_clk,
             Rdy             => '1',
@@ -209,7 +241,7 @@ begin
             R_W_n           => R_W_n_int,
             Sync            => Sync_int,
             A               => Addr_int,
-            DI              => Din,
+            DI              => Din_int,
             DO              => Dout_int,
             Regs            => Regs
         );
@@ -217,12 +249,12 @@ begin
 
     GenAlanDCore: if UseAlanDCore generate
         inst_r65c02: entity work.r65c02 port map (
-            reset    => Res_n_in,
+            reset    => cpu_reset_n,
             clk      => cpu_clk,
             enable   => cpu_clken_ss,
             nmi_n    => NMI_n_masked,
             irq_n    => IRQ_n_masked,
-            di       => unsigned(Din),
+            di       => unsigned(Din_int),
             do       => cpu_dout_us,
             addr     => cpu_addr_us,
             nwe      => R_W_n_int,
@@ -234,49 +266,138 @@ begin
         Addr_int(15 downto 0) <= std_logic_vector(cpu_addr_us);
     end generate;
 
+-- 00 IMP, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
+-- 10 BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMPA,  IMP,  ABS,    ABSX,  ABSX, IMP,
+-- 20 ABS, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
+-- 30 BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMPA,  IMP,  ABSX,   ABSX,  ABSX, IMP,
+-- 40 IMP, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
+-- 50 BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP,
+-- 60 IMP, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  IND16,  ABS,   ABS,  IMP,
+-- 70 BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  IND1X,  ABSX,  ABSX, IMP,
+-- 80 BRA, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+-- 90 BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPY,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP,
+-- A0 IMM, INDX,  IMM, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+-- B0 BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPY,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABSX,   ABSX,  ABSY, IMP,
+-- C0 IMM, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+-- D0 BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP,
+-- E0 IMM, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMP,   IMP,  ABS,    ABS,   ABS,  IMP,
+-- F0 BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP
 
-    -- This block generates a hold signal that acts as the inverse of a clock enable
-    -- for the CPU. See comments above for why this is a cycle delayed a cycle.
-    hold_gen : process(cpu_clk)
+    -- Detect forced opcodes that are 3 bytes long
+    op3 <= '1' when memory_dout(7 downto 0) = "00100000" else
+           '1' when memory_dout(4 downto 0) =    "11011" else
+           '1' when memory_dout(3 downto 0) =     "1100" else
+           '1' when memory_dout(3 downto 0) =     "1101" else
+           '1' when memory_dout(3 downto 0) =     "1110" else
+           '0';
+
+    Din_int <= memory_dout( 7 downto 0) when state = idle and Sync_int = '1' and exec_held = '1' else
+               memory_addr( 7 downto 0) when state = exec1 else
+               memory_addr(15 downto 8) when state = exec2 else
+                                   Din;
+
+    men_access_machine : process(cpu_clk, cpu_reset_n)
     begin
-        if rising_edge(cpu_clk) then
-            if (cpu_clken = '1') then
-                if (Sync_int = '1') then
-                    -- stop after the opcode has been fetched
-                    hold <= SS_Single;
-                elsif (SS_Step = '1') then
-                    -- start again when the single step command is issues
-                    hold <= '0';
-                end if;
+        if cpu_reset_n = '0' then
+            state <= idle;
+        elsif rising_edge(cpu_clk) then
+            -- Extend the control signals from BusMonitorCore which
+            -- only last one cycle.
+            if SS_Step = '1' then
+                SS_Step_held <= '1';
+            elsif state = idle then
+                SS_Step_held <= '0';
+            end if;
+            if memory_rd = '1' then
+                memory_rd1 <= '1';
+            elsif state = rd then
+                memory_rd1 <= '0';
+            end if;
+            if memory_wr = '1' then
+                memory_wr1 <= '1';
+            elsif state = wr then
+                memory_wr1 <= '0';
+            end if;
+            if exec = '1' then
+                exec_held <= '1';
+            elsif state = exec1 then
+                exec_held <= '0';
+            end if;
+            if cpu_clken = '1' and Rdy = '1' then
+                case state is
+                    -- idle is when the CPU is running normally
+                    when idle =>
+                        if Sync_int = '1' then
+                            if exec_held = '1' then
+                                state <= exec1;
+                            elsif SS_Single = '1' then
+                                state <= nop0;
+                            end if;
+                        end if;
+                    -- nop0 is the first state entered when the CPU is paused
+                    when nop0 =>
+                        if memory_rd1 = '1' then
+                            state <= rd;
+                        elsif memory_wr1 = '1' then
+                            state <= wr;
+                        elsif SS_Step_held = '1' or exec_held = '1' then
+                            state <= idle;
+                        else
+                            state <= nop1;
+                        end if;
+                    -- nop1 simulates a sync cycle
+                    when nop1 =>
+                        state <= nop0;
+                    -- rd is a monitor initiated read cycle
+                    when rd =>
+                        state <= nop0;
+                    -- wr is a monitor initiated write cycle
+                    when wr =>
+                        state <= nop0;
+                    -- exec1 is the LSB of a forced JMP
+                    when exec1 =>
+                        if op3 = '1' then
+                            state <= exec2;
+                        else
+                            state <= idle;
+                        end if;
+                    -- exec2 is the MSB of a forced JMP
+                    when exec2 =>
+                        state <= idle;
+                end case;
             end if;
         end if;
     end process;
 
-    -- Only count cycles when the 6809 is actually running
-    CountCycle <= not hold;
+    -- Only count cycles when the 6502 is actually running
+    -- TODO: Should this be qualified with cpu_clken and rdy?
+    CountCycle <= '1' when state = idle or state = exec1 or state = exec2 else '0';
 
-    -- this block delays memory_rd, memory_wr, memory_addr until the start of the next cpu clk cycle
-    -- necessary because the cpu mon block is clocked of the opposite edge of the clock
-    -- this allows a full cpu clk cycle for cpu mon reads and writes
-    mem_gen : process(cpu_clk)
-    begin
-        if rising_edge(cpu_clk) then
-            if (cpu_clken = '1') then
-                memory_rd1   <= memory_rd;
-                memory_wr1   <= memory_wr;
-                memory_addr1 <= memory_addr;
-            end if;
-        end if;
-    end process;
+    R_W_n <= R_W_n_int when state = idle else
+             '0'       when state = wr   else
+             '1';
 
-    R_W_n <= '1' when memory_rd1 = '1' else '0' when memory_wr1 = '1' else R_W_n_int;
-    Addr <= memory_addr1 when (memory_rd1 = '1' or memory_wr1 = '1') else Addr_int(15 downto 0);
-    Sync <= Sync_int;
+    Addr <= Addr_int(15 downto 0) when state = idle else
+            memory_addr when state = rd or state = wr else
+            (others => '0');
 
-    Dout   <= memory_dout when memory_wr1 = '1' else Dout_int;
+    Sync <= Sync_int when state = idle else
+            '1'      when state = nop1 else
+            '0';
 
-    memory_done <= memory_rd1 or memory_wr1;
+    Dout   <= Dout_int when state = idle else
+              memory_dout;
+
+    -- Data is captured by the bus monitor on the rising edge of cpu_clk
+    -- that sees done = 1.
+    memory_done <= '1' when state = rd or state = wr or (op3 = '0' and state = exec1) or state = exec2 else '0';
 
     memory_din <= Din;
 
+    -- Test outputs
+    test(0) <= SS_Single;     -- GODIL J5 pin 1 (46)
+    test(1) <= 'Z';           -- GODIL J5 pin 2 (47)
+    test(2) <= 'Z';           -- GODIL J5 pin 3 (48)
+    test(3) <= 'Z';           -- GODIL J5 pin 4 (56)
+
 end behavioral;

src/MOS6502CpuMonGODIL.vhd

@@ -0,0 +1,144 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : MOS6502CpuMonGODIL.vhd
+-- /___/   /\     Timestamp : 03/11/2019
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: MOS6502CpuMonGODIL
+--Device: XC3S250E and XC3S500E
+--
+-- Note: in 65C02 mode, BE, ML_n and VP_n are not implemented
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MOS6502CpuMonGODIL is
+   generic (
+       UseT65Core        : boolean := true;
+       UseAlanDCore      : boolean := false;
+       num_comparators   : integer := 8;
+       avr_prog_mem_size : integer := 8 * 1024
+       );
+    port (
+        clock49          : in    std_logic;
+
+        -- 6502 Signals
+        Phi0             : in    std_logic;
+        Phi1             : out   std_logic;
+        Phi2             : out   std_logic;
+        IRQ_n            : in    std_logic;
+        NMI_n            : in    std_logic;
+        Sync             : out   std_logic;
+        Addr             : out   std_logic_vector(15 downto 0);
+        R_W_n            : out   std_logic;
+        Data             : inout std_logic_vector(7 downto 0);
+        SO_n             : in    std_logic;
+        Res_n            : in    std_logic;
+        Rdy              : in    std_logic;
+
+        -- External trigger inputs
+        trig             : in    std_logic_vector(1 downto 0);
+
+        -- Jumpers
+        fakeTube_n       : in     std_logic;
+
+        -- Serial Console
+        avr_RxD          : in    std_logic;
+        avr_TxD          : out   std_logic;
+
+        -- Switches
+        sw1              : in   std_logic;
+        sw2              : in   std_logic;
+
+        -- LEDs
+        led3             : out  std_logic;
+        led6             : out  std_logic;
+        led8             : out  std_logic;
+
+        -- OHO_DY1 LED display
+        tmosi            : out  std_logic;
+        tdin             : out  std_logic;
+        tcclk            : out  std_logic
+    );
+end MOS6502CpuMonGODIL;
+
+architecture behavioral of MOS6502CpuMonGODIL is
+
+    signal sw_reset_cpu : std_logic;
+    signal sw_reset_avr : std_logic;
+    signal led_bkpt     : std_logic;
+    signal led_trig0    : std_logic;
+    signal led_trig1    : std_logic;
+
+begin
+
+    sw_reset_cpu <= sw1;
+    sw_reset_avr <= not sw2;
+    led8         <= not led_bkpt;
+    led3         <= not led_trig0;
+    led6         <= not led_trig1;
+
+    wrapper : entity work.MOS6502CpuMon
+        generic map (
+            UseT65Core        => UseT65Core,
+            UseAlanDCore      => UseAlanDCore,
+            ClkMult           => 10,
+            ClkDiv            => 31,
+            ClkPer            => 20.345,
+            num_comparators   => num_comparators,
+            avr_prog_mem_size => avr_prog_mem_size
+            )
+        port map (
+            clock             => clock49,
+
+            -- 6502 Signals
+            Phi0              => Phi0,
+            Phi1              => Phi1,
+            Phi2              => Phi2,
+            IRQ_n             => IRQ_n,
+            NMI_n             => NMI_n,
+            Sync              => Sync,
+            Addr              => Addr,
+            R_W_n             => R_W_n,
+            Data              => Data,
+            SO_n              => SO_n,
+            Res_n             => Res_n,
+            Rdy               => Rdy,
+
+            -- External trigger inputs
+            trig              => trig,
+
+            -- Jumpers
+            fakeTube_n        => fakeTube_n,
+
+            -- Serial Console
+            avr_RxD           => avr_RxD,
+            avr_TxD           => avr_TxD,
+
+            -- Switches
+            sw_reset_cpu      => sw_reset_cpu,
+            sw_reset_avr      => sw_reset_avr,
+
+            -- LEDs
+            led_bkpt          => led_bkpt,
+            led_trig0         => led_trig0,
+            led_trig1         => led_trig1,
+
+            -- OHO_DY1 LED display
+            tmosi            => tmosi,
+            tdin             => tdin,
+            tcclk            => tcclk
+            );
+
+
+end behavioral;

src/MOS6502CpuMonLX9.vhd

@@ -0,0 +1,144 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : MOS6502CpuMonLX9.vhd
+-- /___/   /\     Timestamp : 03/11/2019
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: MOS6502CpuMonLX9
+--Device: XC6SLX9
+--
+-- Note: in 65C02 mode, BE, ML_n and VP_n are not implemented
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity MOS6502CpuMonLX9 is
+   generic (
+       UseT65Core        : boolean := true;
+       UseAlanDCore      : boolean := false;
+       num_comparators   : integer := 8;
+       avr_prog_mem_size : integer := 8 * 1024
+       );
+    port (
+        clock            : in    std_logic;
+
+        -- 6502 Signals
+        Phi0             : in    std_logic;
+        Phi1             : out   std_logic;
+        Phi2             : out   std_logic;
+        IRQ_n            : in    std_logic;
+        NMI_n            : in    std_logic;
+        Sync             : out   std_logic;
+        Addr             : out   std_logic_vector(15 downto 0);
+        R_W_n            : out   std_logic;
+        Data             : inout std_logic_vector(7 downto 0);
+        SO_n             : in    std_logic;
+        Res_n            : in    std_logic;
+        Rdy              : in    std_logic;
+
+        -- External trigger inputs
+        trig             : in    std_logic_vector(1 downto 0);
+
+        -- Jumpers
+        fakeTube_n       : in     std_logic;
+
+        -- Serial Console
+        avr_RxD          : in    std_logic;
+        avr_TxD          : out   std_logic;
+
+        -- Switches
+        sw1              : in   std_logic;
+        sw2              : in   std_logic;
+
+        -- LEDs
+        led3             : out  std_logic;
+        led6             : out  std_logic;
+        led8             : out  std_logic;
+
+        -- OHO_DY1 LED display
+        tmosi            : out  std_logic;
+        tdin             : out  std_logic;
+        tcclk            : out  std_logic
+    );
+end MOS6502CpuMonLX9;
+
+architecture behavioral of MOS6502CpuMonLX9 is
+
+    signal sw_reset_cpu : std_logic;
+    signal sw_reset_avr : std_logic;
+    signal led_bkpt     : std_logic;
+    signal led_trig0    : std_logic;
+    signal led_trig1    : std_logic;
+
+begin
+
+    sw_reset_cpu <= sw1;
+    sw_reset_avr <= sw2;
+    led8         <= led_bkpt;
+    led3         <= led_trig0;
+    led6         <= led_trig1;
+
+    wrapper : entity work.MOS6502CpuMon
+        generic map (
+            UseT65Core        => UseT65Core,
+            UseAlanDCore      => UseAlanDCore,
+            ClkMult           => 8,
+            ClkDiv            => 25,
+            ClkPer            => 20.000,
+            num_comparators   => num_comparators,
+            avr_prog_mem_size => avr_prog_mem_size
+            )
+        port map (
+            clock             => clock,
+
+            -- 6502 Signals
+            Phi0              => Phi0,
+            Phi1              => Phi1,
+            Phi2              => Phi2,
+            IRQ_n             => IRQ_n,
+            NMI_n             => NMI_n,
+            Sync              => Sync,
+            Addr              => Addr,
+            R_W_n             => R_W_n,
+            Data              => Data,
+            SO_n              => SO_n,
+            Res_n             => Res_n,
+            Rdy               => Rdy,
+
+            -- External trigger inputs
+            trig              => trig,
+
+            -- Jumpers
+            fakeTube_n        => fakeTube_n,
+
+            -- Serial Console
+            avr_RxD           => avr_RxD,
+            avr_TxD           => avr_TxD,
+
+            -- Switches
+            sw_reset_cpu      => sw_reset_cpu,
+            sw_reset_avr      => sw_reset_avr,
+
+            -- LEDs
+            led_bkpt          => led_bkpt,
+            led_trig0         => led_trig0,
+            led_trig1         => led_trig1,
+
+            -- OHO_DY1 LED display
+            tmosi            => tmosi,
+            tdin             => tdin,
+            tcclk            => tcclk
+            );
+
+
+end behavioral;

src/MultiBootLoader.v

@@ -0,0 +1,335 @@
+module MultiBootLoader
+  (
+   input       clock,
+   input       mode,
+   input [3:0] id,
+   output      led1, // red
+   output      led2, // trig 1
+   output      led3, // trig 2
+   output      ld1,
+   output      ld2,
+   output      ld3,
+   output      ld4,
+   output      ld5,
+   output      ld6,
+   output      ld7,
+   output      ld8
+   );
+
+   reg [1:0]   clk;
+
+   reg [15:0]  icap_din;
+   reg         icap_ce;
+   reg         icap_wr;
+
+   reg [15:0]  ff_icap_din_reversed;
+   reg         ff_icap_ce;
+   reg         ff_icap_wr;
+
+   reg [15:0]  MBT_REBOOT = 16'h0000;
+
+   reg [24:0]  counter;
+
+   ICAP_SPARTAN6 ICAP_SPARTAN6_inst
+     (
+      .BUSY      (),                      // Busy output
+      .O         (),                      // 16-bit data output
+      .CE        (ff_icap_ce),            // Clock enable input
+      .CLK       (clk[0]),                // Clock input
+      .I         (ff_icap_din_reversed),  // 16-bit data input
+      .WRITE     (ff_icap_wr)             // Write input
+      );
+
+
+   //  -------------------------------------------------
+   //  --  State Machine for ICAP_SPARTAN6 MultiBoot  --
+   //  --   sequence.                                 --
+   //  -------------------------------------------------
+
+
+   parameter
+     IDLE     = 0,
+     SYNC_H   = 1,
+     SYNC_L   = 2,
+
+     CWD_H    = 3,
+     CWD_L    = 4,
+
+     GEN1_H   = 5,
+     GEN1_L   = 6,
+
+     GEN2_H   = 7,
+     GEN2_L   = 8,
+
+     GEN3_H   = 9,
+     GEN3_L   = 10,
+
+     GEN4_H   = 11,
+     GEN4_L   = 12,
+
+     GEN5_H   = 13,
+     GEN5_L   = 14,
+
+     NUL_H    = 15,
+     NUL_L    = 16,
+
+     MOD_H    = 17,
+     MOD_L    = 18,
+
+     HCO_H    = 19,
+     HCO_L    = 20,
+
+     RBT_H    = 21,
+     RBT_L    = 22,
+
+     NOOP_0   = 23,
+     NOOP_1   = 24,
+     NOOP_2   = 25,
+     NOOP_3   = 26;
+
+
+   reg [4:0]   state = IDLE;
+   reg [4:0]   next_state;
+
+   always @(MBT_REBOOT or state or id or mode)
+     begin: COMB
+
+        case (state)
+
+          IDLE:
+            begin
+               if (MBT_REBOOT==16'hffff)
+                 begin
+                    next_state  = SYNC_H;
+                    icap_ce     = 0;
+                    icap_wr     = 0;
+                    icap_din    = 16'hAA99;  // Sync word part 1
+                 end
+               else
+                 begin
+                    next_state  = IDLE;
+                    icap_ce     = 1;
+                    icap_wr     = 1;
+                    icap_din    = 16'hFFFF;  // Null data
+                 end
+            end
+
+          SYNC_H:
+            begin
+               next_state  = SYNC_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h5566;    // Sync word part 2
+            end
+
+          SYNC_L:
+            begin
+               next_state  = GEN1_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h3261;    //  Write to GENERAL_1 Register....
+            end
+
+          GEN1_H:
+            begin
+               next_state  = GEN1_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+
+               // Loader          - 0300-0000
+               // Unknown Adapter - 0305-4000
+               // 6502            - 030A-8000 - mode 1 id 1110
+               // Z80             - 030F-C000 - mode x id 1101
+               // 65C02           - 0315-0000 - mode 0 id 1110 (future)
+               // 6809            - 031A-4000 - mode x id 1100 (future)
+
+               case ({mode, id})
+                 5'b11110: icap_din    = 16'h8000; // 6502
+                 5'b11101: icap_din    = 16'hC000; // Z80 (mode = 1)
+                 5'b01101: icap_din    = 16'hC000; // Z80 (mode = 0)
+                 5'b01110: icap_din    = 16'h0000; // 65C02
+                 5'b11100: icap_din    = 16'h4000; // 6809 (mode = 1)
+                 5'b01100: icap_din    = 16'h4000; // 6809 (mode = 0)
+                 default:  icap_din    = 16'h4000; // Unknown Adapter
+               endcase
+
+            end
+
+          GEN1_L:
+            begin
+               next_state  = GEN2_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h3281;    //  Write to GENERAL_2 Register....
+            end
+
+          GEN2_H:
+            begin
+               next_state  = GEN2_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+
+               case ({mode, id})
+                 5'b11110: icap_din    = 16'h030A; // 6502
+                 5'b11101: icap_din    = 16'h030F; // Z80 (mode = 1)
+                 5'b01101: icap_din    = 16'h030F; // Z80 (mode = 0)
+                 5'b01110: icap_din    = 16'h0315; // 65C02
+                 5'b11100: icap_din    = 16'h031A; // 6809 (mode = 1)
+                 5'b01100: icap_din    = 16'h031A; // 6809 (mode = 0)
+                 default:  icap_din    = 16'h0305; // Unknown Adapter
+               endcase
+
+            end
+
+          GEN2_L:
+            begin
+               next_state  = RBT_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h30A1;      //  Write to Command Register....
+            end
+
+          RBT_H:
+            begin
+               next_state  = RBT_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h000E;      // REBOOT Command issued....  value = 0x000E
+            end
+
+          RBT_L:
+            begin
+               next_state  = NOOP_0;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    //  NOOP
+            end
+
+          NOOP_0:
+            begin
+               next_state  = NOOP_1;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    // NOOP
+            end
+
+          NOOP_1:
+            begin
+               next_state  = NOOP_2;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    // NOOP
+            end
+
+          NOOP_2:
+            begin
+               next_state  = NOOP_3;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    // NOOP
+            end
+
+          NOOP_3:
+            begin
+               next_state  = IDLE;
+               icap_ce     = 1;
+               icap_wr     = 1;
+               icap_din    = 16'h1111;    // NULL value
+            end
+
+          default:
+            begin
+               next_state  = IDLE;
+               icap_ce     = 1;
+               icap_wr     = 1;
+               icap_din    = 16'h1111;    //  16'h1111"
+            end
+
+        endcase
+     end
+
+   // Clock ICAP_SPARTAN6 and the state machine with clocks that are 90deg phase apart.
+   //
+   // This is an attempt to cure some reconfiguration unreliability.
+   //
+   // The problem is that ICAP_SPARTAN2 isn't treated by the Xilinx tools as a synchronous
+   // component, so when clocked off the same clock there can be timing issues.
+   //
+   // The below clocking patten runs the clock at 8MHz (half what it was before).
+   //
+   // It ensures there is plenty of setup and hold time margin for signals passing
+   // between ICAP_SPARTAN6 and the state machine, regardless of which clk edge is used
+   // ICAP_SPARTAN6.
+   //
+   // See this link for some related discussion:
+   // https://forums.xilinx.com/t5/Spartan-Family-FPGAs/20Mhz-limitation-for-ICAP-SPARTAN6/td-p/238060
+   //
+   // NOTE: I'm hedging here, as this bug is quite difficult to reproduce, and changing almost anything
+   // (e.g. connecting state to the test pins) causes the problem to go away.
+   //
+   // At worst this change should be harmless!
+   //
+   // Dave Banks - 18/07/2017
+
+   always@(posedge clock) begin
+      if (clk == 2'b00)
+        clk <= 2'b10;
+      else if (clk == 2'b10)
+        clk <= 2'b11;
+      else if (clk == 2'b11)
+        clk <= 2'b01;
+      else
+        clk <= 2'b00;
+   end
+
+   // Give a bit of delay before starting the state machine
+   always @(posedge clk[1]) begin
+      if (MBT_REBOOT == 16'hffff) begin
+         state <= next_state;
+      end else begin
+         MBT_REBOOT <= MBT_REBOOT + 1'b1;
+         state <= IDLE;
+      end
+   end
+
+
+   always @(posedge clk[1]) begin:   ICAP_FF
+      // need to reverse bits to ICAP module since D0 bit is read first
+      ff_icap_din_reversed[0]  <= icap_din[7];
+      ff_icap_din_reversed[1]  <= icap_din[6];
+      ff_icap_din_reversed[2]  <= icap_din[5];
+      ff_icap_din_reversed[3]  <= icap_din[4];
+      ff_icap_din_reversed[4]  <= icap_din[3];
+      ff_icap_din_reversed[5]  <= icap_din[2];
+      ff_icap_din_reversed[6]  <= icap_din[1];
+      ff_icap_din_reversed[7]  <= icap_din[0];
+      ff_icap_din_reversed[8]  <= icap_din[15];
+      ff_icap_din_reversed[9]  <= icap_din[14];
+      ff_icap_din_reversed[10] <= icap_din[13];
+      ff_icap_din_reversed[11] <= icap_din[12];
+      ff_icap_din_reversed[12] <= icap_din[11];
+      ff_icap_din_reversed[13] <= icap_din[10];
+      ff_icap_din_reversed[14] <= icap_din[9];
+      ff_icap_din_reversed[15] <= icap_din[8];
+      ff_icap_ce  <= icap_ce;
+      ff_icap_wr  <= icap_wr;
+   end
+
+   always@(posedge clock) begin
+      counter <= counter + 1'b1;
+   end
+
+   assign led1 = 1'b1;
+   assign led2 = 1'b0;
+   assign led3 = 1'b0;
+
+   assign ld1 = counter[24];
+   assign ld2 = ~counter[24];
+   assign ld3 = 1'b0;
+   assign ld4 = state[4];
+   assign ld5 = state[3];
+   assign ld6 = state[2];
+   assign ld7 = state[1];
+   assign ld8 = state[0];
+
+endmodule

src/T6502/T65.vhd

@@ -1,32 +1,65 @@
 -- ****
 -- T65(b) core. In an effort to merge and maintain bug fixes ....
 --
+-- Ver 313 WoS January 2015
+--   Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in
+--   Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D
+--   This is just a starting point to go for optimizations and detailed fixes (the Lorenz test can't find)
+--
+-- Ver 312 WoS January 2015
+--   Undoc opcode timing fixes for $B3 (LAX iy) and $BB (LAS ay)
+--   Added comments in MCode section to find handling of individual opcodes more easily
+--   All "basic" Lorenz instruction test (individual functional checks, CPUTIMING check) work now with 
+--       actual FPGAARCADE C64 core (sources used: SVN version 1021).
+--
+-- Ver 305, 306, 307, 308, 309, 310, 311 WoS January 2015
+--   Undoc opcode fixes (now all Lorenz test on instruction functionality working, except timing issues on $B3 and $BB):
+--     SAX opcode
+--     SHA opcode
+--     SHX opcode
+--     SHY opcode
+--     SHS opcode
+--     LAS opcode
+--     alternate SBC opcode
+--     fixed NOP with immediate param (caused Lorenz trap test to fail)
+--     IRQ and NMI timing fixes (in conjuction with branches)
+--
+-- Ver 304 WoS December 2014
+--   Undoc opcode fixes:
+--     ARR opcode
+--     ANE/XAA opcode
+--   Corrected issue with NMI/IRQ prio (when asserted the same time)
+--
 -- Ver 303 ost(ML) July 2014
 --   (Sorry for some scratchpad comments that may make little sense)
 --   Mods and some 6502 undocumented instructions.
---
--- Not correct opcodes acc. to Lorenz tests (incomplete list):
+--   Not correct opcodes acc. to Lorenz tests (incomplete list):
 --     NOPN    (nop)
 --     NOPZX   (nop + byte 172)
 --     NOPAX   (nop + word da  ...  da:  byte 0)
 --     ASOZ    (byte $07 + byte 172)
 --
--- Wolfgang April 2014
--- Ver 303 Bugfixes for NMI from foft
--- Ver 302 Bugfix for BRK command
--- Wolfgang January 2014
--- Ver 301 more merging
--- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
+-- Ver 303,302 WoS April 2014
+--     Bugfixes for NMI from foft
+--     Bugfix for BRK command (and its special flag)
 --
+-- Ver 300,301 WoS January 2014
+--     More merging
+--     Bugfixes by ehenciak added, started tidyup *bust*
+--
+-- MikeJ March 2005
+--      Latest version from www.fpgaarcade.com (original www.opencores.org)
 -- ****
 --
 -- 65xx compatible microprocessor core
 --
--- Version : 0246
+-- FPGAARCADE SVN: $Id: T65.vhd 1347 2015-05-27 20:07:34Z wolfgang.scherr $
 --
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+-- Copyright (c) 2002...2015
+--               Daniel Wallner (jesus <at> opencores <dot> org)
+--               Mike Johnson   (mikej <at> fpgaarcade <dot> com)
+--               Wolfgang Scherr (WoS <at> pin4 <dot> at>
+--               Morten Leikvoll ()
 --
 -- All rights reserved
 --
@@ -56,22 +89,37 @@
 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 -- POSSIBILITY OF SUCH DAMAGE.
 --
--- Please report bugs to the author, but before you do so, please
+-- Please report bugs to the author(s), but before you do so, please
 -- make sure that this is not a derivative work and that
 -- you have the latest version of this file.
 --
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t65/
+-- ----- IMPORTANT NOTES -----
 --
--- Limitations :
+-- Limitations:
+--   65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes)
+--      65C02 supported : inc, dec, phx, plx, phy, ply
+--      65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
+--   Some interface signals behave incorrect
+--   NMI interrupt handling not nice, needs further rework (to cycle-based encoding).
 --
--- 65C02 and 65C816 modes are incomplete
--- Undocumented instructions are not supported
--- Some interface signals behaves incorrect
+-- Usage:
+--   The enable signal allows clock gating / throttling without using the ready signal.
+--   Set it to constant '1' when using the Clk input as the CPU clock directly.
 --
--- File history :
+--   TAKE CARE you route the DO signal back to the DI signal while R_W_n='0',
+--   otherwise some undocumented opcodes won't work correctly.
+--   EXAMPLE:
+--      CPU : entity work.T65
+--          port map (
+--              R_W_n   => cpu_rwn_s,
+--              [....all other ports....]
+--              DI      => cpu_din_s,
+--              DO      => cpu_dout_s
+--          );
+--      cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else 
+--                   [....other sources from peripherals and memories...]
 --
---      0246 : First release
+-- ----- IMPORTANT NOTES -----
 --
 
 library IEEE;
@@ -79,8 +127,6 @@ library IEEE;
   use IEEE.numeric_std.all;
   use work.T65_Pack.all;
 
--- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
--- the ready signal to limit the CPU.
 entity T65 is
   port(
     Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
@@ -102,17 +148,18 @@ entity T65 is
     VDA     : out std_logic;
     VPA     : out std_logic;
     A       : out std_logic_vector(23 downto 0);
-    DI      : in  std_logic_vector(7 downto 0);--NOTE:Make sure DI equals DO when writing. This is important for DCP/DCM undoc instruction. TODO:convert to inout
+    DI      : in  std_logic_vector(7 downto 0);
     DO      : out std_logic_vector(7 downto 0);
     -- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
-    Regs    : out std_logic_vector(63 downto 0)
+    Regs    : out std_logic_vector(63 downto 0);
+    DEBUG   : out T_t65_dbg
   );
 end T65;
 
 architecture rtl of T65 is
 
   -- Registers
-  signal ABC, X, Y, D       : std_logic_vector(15 downto 0);
+  signal ABC, X, Y          : std_logic_vector(15 downto 0);
   signal P, AD, DL          : std_logic_vector(7 downto 0) :=  x"00";
   signal PwithB             : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack
   signal BAH                : std_logic_vector(7 downto 0);
@@ -149,6 +196,7 @@ architecture rtl of T65 is
   signal BusA               : std_logic_vector(7 downto 0);
   signal BusA_r             : std_logic_vector(7 downto 0);
   signal BusB               : std_logic_vector(7 downto 0);
+  signal BusB_r             : std_logic_vector(7 downto 0);
   signal ALU_Q              : std_logic_vector(7 downto 0);
   signal P_Out              : std_logic_vector(7 downto 0);
 
@@ -178,37 +226,39 @@ architecture rtl of T65 is
   signal LDBAH              : std_logic;
   signal SaveP              : std_logic;
   signal Write              : std_logic;
-  signal ALUmore            : std_logic;
 
-  signal really_rdy         : std_logic;
-  signal R_W_n_i            : std_logic;
-  signal R_W_n_i_d          : std_logic;
-  
-  signal NMIActClear        : std_logic; -- MWW hack
+  signal Res_n_i        : std_logic;
+  signal Res_n_d        : std_logic;
+
+  signal really_rdy     : std_logic;
+  signal WRn_i          : std_logic;
+
+  signal NMI_entered    : std_logic;
 
 begin
-  -- workaround for ready-handling
-  -- ehenciak : Drive R_W_n_i off chip.
-  R_W_n      <= R_W_n_i;
-
-  -- ehenciak : gate Rdy with read/write to make an "OK, it's
-  --            really OK to stop the processor now if Rdy is
-  --            deasserted" signal
-  really_rdy <= Rdy or not(R_W_n_i);
-  ----
-
+  -- gate Rdy with read/write to make an "OK, it's really OK to stop the processor 
+  really_rdy <= Rdy or not(WRn_i);
   Sync <= '1' when MCycle = "000" else '0';
   EF <= EF_i;
   MF <= MF_i;
   XF <= XF_i;
+  R_W_n <= WRn_i;
   ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
   VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
-  VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0';            -- Incorrect !!!!!!!!!!!!
-  VPA <= '1' when Jump(1) = '0' else '0';                     -- Incorrect !!!!!!!!!!!!
+  VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0';
+  VPA <= '1' when Jump(1) = '0' else '0';
 
-    Regs <= std_logic_vector(PC) & std_logic_vector(S)& P & Y(7 downto 0) & X(7 downto 0) & ABC(7 downto 0);
+  -- debugging signals
+  DEBUG.I <= IR;
+  DEBUG.A <= ABC(7 downto 0);
+  DEBUG.X <= X(7 downto 0);
+  DEBUG.Y <= Y(7 downto 0);
+  DEBUG.S <= std_logic_vector(S(7 downto 0));
+  DEBUG.P <= P;
 
-  mcode : T65_MCode
+  Regs <= std_logic_vector(PC) & std_logic_vector(S)& P & Y(7 downto 0) & X(7 downto 0) & ABC(7 downto 0);
+
+  mcode : entity work.T65_MCode
     port map(
 --inputs
       Mode        => Mode_r,
@@ -240,11 +290,10 @@ begin
       LDBAL       => LDBAL,
       LDBAH       => LDBAH,
       SaveP       => SaveP,
-      ALUmore     => ALUmore,
       Write       => Write
       );
 
-  alu : T65_ALU
+  alu : entity work.T65_ALU
     port map(
       Mode => Mode_r,
       Op => ALU_Op_r,
@@ -255,14 +304,25 @@ begin
       Q => ALU_Q
       );
 
-
+  -- the 65xx design requires at least two clock cycles before
+  -- starting its reset sequence (according to datasheet)
   process (Res_n, Clk)
   begin
     if Res_n = '0' then
+      Res_n_i <= '0';
+      Res_n_d <= '0';
+    elsif Clk'event and Clk = '1' then
+      Res_n_i <= Res_n_d;
+      Res_n_d <= '1';
+    end if;
+  end process;
+
+  process (Res_n_i, Clk)
+  begin
+    if Res_n_i = '0' then
       PC <= (others => '0');  -- Program Counter
       IR <= "00000000";
-      S <= (others => '0');       -- Dummy !!!!!!!!!!!!!!!!!!!!!
-      D <= (others => '0');
+      S <= (others => '0');       -- Dummy
       PBR <= (others => '0');
       DBR <= (others => '0');
 
@@ -271,7 +331,7 @@ begin
       Write_Data_r <= Write_Data_DL;
       Set_Addr_To_r <= Set_Addr_To_PBR;
 
-      R_W_n_i <= '1';
+      WRn_i <= '1';
       EF_i <= '1';
       MF_i <= '1';
       XF_i <= '1';
@@ -279,9 +339,8 @@ begin
     elsif Clk'event and Clk = '1' then  
       if (Enable = '1') then
         if (really_rdy = '1') then
-          R_W_n_i <= not Write or RstCycle;
+          WRn_i <= not Write or RstCycle;
 
-          D <= (others => '1');   -- Dummy
           PBR <= (others => '1'); -- Dummy
           DBR <= (others => '1'); -- Dummy
           EF_i <= '0';    -- Dummy
@@ -300,6 +359,10 @@ begin
             else
               IR <= DI;
             end if;
+
+            if LDS = '1' then -- LAS won't work properly if not limited to machine cycle 0
+              S(7 downto 0) <= unsigned(ALU_Q);
+            end if;
           end if;
 
           ALU_Op_r <= ALU_Op;
@@ -316,9 +379,6 @@ begin
           if Dec_S = '1' and RstCycle = '0' then
             S <= S - 1;
           end if;
-          if LDS = '1' then
-            S(7 downto 0) <= unsigned(ALU_Q);
-          end if;
 
           if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
             PC <= PC + 1;
@@ -329,10 +389,8 @@ begin
           case Jump is
             when "01" =>
               PC <= PC + 1;
-
             when "10" =>
               PC <= unsigned(DI & DL);
-
             when "11" =>
               if PCAdder(8) = '1' then
                 if DL(7) = '0' then
@@ -342,7 +400,6 @@ begin
                 end if;
               end if;
               PC(7 downto 0) <= PCAdder(7 downto 0);
-
             when others => null;
           end case;
         end if;
@@ -353,13 +410,13 @@ begin
   PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
          else "0" & PC(7 downto 0);
 
-  process (Res_n, Clk)
-    variable tmpP:std_logic_vector(7 downto 0);--ML:Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
+  process (Res_n_i, Clk)
+    variable tmpP:std_logic_vector(7 downto 0);--Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
   begin
-    if Res_n = '0' then
-      P <= x"00"; -- ensure we have nothing set on reset (e.g. B flag!) 
+    if Res_n_i = '0' then
+      P <= x"00"; -- ensure we have nothing set on reset
     elsif Clk'event and Clk = '1' then
-    tmpP:=P;
+      tmpP:=P;
       if (Enable = '1') then
         if (really_rdy = '1') then
           if MCycle = "000" then
@@ -373,82 +430,59 @@ begin
               Y(7 downto 0) <= ALU_Q;
             end if;
             if (LDA or LDX or LDY) = '1' then
---              P <= P_Out;-- Replaced with:
               tmpP:=P_Out;
             end if;
           end if;
           if SaveP = '1' then
---            P <= P_Out;-- Replaced with:
             tmpP:=P_Out;
           end if;
           if LDP = '1' then
---            P <= ALU_Q;-- Replaced with:     --ML:no need anymore: AND x"EF";  -- NEVER set B on RTI and PLP
             tmpP:=ALU_Q;
           end if;
           if IR(4 downto 0) = "11000" then
             case IR(7 downto 5) is
             when "000" =>--0x18(clc)
---              P(Flag_C) <= '0';-- Replaced with:
               tmpP(Flag_C) := '0';
             when "001" =>--0x38(sec)
---              P(Flag_C) <= '1';
               tmpP(Flag_C) := '1';
             when "010" =>--0x58(cli)
---              P(Flag_I) <= '0';
               tmpP(Flag_I) := '0';
             when "011" =>--0x78(sei)
---              P(Flag_I) <= '1';
               tmpP(Flag_I) := '1';
             when "101" =>--0xb8(clv)
---              P(Flag_V) <= '0';
               tmpP(Flag_V) := '0';
             when "110" =>--0xd8(cld)
---              P(Flag_D) <= '0';
               tmpP(Flag_D) := '0';
             when "111" =>--0xf8(sed)
---              P(Flag_D) <= '1';
               tmpP(Flag_D) := '1';
             when others =>
             end case;
           end if;
-          --ML:Removed change of B flag, its constant '1' in P
-          --ML:The B flag appears to be locked to '1', but when pushed to stack, the SR data on the stack has the B flag cleared on interrupts, set on BRK instr.
-          --ML:The state of the B flag on warm reset apparently is unchanged (not confirmed, please do if you know)
-          --ML:The state of the B flag on cold reset is uncertain, but my guess would be set, unless it can be used to detect cold from warm reset.
-          --Since we cant (well, won't) simulate B=0 on cold reset, we just behave as if it was constant 1.
---          P(Flag_B) <= '1';
           tmpP(Flag_B) := '1';
---          if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then -- BRK
---            P(Flag_B) <= '1';
---          elsif IR = "00001000" then -- PHP
---            P(Flag_B) <= '1';
---          else
---            P(Flag_B) <= '0';  --> not the best way, but we keep B zero except for BRK and PHP opcodes
---          end if;
-          if IR = "00000000" and MCycle = "100" and RstCycle = '0' then --and (NMICycle = '1' or IRQCycle = '1')  then
+          if IR = "00000000" and MCycle = "100" and RstCycle = '0' then
             --This should happen after P has been pushed to stack
---            P(Flag_I) <= '1';
             tmpP(Flag_I) := '1';
           end if;
           if SO_n_o = '1' and SO_n = '0' then
---            P(Flag_V) <= '1';
             tmpP(Flag_V) := '1';
           end if;
           if RstCycle = '1' then
---            P(Flag_I) <= '0';
---            P(Flag_D) <= '0';
             tmpP(Flag_I) := '1';
             tmpP(Flag_D) := '0';
           end if;
---          P(Flag_1) <= '1';
           tmpP(Flag_1) := '1';
 
           P<=tmpP;--new way
 
           SO_n_o <= SO_n;
-          IRQ_n_o <= IRQ_n;
+          if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works...
+            IRQ_n_o <= IRQ_n;
+          end if;
+        end if;
+        -- detect nmi even if not rdy
+        if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works...
+          NMI_n_o <= NMI_n;
         end if;
-        NMI_n_o <= NMI_n; -- MWW: detect nmi even if not rdy    
       end if;
     end if;
   end process;
@@ -459,24 +493,26 @@ begin
 --
 ---------------------------------------------------------------------------
 
-  process (Res_n, Clk)
+  process (Res_n_i, Clk)
   begin
-    if Res_n = '0' then
+    if Res_n_i = '0' then
       BusA_r <= (others => '0');
       BusB <= (others => '0');
+      BusB_r <= (others => '0');
       AD <= (others => '0');
       BAL <= (others => '0');
       BAH <= (others => '0');
       DL <= (others => '0');
     elsif Clk'event and Clk = '1' then
       if (Enable = '1') then
+        NMI_entered <= '0';
         if (really_rdy = '1') then
-        --if (Rdy = '1') then
           BusA_r <= BusA;
-          if ALUmore='1' then
-            BusB <= ALU_Q;
-          else
-            BusB <= DI;
+          BusB <= DI;
+
+          -- not really nice, but no better way found yet !
+          if Set_Addr_To_r = Set_Addr_To_PBR or Set_Addr_To_r = Set_Addr_To_ZPG then
+            BusB_r <= std_logic_vector(unsigned(DI(7 downto 0)) + 1); -- required for SHA
           end if;
 
           case BAAdd is
@@ -495,26 +531,25 @@ begin
           when others =>
           end case;
 
-          -- ehenciak : modified to use Y register as well (bugfix)
+          -- modified to use Y register as well
           if ADAdd = '1' then
             if (AddY = '1') then
-            AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
+              AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
             else
-            AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
+              AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
             end if;
           end if;
 
-          NMIActClear <= '0';
           if IR = "00000000" then
             BAL <= (others => '1');
             BAH <= (others => '1');
             if RstCycle = '1' then
-              BAL(2 downto 0) <= "100";          
-            elsif NMICycle = '1' then
+              BAL(2 downto 0) <= "100";
+            elsif NMICycle = '1' or (NMIAct = '1' and MCycle="100") or NMI_entered='1' then
               BAL(2 downto 0) <= "010";
-            elsif NMIAct = '1' then  -- MWW, force this to be changed by NMI, even if in midstream IRQ/brk
-              BAL(2 downto 0) <= "010";
-              NMIActClear <= '1';      
+              if MCycle="100" then
+                NMI_entered <= '1';
+              end if;
             else
               BAL(2 downto 0) <= "110";
             end if;
@@ -523,7 +558,6 @@ begin
             end if;
           end if;
 
-
           if LDDI = '1' then
             DL <= DI;
           end if;
@@ -554,16 +588,20 @@ begin
       Y(7 downto 0)                         when Set_BusA_To_Y,
       std_logic_vector(S(7 downto 0))       when Set_BusA_To_S,
       P                                     when Set_BusA_To_P,
+      ABC(7 downto 0) and DI                when Set_BusA_To_DA,
+      (ABC(7 downto 0) or x"ee") and DI     when Set_BusA_To_DAO,--ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
+      (ABC(7 downto 0) or x"ee") and DI and X(7 downto 0)    when Set_BusA_To_DAX,--XAA, ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
+      ABC(7 downto 0) and X(7 downto 0)     when Set_BusA_To_AAX,--SAX, SHA
       (others => '-')                       when Set_BusA_To_DONTCARE;--Can probably remove this
 
   with Set_Addr_To_r select
     A <=
-      "0000000000000001" & std_logic_vector(S(7 downto 0))                            when Set_Addr_To_S,
-      DBR & "00000000" & AD                                                           when Set_Addr_To_AD,
+      "0000000000000001" & std_logic_vector(S(7 downto 0))                            when Set_Addr_To_SP,
+      DBR & "00000000" & AD                                                           when Set_Addr_To_ZPG,
       "00000000" & BAH & BAL(7 downto 0)                                              when Set_Addr_To_BA,
       PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR;
 
-  --ML:This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
+  -- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
   PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
 
   with Write_Data_r select
@@ -576,6 +614,10 @@ begin
       PwithB                              when Write_Data_P,
       std_logic_vector(PC(7 downto 0))    when Write_Data_PCL,
       std_logic_vector(PC(15 downto 8))   when Write_Data_PCH,
+      ABC(7 downto 0) and X(7 downto 0)   when Write_Data_AX,
+      ABC(7 downto 0) and X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_AXB, -- no better way found yet...
+      X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_XB, -- no better way found yet...
+      Y(7 downto 0) and BusB_r(7 downto 0) when Write_Data_YB, -- no better way found yet...
       (others=>'-')                       when Write_Data_DONTCARE;--Can probably remove this
 
 
@@ -585,9 +627,9 @@ begin
 --
 -------------------------------------------------------------------------
 
-  process (Res_n, Clk)
+  process (Res_n_i, Clk)
   begin
-    if Res_n = '0' then
+    if Res_n_i = '0' then
       MCycle <= "001";
       RstCycle <= '1';
       IRQCycle <= '0';
@@ -596,31 +638,29 @@ begin
     elsif Clk'event and Clk = '1' then
       if (Enable = '1') then
         if (really_rdy = '1') then
-          if (NMIActClear = '1') then
-            NMIAct <= '0';
-          end if;
-        
           if MCycle = LCycle or Break = '1' then
             MCycle <= "000";
             RstCycle <= '0';
             IRQCycle <= '0';
             NMICycle <= '0';
-            if NMIAct = '1' then
+            if NMIAct = '1' and IR/=x"00" then -- delay NMI further if we just executed a BRK
               NMICycle <= '1';
+              NMIAct <= '0'; -- reset NMI edge detector if we start processing the NMI
             elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
               IRQCycle <= '1';
             end if;
           else
             MCycle <= std_logic_vector(unsigned(MCycle) + 1);
           end if;
-
-          if NMICycle = '1' then
-            NMIAct <= '0';
-          end if;
-        end if;        
-        if NMI_n_o = '1' and NMI_n = '0' then  -- MWW: detect nmi even if not rdy    
+        end if;
+        --detect NMI even if not rdy    
+        if NMI_n_o = '1' and (NMI_n = '0' and (IR(4 downto 0)/="10000" or Jump/="01")) then -- branches have influence on NMI start (not best way yet, though - but works...)
           NMIAct <= '1';
         end if;
+        -- we entered NMI during BRK instruction
+        if NMI_entered='1' then
+          NMIAct <= '0';
+        end if;
       end if;
     end if;
   end process;

src/T6502/T65_ALU.vhd

@@ -1,20 +1,18 @@
 -- ****
 -- T65(b) core. In an effort to merge and maintain bug fixes ....
 --
---
--- Ver 303 ost(ML) July 2014
---   ALU opcodes to vhdl types
--- Ver 300 Bugfixes by ehenciak added
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
+-- See list of changes in T65 top file (T65.vhd)...
 --
 -- ****
+-- 65xx compatible microprocessor core
 --
--- 6502 compatible microprocessor core
+-- FPGAARCADE SVN: $Id: T65_ALU.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
 --
--- Version : 0245
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+-- Copyright (c) 2002...2015
+--               Daniel Wallner (jesus <at> opencores <dot> org)
+--               Mike Johnson   (mikej <at> fpgaarcade <dot> com)
+--               Wolfgang Scherr (WoS <at> pin4 <dot> at>
+--               Morten Leikvoll ()
 --
 -- All rights reserved
 --
@@ -44,19 +42,12 @@
 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 -- POSSIBILITY OF SUCH DAMAGE.
 --
--- Please report bugs to the author, but before you do so, please
+-- Please report bugs to the author(s), but before you do so, please
 -- make sure that this is not a derivative work and that
 -- you have the latest version of this file.
 --
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t65/
---
 -- Limitations :
---
--- File history :
---
---      0245 : First version
---
+--   See in T65 top file (T65.vhd)...
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -88,6 +79,7 @@ architecture rtl of T65_ALU is
   signal      SBC_V           : std_logic;
   signal      SBC_N           : std_logic;
   signal      SBC_Q           : std_logic_vector(7 downto 0);
+  signal      SBX_Q           : std_logic_vector(7 downto 0);
 
 begin
 
@@ -146,7 +138,7 @@ begin
          Op=ALU_OP_SBC or	--"0111"
          Op=ALU_OP_ROL or	--"1001"
          Op=ALU_OP_ROR or	--"1011"
-         Op=ALU_OP_EQ3 or	--"1101"
+--         Op=ALU_OP_EQ3 or	--"1101"
          Op=ALU_OP_INC		--"1111"
       ) then
       CT:='1';
@@ -156,10 +148,10 @@ begin
     AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
     AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
 
--- pragma translate_off
-      if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
-      if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
--- pragma translate_on
+    -- pragma translate_off
+    if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+    if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
+    -- pragma translate_on
 
     if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
       SBC_Z <= '1';
@@ -171,6 +163,8 @@ begin
     SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
     SBC_N <= AH(4);
 
+    SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+
     if P_In(Flag_D) = '1' then
       if AL(5) = '1' then
         AL(5 downto 1) := AL(5 downto 1) - 6;
@@ -186,79 +180,114 @@ begin
 
   process (Op, P_In, BusA, BusB,
       ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
-      SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
+      SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
+      SBX_Q)
     variable Q_t : std_logic_vector(7 downto 0);
+    variable Q2_t : std_logic_vector(7 downto 0);
   begin
     -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
     -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
     P_Out <= P_In;
-    Q_t := BusA;
+    Q_t := BusA;
+    Q2_t := BusA;
     case Op is
-    when ALU_OP_OR=>
-      Q_t := BusA or BusB;
-    when ALU_OP_AND=>
-      Q_t := BusA and BusB;
-    when ALU_OP_EOR=>
-      Q_t := BusA xor BusB;
-    when ALU_OP_ADC=>
-      P_Out(Flag_V) <= ADC_V;
-      P_Out(Flag_C) <= ADC_C;
-      Q_t := ADC_Q;
-    when ALU_OP_EQ2|ALU_OP_EQ3=>
-      -- LDA
-    when ALU_OP_CMP=>
-      P_Out(Flag_C) <= SBC_C;
-    when ALU_OP_SBC=>
-      P_Out(Flag_V) <= SBC_V;
-      P_Out(Flag_C) <= SBC_C;
-      Q_t := SBC_Q;
-    when ALU_OP_ASL=>
-      Q_t := BusA(6 downto 0) & "0";
-      P_Out(Flag_C) <= BusA(7);
-    when ALU_OP_ROL=>
-      Q_t := BusA(6 downto 0) & P_In(Flag_C);
-      P_Out(Flag_C) <= BusA(7);
-    when ALU_OP_LSR=>
-      Q_t := "0" & BusA(7 downto 1);
-      P_Out(Flag_C) <= BusA(0);
-    when ALU_OP_ROR=>
-      Q_t := P_In(Flag_C) & BusA(7 downto 1);
-      P_Out(Flag_C) <= BusA(0);
-    when ALU_OP_BIT=>
-      P_Out(Flag_V) <= BusB(6);
-    when ALU_OP_DEC=>
-      Q_t := std_logic_vector(unsigned(BusA) - 1);
-    when ALU_OP_INC=>
-      Q_t := std_logic_vector(unsigned(BusA) + 1);
-    when others =>
-    --EQ1,EQ2,EQ3 passes BusA to Q_t
+      when ALU_OP_OR=>
+        Q_t := BusA or BusB;
+      when ALU_OP_AND=>
+        Q_t := BusA and BusB;
+      when ALU_OP_EOR=>
+        Q_t := BusA xor BusB;
+      when ALU_OP_ADC=>
+        P_Out(Flag_V) <= ADC_V;
+        P_Out(Flag_C) <= ADC_C;
+        Q_t := ADC_Q;
+      when ALU_OP_CMP=>
+        P_Out(Flag_C) <= SBC_C;
+      when ALU_OP_SAX=>
+        P_Out(Flag_C) <= SBC_C;
+        Q_t := SBX_Q;  -- undoc: subtract (A & X) - (immediate)
+      when ALU_OP_SBC=>
+        P_Out(Flag_V) <= SBC_V;
+        P_Out(Flag_C) <= SBC_C;
+        Q_t := SBC_Q;  -- undoc: subtract  (A & X) - (immediate), then decimal correction
+      when ALU_OP_ASL=>
+        Q_t := BusA(6 downto 0) & "0";
+        P_Out(Flag_C) <= BusA(7);
+      when ALU_OP_ROL=>
+        Q_t := BusA(6 downto 0) & P_In(Flag_C);
+        P_Out(Flag_C) <= BusA(7);
+      when ALU_OP_LSR=>
+        Q_t := "0" & BusA(7 downto 1);
+        P_Out(Flag_C) <= BusA(0);
+      when ALU_OP_ROR=>
+        Q_t := P_In(Flag_C) & BusA(7 downto 1);
+        P_Out(Flag_C) <= BusA(0);
+      when ALU_OP_ARR=> 
+        Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
+        P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
+        Q2_t := Q_t;
+        if P_In(Flag_D)='1' then
+          if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
+            Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
+          end if;
+          if (BusA(7 downto 4) and BusB(7 downto 4)) > "0100" then
+            Q2_t(7 downto 4) := std_logic_vector(unsigned(Q_t(7 downto 4)) + x"6");
+            P_Out(Flag_C) <= '1';
+          else
+            P_Out(Flag_C) <= '0';
+          end if;
+        else
+          P_Out(Flag_C) <= Q_t(6);
+        end if;
+      when ALU_OP_BIT=>
+        P_Out(Flag_V) <= BusB(6);
+      when ALU_OP_DEC=>
+        Q_t := std_logic_vector(unsigned(BusA) - 1);
+      when ALU_OP_INC=>
+        Q_t := std_logic_vector(unsigned(BusA) + 1);
+      when others =>
+        null;
+      --EQ1,EQ2,EQ3 passes BusA to Q_t and P_in to P_out
     end case;
 
     case Op is
-    when ALU_OP_ADC=>
-      P_Out(Flag_N) <= ADC_N;
-      P_Out(Flag_Z) <= ADC_Z;
-    when ALU_OP_CMP|ALU_OP_SBC=>
-      P_Out(Flag_N) <= SBC_N;
-      P_Out(Flag_Z) <= SBC_Z;
-    when ALU_OP_EQ1=>
-    when ALU_OP_BIT=>
-      P_Out(Flag_N) <= BusB(7);
-      if (BusA and BusB) = "00000000" then
-        P_Out(Flag_Z) <= '1';
-      else
-        P_Out(Flag_Z) <= '0';
-      end if;
-    when others =>
-      P_Out(Flag_N) <= Q_t(7);
-      if Q_t = "00000000" then
-        P_Out(Flag_Z) <= '1';
-      else
-        P_Out(Flag_Z) <= '0';
-      end if;
+      when ALU_OP_ADC=>
+        P_Out(Flag_N) <= ADC_N;
+        P_Out(Flag_Z) <= ADC_Z;
+      when ALU_OP_CMP|ALU_OP_SBC|ALU_OP_SAX=>
+        P_Out(Flag_N) <= SBC_N;
+        P_Out(Flag_Z) <= SBC_Z;
+      when ALU_OP_EQ1=>--dont touch P
+      when ALU_OP_BIT=>
+        P_Out(Flag_N) <= BusB(7);
+        if (BusA and BusB) = "00000000" then
+          P_Out(Flag_Z) <= '1';
+        else
+          P_Out(Flag_Z) <= '0';
+        end if;
+      when ALU_OP_ANC=>
+        P_Out(Flag_N) <= Q_t(7);
+        P_Out(Flag_C) <= Q_t(7);
+        if Q_t = "00000000" then
+          P_Out(Flag_Z) <= '1';
+        else
+          P_Out(Flag_Z) <= '0';
+        end if;
+      when others =>
+        P_Out(Flag_N) <= Q_t(7);
+        if Q_t = "00000000" then
+          P_Out(Flag_Z) <= '1';
+        else
+          P_Out(Flag_Z) <= '0';
+        end if;
     end case;
 
-    Q <= Q_t;
+    if Op=ALU_OP_ARR then
+      -- handled above in ARR code
+      Q <= Q2_t;
+    else
+      Q <= Q_t;
+    end if;
   end process;
 
 end;

src/T6502/T65_Pack.vhd

@@ -1,20 +1,18 @@
 -- ****
 -- T65(b) core. In an effort to merge and maintain bug fixes ....
 --
---
--- Ver 303 ost(ML) July 2014
---   "magic" constants converted to vhdl types
--- Ver 300 Bugfixes by ehenciak added
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
+-- See list of changes in T65 top file (T65.vhd)...
 --
 -- ****
---
 -- 65xx compatible microprocessor core
 --
--- Version : 0246
+-- FPGAARCADE SVN: $Id: T65_Pack.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
 --
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+-- Copyright (c) 2002...2015
+--               Daniel Wallner (jesus <at> opencores <dot> org)
+--               Mike Johnson   (mikej <at> fpgaarcade <dot> com)
+--               Wolfgang Scherr (WoS <at> pin4 <dot> at>
+--               Morten Leikvoll ()
 --
 -- All rights reserved
 --
@@ -44,17 +42,12 @@
 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 -- POSSIBILITY OF SUCH DAMAGE.
 --
--- Please report bugs to the author, but before you do so, please
+-- Please report bugs to the author(s), but before you do so, please
 -- make sure that this is not a derivative work and that
 -- you have the latest version of this file.
 --
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t65/
---
 -- Limitations :
---
--- File history :
---
+--   See in T65 top file (T65.vhd)...
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -70,6 +63,18 @@ package T65_Pack is
   constant Flag_V : integer := 6;
   constant Flag_N : integer := 7;
 
+  subtype T_Lcycle is std_logic_vector(2 downto 0);
+  constant Cycle_sync :T_Lcycle:="000";
+  constant Cycle_1    :T_Lcycle:="001";
+  constant Cycle_2    :T_Lcycle:="010";
+  constant Cycle_3    :T_Lcycle:="011";
+  constant Cycle_4    :T_Lcycle:="100";
+  constant Cycle_5    :T_Lcycle:="101";
+  constant Cycle_6    :T_Lcycle:="110";
+  constant Cycle_7    :T_Lcycle:="111";
+
+  function CycleNext(c:T_Lcycle) return T_Lcycle;
+
   type T_Set_BusA_To is
   (
     Set_BusA_To_DI,
@@ -78,15 +83,21 @@ package T65_Pack is
     Set_BusA_To_Y,
     Set_BusA_To_S,
     Set_BusA_To_P,
+    Set_BusA_To_DA,
+    Set_BusA_To_DAO,
+    Set_BusA_To_DAX,
+    Set_BusA_To_AAX,
     Set_BusA_To_DONTCARE
   );
+  
   type T_Set_Addr_To is
   (
-    Set_Addr_To_S,
-    Set_Addr_To_AD,
     Set_Addr_To_PBR,
+    Set_Addr_To_SP,
+    Set_Addr_To_ZPG,
     Set_Addr_To_BA
   );
+  
   type T_Write_Data is
   (
     Write_Data_DL,
@@ -97,74 +108,73 @@ package T65_Pack is
     Write_Data_P,
     Write_Data_PCL,
     Write_Data_PCH,
+    Write_Data_AX,
+    Write_Data_AXB,
+    Write_Data_XB,
+    Write_Data_YB,
     Write_Data_DONTCARE
   );
+  
   type T_ALU_OP is
   (
-  	ALU_OP_OR,	--"0000"
-  	ALU_OP_AND,	--"0001"
-  	ALU_OP_EOR,	--"0010"
-  	ALU_OP_ADC,	--"0011"
-  	ALU_OP_EQ1,	--"0100" EQ1 does not change N,Z flags, EQ2/3 does.
-  	ALU_OP_EQ2,	--"0101"Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
-  	ALU_OP_CMP,	--"0110"
-  	ALU_OP_SBC,	--"0111"
-  	ALU_OP_ASL,	--"1000"
-  	ALU_OP_ROL,	--"1001"
-  	ALU_OP_LSR,	--"1010"
-  	ALU_OP_ROR,	--"1011"
-  	ALU_OP_BIT,	--"1100"
-  	ALU_OP_EQ3,	--"1101"
-  	ALU_OP_DEC,	--"1110"
-  	ALU_OP_INC,	--"1111"
-  	ALU_OP_UNDEF--"----"--may be replaced with any?
+    ALU_OP_OR,  --"0000"
+    ALU_OP_AND,  --"0001"
+    ALU_OP_EOR,  --"0010"
+    ALU_OP_ADC,  --"0011"
+    ALU_OP_EQ1,  --"0100" EQ1 does not change N,Z flags, EQ2/3 does.
+    ALU_OP_EQ2,  --"0101" Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
+    ALU_OP_CMP,  --"0110"
+    ALU_OP_SBC,  --"0111"
+    ALU_OP_ASL,  --"1000"
+    ALU_OP_ROL,  --"1001"
+    ALU_OP_LSR,  --"1010"
+    ALU_OP_ROR,  --"1011"
+    ALU_OP_BIT,  --"1100"
+--    ALU_OP_EQ3,  --"1101"
+    ALU_OP_DEC,  --"1110"
+    ALU_OP_INC,  --"1111"
+    ALU_OP_ARR,
+    ALU_OP_ANC,
+    ALU_OP_SAX,
+    ALU_OP_XAA
+--    ALU_OP_UNDEF--"----"--may be replaced with any?
   );
 
-  component T65_MCode
-  port(
-    Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
-    IR                      : in  std_logic_vector(7 downto 0);
-    MCycle                  : in  std_logic_vector(2 downto 0);
-    P                       : in  std_logic_vector(7 downto 0);
-    LCycle                  : out std_logic_vector(2 downto 0);
-    ALU_Op                  : out T_ALU_Op;
-    Set_BusA_To             : out T_Set_BusA_To;-- DI,A,X,Y,S,P
-    Set_Addr_To             : out T_Set_Addr_To;-- PC Adder,S,AD,BA
-    Write_Data              : out T_Write_Data;-- DL,A,X,Y,S,P,PCL,PCH
-    Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
-    BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
-    BreakAtNA               : out std_logic;
-    ADAdd                   : out std_logic;
-    AddY                    : out std_logic;
-    PCAdd                   : out std_logic;
-    Inc_S                   : out std_logic;
-    Dec_S                   : out std_logic;
-    LDA                     : out std_logic;
-    LDP                     : out std_logic;
-    LDX                     : out std_logic;
-    LDY                     : out std_logic;
-    LDS                     : out std_logic;
-    LDDI                    : out std_logic;
-    LDALU                   : out std_logic;
-    LDAD                    : out std_logic;
-    LDBAL                   : out std_logic;
-    LDBAH                   : out std_logic;
-    SaveP                   : out std_logic;
-    ALUmore                 : out std_logic;
-    Write                   : out std_logic
-  );
-  end component;
-
-  component T65_ALU
-  port(
-    Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
-    Op      : in  T_ALU_Op;
-    BusA    : in  std_logic_vector(7 downto 0);
-    BusB    : in  std_logic_vector(7 downto 0);
-    P_In    : in  std_logic_vector(7 downto 0);
-    P_Out   : out std_logic_vector(7 downto 0);
-    Q       : out std_logic_vector(7 downto 0)
-  );
-  end component;
+  type T_t65_dbg is record
+    I     : std_logic_vector(7 downto 0); -- instruction
+    A     : std_logic_vector(7 downto 0); -- A reg
+    X     : std_logic_vector(7 downto 0); -- X reg
+    Y     : std_logic_vector(7 downto 0); -- Y reg
+    S     : std_logic_vector(7 downto 0); -- stack pointer
+    P     : std_logic_vector(7 downto 0); -- processor flags
+  end record;
 
 end;
+
+package body T65_Pack is
+
+  function CycleNext(c:T_Lcycle) return T_Lcycle is
+  begin
+    case(c) is
+    when Cycle_sync=>
+      return Cycle_1;
+    when Cycle_1=>
+      return Cycle_2;
+    when Cycle_2=>
+      return Cycle_3;
+    when Cycle_3=>
+      return Cycle_4;
+    when Cycle_4=>
+      return Cycle_5;
+    when Cycle_5=>
+      return Cycle_6;
+    when Cycle_6=>
+      return Cycle_7;
+    when Cycle_7=>
+      return Cycle_sync;
+    when others=>
+      return Cycle_sync;
+    end case;
+  end CycleNext;
+
+end T65_Pack;

src/T80/T80_ALU.vhd

@@ -1,10 +1,26 @@
+--------------------------------------------------------------------------------
+-- ****
+-- T80(c) core. Attempt to finish all undocumented features and provide
+--              accurate timings.
+-- Version 350.
+-- Copyright (c) 2018 Sorgelig
+--  Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
+--  (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
+--      correct implementation is still unclear.
 --
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
 -- Z80 compatible microprocessor core
 --
 -- Version : 0247
---
 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
 -- All rights reserved
 --
 -- Redistribution and use in source and synthezised forms, with or without
@@ -38,23 +54,17 @@
 -- you have the latest version of this file.
 --
 -- The latest version of this file can be found at:
---  http://www.opencores.org/cvsweb.shtml/t80/
+--      http://www.opencores.org/cvsweb.shtml/t80/
 --
 -- Limitations :
 --
 -- File history :
 --
---  0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---  0238 : Fixed zero flag for 16 bit SBC and ADC
---
---  0240 : Added GB operations
---
---  0242 : Cleanup
---
---  0247 : Cleanup
---
---  0249 : add undocumented XY-Flags for CPI/CPD by TobiFlex 22.07.2012
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--      0240 : Added GB operations
+--      0242 : Cleanup
+--      0247 : Cleanup
 --
 
 library IEEE;
@@ -62,301 +72,338 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 entity T80_ALU is
-    generic(
-        Mode   : integer := 0;
-        Flag_C : integer := 0;
-        Flag_N : integer := 1;
-        Flag_P : integer := 2;
-        Flag_X : integer := 3;
-        Flag_H : integer := 4;
-        Flag_Y : integer := 5;
-        Flag_Z : integer := 6;
-        Flag_S : integer := 7
-    );
-    port(
-        Arith16     : in std_logic;
-        Z16         : in std_logic;
-        ALU_cpi     : in std_logic;
-        ALU_Op      : in std_logic_vector(3 downto 0);
-        IR          : in std_logic_vector(5 downto 0);
-        ISet        : in std_logic_vector(1 downto 0);
-        BusA        : in std_logic_vector(7 downto 0);
-        BusB        : in std_logic_vector(7 downto 0);
-        F_In        : in std_logic_vector(7 downto 0);
-        Q           : out std_logic_vector(7 downto 0);
-        F_Out       : out std_logic_vector(7 downto 0)
-    );
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		WZ              : in  std_logic_vector(15 downto 0);
+		XY_State		    : in  std_logic_vector(1 downto 0);
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		Rot_Akku        : in  std_logic;
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
 end T80_ALU;
 
 architecture rtl of T80_ALU is
 
-    procedure AddSub(A : std_logic_vector;
-                    B : std_logic_vector;
-                    Sub : std_logic;
-                    Carry_In : std_logic;
-                    signal Res : out std_logic_vector;
-                    signal Carry : out std_logic) is
-        variable B_i        : unsigned(A'length - 1 downto 0);
-        variable Res_i      : unsigned(A'length + 1 downto 0);
-    begin
-        if Sub = '1' then
-            B_i := not unsigned(B);
-        else
-            B_i := unsigned(B);
-        end if;
-        Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-        Carry <= Res_i(A'length + 1);
-        Res <= std_logic_vector(Res_i(A'length downto 1));
-    end;
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
 
-    -- AddSub variables (temporary signals)
-    signal  UseCarry        : std_logic;
-    signal  Carry7_v        : std_logic;
-    signal  Overflow_v      : std_logic;
-    signal  HalfCarry_v     : std_logic;
-    signal  Carry_v         : std_logic;
-    signal  Q_v             : std_logic_vector(7 downto 0);
-    signal  Q_cpi           : std_logic_vector(4 downto 0);
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
 
-    signal  BitMask         : std_logic_vector(7 downto 0);
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
 
 begin
 
-    with IR(5 downto 3) select BitMask <= "00000001" when "000",
-                                    "00000010" when "001",
-                                    "00000100" when "010",
-                                    "00001000" when "011",
-                                    "00010000" when "100",
-                                    "00100000" when "101",
-                                    "01000000" when "110",
-                                    "10000000" when others;
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
 
-    UseCarry <= not ALU_Op(2) and ALU_Op(0);
-    AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-    AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-    AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-    OverFlow_v <= Carry_v xor Carry7_v;
-    
-    AddSub(BusA(3 downto 0), BusB(3 downto 0), '1', HalfCarry_v, Q_cpi(3 downto 0), Q_cpi(4));
-   
-    process (Arith16, ALU_OP, ALU_cpi, F_In, BusA, BusB, IR, Q_v, Q_cpi, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-        variable Q_t : std_logic_vector(7 downto 0);
-        variable DAA_Q : unsigned(8 downto 0);
-    begin
-        Q_t := "--------";
-        F_Out <= F_In;
-        DAA_Q := "---------";
-        case ALU_Op is
-        when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-            F_Out(Flag_N) <= '0';
-            F_Out(Flag_C) <= '0';
-            case ALU_OP(2 downto 0) is
-            when "000" | "001" => -- ADD, ADC
-                Q_t := Q_v;
-                F_Out(Flag_C) <= Carry_v;
-                F_Out(Flag_H) <= HalfCarry_v;
-                F_Out(Flag_P) <= OverFlow_v;
-            when "010" | "011" | "111" => -- SUB, SBC, CP
-                Q_t := Q_v;
-                F_Out(Flag_N) <= '1';
-                F_Out(Flag_C) <= not Carry_v;
-                F_Out(Flag_H) <= not HalfCarry_v;
-                F_Out(Flag_P) <= OverFlow_v;
-            when "100" => -- AND
-                Q_t(7 downto 0) := BusA and BusB;
-                F_Out(Flag_H) <= '1';
-            when "101" => -- XOR
-                Q_t(7 downto 0) := BusA xor BusB;
-                F_Out(Flag_H) <= '0';
-            when others => -- OR "110"
-                Q_t(7 downto 0) := BusA or BusB;
-                F_Out(Flag_H) <= '0';
-            end case;
-            if ALU_Op(2 downto 0) = "111" then -- CP
-                if ALU_cpi='1' then --CPI
-                    F_Out(Flag_X) <= Q_cpi(3);
-                    F_Out(Flag_Y) <= Q_cpi(1);
-                else
-                    F_Out(Flag_X) <= BusB(3);
-                    F_Out(Flag_Y) <= BusB(5);
-                end if;  
-            else
-                F_Out(Flag_X) <= Q_t(3);
-                F_Out(Flag_Y) <= Q_t(5);
-            end if;
-            if Q_t(7 downto 0) = "00000000" then
-                F_Out(Flag_Z) <= '1';
-                if Z16 = '1' then
-                    F_Out(Flag_Z) <= F_In(Flag_Z);  -- 16 bit ADC,SBC
-                end if;
-            else
-                F_Out(Flag_Z) <= '0';
-            end if;
-            F_Out(Flag_S) <= Q_t(7);
-            case ALU_Op(2 downto 0) is
-            when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-            when others =>
-                F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-                    Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-            end case;
-            if Arith16 = '1' then
-                F_Out(Flag_S) <= F_In(Flag_S);
-                F_Out(Flag_Z) <= F_In(Flag_Z);
-                F_Out(Flag_P) <= F_In(Flag_P);
-            end if;
-        when "1100" =>
-            -- DAA
-            F_Out(Flag_H) <= F_In(Flag_H);
-            F_Out(Flag_C) <= F_In(Flag_C);
-            DAA_Q(7 downto 0) := unsigned(BusA);
-            DAA_Q(8) := '0';
-            if F_In(Flag_N) = '0' then
-                -- After addition
-                -- Alow > 9 or H = 1
-                if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-                    if (DAA_Q(3 downto 0) > 9) then
-                        F_Out(Flag_H) <= '1';
-                    else
-                        F_Out(Flag_H) <= '0';
-                    end if;
-                    DAA_Q := DAA_Q + 6;
-                end if;
-                -- new Ahigh > 9 or C = 1
-                if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-                    DAA_Q := DAA_Q + 96; -- 0x60
-                end if;
-            else
-                -- After subtraction
-                if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-                    if DAA_Q(3 downto 0) > 5 then
-                        F_Out(Flag_H) <= '0';
-                    end if;
-                    DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-                end if;
-                if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-                    DAA_Q := DAA_Q - 352; -- 0x160
-                end if;
-            end if;
-            F_Out(Flag_X) <= DAA_Q(3);
-            F_Out(Flag_Y) <= DAA_Q(5);
-            F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-            Q_t := std_logic_vector(DAA_Q(7 downto 0));
-            if DAA_Q(7 downto 0) = "00000000" then
-                F_Out(Flag_Z) <= '1';
-            else
-                F_Out(Flag_Z) <= '0';
-            end if;
-            F_Out(Flag_S) <= DAA_Q(7);
-            F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-                DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-        when "1101" | "1110" =>
-            -- RLD, RRD
-            Q_t(7 downto 4) := BusA(7 downto 4);
-            if ALU_Op(0) = '1' then
-                Q_t(3 downto 0) := BusB(7 downto 4);
-            else
-                Q_t(3 downto 0) := BusB(3 downto 0);
-            end if;
-            F_Out(Flag_H) <= '0';
-            F_Out(Flag_N) <= '0';
-            F_Out(Flag_X) <= Q_t(3);
-            F_Out(Flag_Y) <= Q_t(5);
-            if Q_t(7 downto 0) = "00000000" then
-                F_Out(Flag_Z) <= '1';
-            else
-                F_Out(Flag_Z) <= '0';
-            end if;
-            F_Out(Flag_S) <= Q_t(7);
-            F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-                Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-        when "1001" =>
-            -- BIT
-            Q_t(7 downto 0) := BusB and BitMask;
-            F_Out(Flag_S) <= Q_t(7);
-            if Q_t(7 downto 0) = "00000000" then
-                F_Out(Flag_Z) <= '1';
-                F_Out(Flag_P) <= '1';
-            else
-                F_Out(Flag_Z) <= '0';
-                F_Out(Flag_P) <= '0';
-            end if;
-            F_Out(Flag_H) <= '1';
-            F_Out(Flag_N) <= '0';
-            F_Out(Flag_X) <= '0';
-            F_Out(Flag_Y) <= '0';
-            if IR(2 downto 0) /= "110" then
-                F_Out(Flag_X) <= BusB(3);
-                F_Out(Flag_Y) <= BusB(5);
-            end if;
-        when "1010" =>
-            -- SET
-            Q_t(7 downto 0) := BusB or BitMask;
-        when "1011" =>
-            -- RES
-            Q_t(7 downto 0) := BusB and not BitMask;
-        when "1000" =>
-            -- ROT
-            case IR(5 downto 3) is
-            when "000" => -- RLC
-                Q_t(7 downto 1) := BusA(6 downto 0);
-                Q_t(0) := BusA(7);
-                F_Out(Flag_C) <= BusA(7);
-            when "010" => -- RL
-                Q_t(7 downto 1) := BusA(6 downto 0);
-                Q_t(0) := F_In(Flag_C);
-                F_Out(Flag_C) <= BusA(7);
-            when "001" => -- RRC
-                Q_t(6 downto 0) := BusA(7 downto 1);
-                Q_t(7) := BusA(0);
-                F_Out(Flag_C) <= BusA(0);
-            when "011" => -- RR
-                Q_t(6 downto 0) := BusA(7 downto 1);
-                Q_t(7) := F_In(Flag_C);
-                F_Out(Flag_C) <= BusA(0);
-            when "100" => -- SLA
-                Q_t(7 downto 1) := BusA(6 downto 0);
-                Q_t(0) := '0';
-                F_Out(Flag_C) <= BusA(7);
-            when "110" => -- SLL (Undocumented) / SWAP
-                if Mode = 3 then
-                    Q_t(7 downto 4) := BusA(3 downto 0);
-                    Q_t(3 downto 0) := BusA(7 downto 4);
-                    F_Out(Flag_C) <= '0';
-                else
-                    Q_t(7 downto 1) := BusA(6 downto 0);
-                    Q_t(0) := '1';
-                    F_Out(Flag_C) <= BusA(7);
-                end if;
-            when "101" => -- SRA
-                Q_t(6 downto 0) := BusA(7 downto 1);
-                Q_t(7) := BusA(7);
-                F_Out(Flag_C) <= BusA(0);
-            when others => -- SRL
-                Q_t(6 downto 0) := BusA(7 downto 1);
-                Q_t(7) := '0';
-                F_Out(Flag_C) <= BusA(0);
-            end case;
-            F_Out(Flag_H) <= '0';
-            F_Out(Flag_N) <= '0';
-            F_Out(Flag_X) <= Q_t(3);
-            F_Out(Flag_Y) <= Q_t(5);
-            F_Out(Flag_S) <= Q_t(7);
-            if Q_t(7 downto 0) = "00000000" then
-                F_Out(Flag_Z) <= '1';
-            else
-                F_Out(Flag_Z) <= '0';
-            end if;
-            F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-                Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-            if ISet = "00" then
-                F_Out(Flag_P) <= F_In(Flag_P);
-                F_Out(Flag_S) <= F_In(Flag_S);
-                F_Out(Flag_Z) <= F_In(Flag_Z);
-            end if;
-        when others =>
-            null;
-        end case;
-        Q <= Q_t;
-    end process;
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
 
+	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
+	process (Carry_v, Carry7_v, Q_v)
+	begin
+		if(Mode=2) then
+			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
+					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
+			OverFlow_v <= Carry_v xor Carry7_v;
+		end if;
+	end process;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, Rot_Akku, WZ, XY_State)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			if Mode = 3 then
+				F_Out(Flag_H) <= '0';
+				F_Out(Flag_C) <= F_In(Flag_C);
+				DAA_Q(7 downto 0) := unsigned(BusA);
+				DAA_Q(8) := '0';
+				if F_In(Flag_N) = '0' then
+					-- After addition
+					-- Alow > 9 or H = 1
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+							DAA_Q := DAA_Q + 6;
+					end if;
+					-- new Ahigh > 9 or C = 1
+					if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q + 96; -- 0x60
+					end if;
+				else
+					-- After subtraction
+					if F_In(Flag_H) = '1' then
+						DAA_Q := DAA_Q - 6;
+						if F_In(Flag_C) = '0' then
+							DAA_Q(8) := '0';
+						end if;
+					end if;
+					if F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q - 96; -- 0x60
+					end if;
+				end if;
+			else
+				F_Out(Flag_H) <= F_In(Flag_H);
+				F_Out(Flag_C) <= F_In(Flag_C);
+				DAA_Q(7 downto 0) := unsigned(BusA);
+				DAA_Q(8) := '0';
+				if F_In(Flag_N) = '0' then
+					-- After addition
+					-- Alow > 9 or H = 1
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+						if (DAA_Q(3 downto 0) > 9) then
+							F_Out(Flag_H) <= '1';
+						else
+							F_Out(Flag_H) <= '0';
+						end if;
+						DAA_Q := DAA_Q + 6;
+					end if;
+					-- new Ahigh > 9 or C = 1
+					if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q + 96; -- 0x60
+					end if;
+				else
+					-- After subtraction
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+						if DAA_Q(3 downto 0) > 5 then
+							F_Out(Flag_H) <= '0';
+						end if;
+						DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+					end if;
+					if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q - 352; -- 0x160
+					end if;
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			if IR(2 downto 0) = "110" or XY_State /= "00" then
+				F_Out(Flag_X) <= WZ(11);
+				F_Out(Flag_Y) <= WZ(13);
+			else
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+			if Mode = 3 and Rot_Akku = '1'  then
+					F_Out(Flag_Z) <= '0';
+			end if; 
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
 end;

src/T80/T80_Pack.vhd

@@ -1,7 +1,17 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
 --
 -- Z80 compatible microprocessor core
 --
--- Version : 0242
+-- Version : 0250
 --
 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
 --
@@ -38,7 +48,7 @@
 -- you have the latest version of this file.
 --
 -- The latest version of this file can be found at:
---  http://www.opencores.org/cvsweb.shtml/t80/
+--      http://www.opencores.org/cvsweb.shtml/t80/
 --
 -- Limitations :
 --
@@ -50,165 +60,189 @@ use IEEE.std_logic_1164.all;
 
 package T80_Pack is
 
-    component T80
-    generic(
-        Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-        IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-        Flag_C : integer := 0;
-        Flag_N : integer := 1;
-        Flag_P : integer := 2;
-        Flag_X : integer := 3;
-        Flag_H : integer := 4;
-        Flag_Y : integer := 5;
-        Flag_Z : integer := 6;
-        Flag_S : integer := 7
-    );
-    port(
-        RESET_n     : in std_logic;
-        CLK_n       : in std_logic;
-        CEN         : in std_logic;
-        WAIT_n      : in std_logic;
-        INT_n       : in std_logic;
-        NMI_n       : in std_logic;
-        BUSRQ_n     : in std_logic;
-        M1_n        : out std_logic;
-        IORQ        : out std_logic;
-        NoRead      : out std_logic;
-        Write       : out std_logic;
-        RFSH_n      : out std_logic;
-        HALT_n      : out std_logic;
-        BUSAK_n     : out std_logic;
-        A           : out std_logic_vector(15 downto 0);
-        DInst       : in std_logic_vector(7 downto 0);
-        DI          : in std_logic_vector(7 downto 0);
-        DO          : out std_logic_vector(7 downto 0);
-        MC          : out std_logic_vector(2 downto 0);
-        TS          : out std_logic_vector(2 downto 0);
-        IntCycle_n  : out std_logic;
-        IntE        : out std_logic;
-        Stop        : out std_logic;
-        Regs        : out std_logic_vector(255 downto 0)        
-    );
-    end component;
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
 
-    component T80_Reg
-    port(
-        Clk         : in std_logic;
-        CEN         : in std_logic;
-        WEH         : in std_logic;
-        WEL         : in std_logic;
-        AddrA       : in std_logic_vector(2 downto 0);
-        AddrB       : in std_logic_vector(2 downto 0);
-        AddrC       : in std_logic_vector(2 downto 0);
-        DIH         : in std_logic_vector(7 downto 0);
-        DIL         : in std_logic_vector(7 downto 0);
-        DOAH        : out std_logic_vector(7 downto 0);
-        DOAL        : out std_logic_vector(7 downto 0);
-        DOBH        : out std_logic_vector(7 downto 0);
-        DOBL        : out std_logic_vector(7 downto 0);
-        DOCH        : out std_logic_vector(7 downto 0);
-        DOCL        : out std_logic_vector(7 downto 0);
-        RegFileData : out std_logic_vector(127 downto 0)
-    );
-    end component;
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN             : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI              : in std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		NMICycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic;
+		R800_mode       : in  std_logic := '0';
+		out0            : in  std_logic := '0';  -- 0 => OUT(C),0, 1 => OUT(C),255
+		REG             : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
+		DIRSet          : in  std_logic := '0';
+		DIR             : in  std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
+	);
+	end component;
 
-    component T80_MCode
-    generic(
-        Mode : integer := 0;
-        Flag_C : integer := 0;
-        Flag_N : integer := 1;
-        Flag_P : integer := 2;
-        Flag_X : integer := 3;
-        Flag_H : integer := 4;
-        Flag_Y : integer := 5;
-        Flag_Z : integer := 6;
-        Flag_S : integer := 7
-    );
-    port(
-        IR              : in std_logic_vector(7 downto 0);
-        ISet            : in std_logic_vector(1 downto 0);
-        MCycle          : in std_logic_vector(2 downto 0);
-        F               : in std_logic_vector(7 downto 0);
-        NMICycle        : in std_logic;
-        IntCycle        : in std_logic;
-        XY_State        : in  std_logic_vector(1 downto 0);
-        MCycles         : out std_logic_vector(2 downto 0);
-        TStates         : out std_logic_vector(2 downto 0);
-        Prefix          : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-        Inc_PC          : out std_logic;
-        Inc_WZ          : out std_logic;
-        IncDec_16       : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-        Read_To_Reg     : out std_logic;
-        Read_To_Acc     : out std_logic;
-        Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-        Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-        ALU_Op          : out std_logic_vector(3 downto 0);
-            -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-        ALU_cpi         : out std_logic;
-        Save_ALU        : out std_logic;
-        PreserveC       : out std_logic;
-        Arith16         : out std_logic;
-        Set_Addr_To     : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-        IORQ            : out std_logic;
-        Jump            : out std_logic;
-        JumpE           : out std_logic;
-        JumpXY          : out std_logic;
-        Call            : out std_logic;
-        RstP            : out std_logic;
-        LDZ             : out std_logic;
-        LDW             : out std_logic;
-        LDSPHL          : out std_logic;
-        Special_LD      : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-        ExchangeDH      : out std_logic;
-        ExchangeRp      : out std_logic;
-        ExchangeAF      : out std_logic;
-        ExchangeRS      : out std_logic;
-        I_DJNZ          : out std_logic;
-        I_CPL           : out std_logic;
-        I_CCF           : out std_logic;
-        I_SCF           : out std_logic;
-        I_RETN          : out std_logic;
-        I_BT            : out std_logic;
-        I_BC            : out std_logic;
-        I_BTR           : out std_logic;
-        I_RLD           : out std_logic;
-        I_RRD           : out std_logic;
-        I_INRC          : out std_logic;
-        SetDI           : out std_logic;
-        SetEI           : out std_logic;
-        IMode           : out std_logic_vector(1 downto 0);
-        Halt            : out std_logic;
-        NoRead          : out std_logic;
-        Write           : out std_logic;
-        XYbit_undoc     : out std_logic
-    );
-    end component;
+	component T80_Reg
+	port(
+		Clk             : in std_logic;
+		CEN             : in std_logic;
+		WEH             : in std_logic;
+		WEL             : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH             : in std_logic_vector(7 downto 0);
+		DIL             : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0);
+		DOR             : out std_logic_vector(127 downto 0);
+		DIRSet          : in  std_logic;
+		DIR             : in  std_logic_vector(127 downto 0)
+	);
+	end component;
 
-    component T80_ALU
-    generic(
-        Mode : integer := 0;
-        Flag_C : integer := 0;
-        Flag_N : integer := 1;
-        Flag_P : integer := 2;
-        Flag_X : integer := 3;
-        Flag_H : integer := 4;
-        Flag_Y : integer := 5;
-        Flag_Z : integer := 6;
-        Flag_S : integer := 7
-    );
-    port(
-        Arith16     : in std_logic;
-        Z16         : in std_logic;
-        ALU_cpi     : in std_logic;
-        ALU_Op      : in std_logic_vector(3 downto 0);
-        IR          : in std_logic_vector(5 downto 0);
-        ISet        : in std_logic_vector(1 downto 0);
-        BusA        : in std_logic_vector(7 downto 0);
-        BusB        : in std_logic_vector(7 downto 0);
-        F_In        : in std_logic_vector(7 downto 0);
-        Q           : out std_logic_vector(7 downto 0);
-        F_Out       : out std_logic_vector(7 downto 0)
-    );
-    end component;
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		XY_State                : in  std_logic_vector(1 downto 0);
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		Rot_Akku                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		LDHLSP                  : out std_logic;
+		ADDSPdd                 : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		I_MULUB                 : out std_logic;
+		I_MULU                  : out std_logic;
+		SetWZ                   : out std_logic_vector(1 downto 0);
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic;
+		R800_mode               : in  std_logic;
+		No_PC                   : out std_logic;
+		XYbit_undoc             : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		WZ              : in  std_logic_vector(15 downto 0);
+		XY_State        : in  std_logic_vector(1 downto 0);
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		Rot_Akku        : in  std_logic;
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
 
 end;

src/T80/T80_Reg.vhd

@@ -1,3 +1,22 @@
+--------------------------------------------------------------------------------
+-- ****
+-- T80(c) core. Attempt to finish all undocumented features and provide
+--              accurate timings.
+-- Version 350.
+-- Copyright (c) 2018 Sorgelig
+--  Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
+--  (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
+--      correct implementation is still unclear.
+--
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
 --
 -- T80 Registers, technology independent
 --
@@ -38,15 +57,15 @@
 -- you have the latest version of this file.
 --
 -- The latest version of this file can be found at:
---  http://www.opencores.org/cvsweb.shtml/t51/
+--	http://www.opencores.org/cvsweb.shtml/t51/
 --
 -- Limitations :
 --
 -- File history :
 --
---  0242 : Initial release
+--	0242 : Initial release
 --
---  0244 : Changed to single register file
+--	0244 : Changed to single register file
 --
 
 library IEEE;
@@ -54,70 +73,80 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 entity T80_Reg is
-    port(
-        Clk         : in std_logic;
-        CEN         : in std_logic;
-        WEH         : in std_logic;
-        WEL         : in std_logic;
-        AddrA       : in std_logic_vector(2 downto 0);
-        AddrB       : in std_logic_vector(2 downto 0);
-        AddrC       : in std_logic_vector(2 downto 0);
-        DIH         : in std_logic_vector(7 downto 0);
-        DIL         : in std_logic_vector(7 downto 0);
-        DOAH        : out std_logic_vector(7 downto 0);
-        DOAL        : out std_logic_vector(7 downto 0);
-        DOBH        : out std_logic_vector(7 downto 0);
-        DOBL        : out std_logic_vector(7 downto 0);
-        DOCH        : out std_logic_vector(7 downto 0);
-        DOCL        : out std_logic_vector(7 downto 0);
-        RegFileData : out std_logic_vector(127 downto 0)
-    );
+	port(
+		Clk     : in  std_logic;
+		CEN     : in  std_logic;
+		WEH     : in  std_logic;
+		WEL     : in  std_logic;
+		AddrA   : in  std_logic_vector(2 downto 0);
+		AddrB   : in  std_logic_vector(2 downto 0);
+		AddrC   : in  std_logic_vector(2 downto 0);
+		DIH     : in  std_logic_vector(7 downto 0);
+		DIL     : in  std_logic_vector(7 downto 0);
+		DOAH    : out std_logic_vector(7 downto 0);
+		DOAL    : out std_logic_vector(7 downto 0);
+		DOBH    : out std_logic_vector(7 downto 0);
+		DOBL    : out std_logic_vector(7 downto 0);
+		DOCH    : out std_logic_vector(7 downto 0);
+		DOCL    : out std_logic_vector(7 downto 0);
+		DOR     : out std_logic_vector(127 downto 0);
+		DIRSet  : in  std_logic;
+		DIR     : in  std_logic_vector(127 downto 0)
+	);
 end T80_Reg;
 
 architecture rtl of T80_Reg is
 
-    type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-    signal  RegsH   : Register_Image(0 to 7);
-    signal  RegsL   : Register_Image(0 to 7);
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal RegsH : Register_Image(0 to 7);
+	signal RegsL : Register_Image(0 to 7);
 
 begin
 
-    RegFileData( 7  downto   0) <= RegsL(0);
-    RegFileData( 15 downto   8) <= RegsH(0);
-    RegFileData( 23 downto  16) <= RegsL(1);
-    RegFileData( 31 downto  24) <= RegsH(1);
-    RegFileData( 39 downto  32) <= RegsL(2);
-    RegFileData( 47 downto  40) <= RegsH(2);
-    RegFileData( 55 downto  48) <= RegsL(3);
-    RegFileData( 63 downto  56) <= RegsH(3);
-    RegFileData( 71 downto  64) <= RegsL(4);
-    RegFileData( 79 downto  72) <= RegsH(4);
-    RegFileData( 87 downto  80) <= RegsL(5);
-    RegFileData( 95 downto  88) <= RegsH(5);
-    RegFileData(103 downto  96) <= RegsL(6);
-    RegFileData(111 downto 104) <= RegsH(6);
-    RegFileData(119 downto 112) <= RegsL(7);
-    RegFileData(127 downto 120) <= RegsH(7);
+	process (Clk)
+	begin
+		if rising_edge(Clk) then
+			if DIRSet = '1' then
+				RegsL(0) <= DIR(  7 downto   0);
+				RegsH(0) <= DIR( 15 downto   8);
 
-    process (Clk)
-    begin
-        if Clk'event and Clk = '1' then
-            if CEN = '1' then
-                if WEH = '1' then
-                    RegsH(to_integer(unsigned(AddrA))) <= DIH;
-                end if;
-                if WEL = '1' then
-                    RegsL(to_integer(unsigned(AddrA))) <= DIL;
-                end if;
-            end if;
-        end if;
-    end process;
+				RegsL(1) <= DIR( 23 downto  16);
+				RegsH(1) <= DIR( 31 downto  24);
 
-    DOAH <= RegsH(to_integer(unsigned(AddrA)));
-    DOAL <= RegsL(to_integer(unsigned(AddrA)));
-    DOBH <= RegsH(to_integer(unsigned(AddrB)));
-    DOBL <= RegsL(to_integer(unsigned(AddrB)));
-    DOCH <= RegsH(to_integer(unsigned(AddrC)));
-    DOCL <= RegsL(to_integer(unsigned(AddrC)));
+				RegsL(2) <= DIR( 39 downto  32);
+				RegsH(2) <= DIR( 47 downto  40);
+
+				RegsL(3) <= DIR( 55 downto  48);
+				RegsH(3) <= DIR( 63 downto  56);
+
+				RegsL(4) <= DIR( 71 downto  64);
+				RegsH(4) <= DIR( 79 downto  72);
+
+				RegsL(5) <= DIR( 87 downto  80);
+				RegsH(5) <= DIR( 95 downto  88);
+
+				RegsL(6) <= DIR(103 downto  96);
+				RegsH(6) <= DIR(111 downto 104);
+
+				RegsL(7) <= DIR(119 downto 112);
+				RegsH(7) <= DIR(127 downto 120);
+			elsif CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+	DOR  <= RegsH(7) & RegsL(7) & RegsH(6) & RegsL(6) & RegsH(5) & RegsL(5) & RegsH(4) & RegsL(4) & RegsH(3) & RegsL(3) & RegsH(2) & RegsL(2) & RegsH(1) & RegsL(1) & RegsH(0) & RegsL(0);
 
 end;

src/T80/T80a.vhd

@@ -72,11 +72,13 @@ entity T80a is
     );
     port(
         -- Additions
-        TS              : out std_logic_vector(2 downto 0);
-        Regs            : out std_logic_vector(255 downto 0);
+        TS          : out std_logic_vector(2 downto 0);
+        Regs        : out std_logic_vector(255 downto 0);
+        PdcData     : out std_logic_vector(7 downto 0);
         -- Original Signals
         RESET_n     : in std_logic;
         CLK_n       : in std_logic;
+        CEN         : in std_logic;
         WAIT_n      : in std_logic;
         INT_n       : in std_logic;
         NMI_n       : in std_logic;
@@ -98,9 +100,9 @@ end T80a;
 
 architecture rtl of T80a is
 
-    signal CEN          : std_logic;
     signal Reset_s      : std_logic;
     signal IntCycle_n   : std_logic;
+    signal NMICycle_n   : std_logic;
     signal IORQ         : std_logic;
     signal NoRead       : std_logic;
     signal Write        : std_logic;
@@ -122,22 +124,35 @@ architecture rtl of T80a is
     signal Wait_s       : std_logic;
     signal MCycle       : std_logic_vector(2 downto 0);
     signal TState       : std_logic_vector(2 downto 0);
+    signal HALT_n_int   : std_logic;
+    signal iack1        : std_logic;
+    signal iack2        : std_logic;
 
 begin
 
-    CEN <= '1';
 
     BUSAK_n <= BUSAK_n_i;
     MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-    RD_n_i <= not RD or Req_Inhibit;
-    WR_n_j <= WR_n_i;					    		-- 0247a
+    RD_n_i <= not RD or (IORQ and IReq_Inhibit) or Req_Inhibit;  -- DMB
+    WR_n_j <= WR_n_i or (IORQ and IReq_Inhibit);                 -- DMB
+    HALT_n <= HALT_n_int;
+
+
+    --Remove tristate as in ICE-Z80 this is implmeneted in Z80CpuMon
+    --MREQ_n <= MREQ_n_i; when BUSAK_n_i = '1' else 'Z';
+    --IORQ_n <= IORQ_n_i or IReq_Inhibit when BUSAK_n_i = '1' else 'Z';	-- 0247a
+    --RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
+    --WR_n <= WR_n_j when BUSAK_n_i = '1' else 'Z';			-- 0247a
+    --RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
+    --A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
+
+    MREQ_n <= MREQ_n_i;
+    IORQ_n <= IORQ_n_i or IReq_Inhibit or Req_inhibit; --DMB
+    RD_n <= RD_n_i;
+    WR_n <= WR_n_j;			-- 0247a
+    RFSH_n <= RFSH_n_i;
+    A <= A_i;
 
-    MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
-    IORQ_n <= IORQ_n_i or IReq_Inhibit when BUSAK_n_i = '1' else 'Z';	-- 0247a
-    RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
-    WR_n <= WR_n_j when BUSAK_n_i = '1' else 'Z';			-- 0247a
-    RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
-    A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
     Dout <= DO;
     Den  <= Write and BUSAK_n_i;
 
@@ -161,7 +176,7 @@ begin
             NoRead => NoRead,
             Write => Write,
             RFSH_n => RFSH_n_i,
-            HALT_n => HALT_n,
+            HALT_n => HALT_n_int,
             WAIT_n => Wait_s,
             INT_n => INT_n,
             NMI_n => NMI_n,
@@ -176,15 +191,22 @@ begin
             MC => MCycle,
             TS => TState,
             IntCycle_n => IntCycle_n,
-            Regs => Regs
+            NMICycle_n => NMICycle_n,
+            REG => Regs(211 downto 0),
+            DIRSet => '0',
+            DIR => (others => '0')
             );
 
+    Regs(255 downto 212) <= (others => '0');
+
     process (CLK_n)
     begin
         if CLK_n'event and CLK_n = '0' then
-            Wait_s <= WAIT_n;
-            if TState = "011" and BUSAK_n_i = '1' then
-                DI_Reg <= to_x01(Din);
+            if CEN = '1' then
+                Wait_s <= WAIT_n or (IORQ_n_i and MREQ_n_i);
+                if TState = "011" and BUSAK_n_i = '1' then
+                    DI_Reg <= to_x01(Din);
+                end if;
             end if;
         end if;
     end process;
@@ -192,7 +214,7 @@ begin
     process (CLK_n)		-- 0247a
     begin
         if CLK_n'event and CLK_n = '1' then
-            -- IReq_Inhibit <= not IORQ;
+            IReq_Inhibit <= (not IORQ) and IntCycle_n;
         end if;
     end process;
 
@@ -201,17 +223,19 @@ begin
         if Reset_s = '0' then
             WR_n_i <= '1';
         elsif CLK_n'event and CLK_n = '0' then
-            if (IORQ = '0') then
-                if TState = "010" then
-                    WR_n_i <= not Write;
-                elsif Tstate = "011" then
-                    WR_n_i <= '1';
-                end if;
-            else
-                if TState = "001" and IORQ_n_i = '0' then
-                    WR_n_i <= not Write;
-                elsif Tstate = "011" then
-                    WR_n_i <= '1';
+            if CEN = '1' then
+                if (IORQ = '0') then
+                    if TState = "010" then
+                        WR_n_i <= not Write;
+                    elsif Tstate = "011" then
+                        WR_n_i <= '1';
+                    end if;
+                else
+                    if TState = "001" then     -- DMB
+                        WR_n_i <= not Write;
+                    elsif Tstate = "011" then
+                        WR_n_i <= '1';
+                    end if;
                 end if;
             end if;
         end if;
@@ -222,10 +246,12 @@ begin
         if Reset_s = '0' then
             Req_Inhibit <= '0';
         elsif CLK_n'event and CLK_n = '1' then
-            if MCycle = "001" and TState = "010" and wait_s = '1' then
-                Req_Inhibit <= '1';
-            else
-                Req_Inhibit <= '0';
+            if CEN = '1' then
+                if MCycle = "001" and TState = "010" and wait_s = '1' then
+                    Req_Inhibit <= '1';
+                else
+                    Req_Inhibit <= '0';
+                end if;
             end if;
         end if;
     end process;
@@ -235,10 +261,12 @@ begin
         if Reset_s = '0' then
             MReq_Inhibit <= '0';
         elsif CLK_n'event and CLK_n = '0' then
-            if MCycle = "001" and TState = "010" then
-                MReq_Inhibit <= '1';
-            else
-                MReq_Inhibit <= '0';
+            if CEN = '1' then
+                if MCycle = "001" and TState = "010" then
+                    MReq_Inhibit <= '1';
+                else
+                    MReq_Inhibit <= '0';
+                end if;
             end if;
         end if;
     end process;
@@ -249,40 +277,59 @@ begin
             RD <= '0';
             IORQ_n_i <= '1';
             MREQ <= '0';
+            iack1 <= '0';
+            iack2 <= '0';
         elsif CLK_n'event and CLK_n = '0' then
-
-            if MCycle = "001" then
-                if TState = "001" then
-                    RD <= IntCycle_n;
-                    MREQ <= IntCycle_n;
-                    IORQ_n_i <= IntCycle_n;
-                end if;
-                if TState = "011" then
-                    RD <= '0';
-                    IORQ_n_i <= '1';
-                    MREQ <= '1';
-                end if;
-                if TState = "100" then
-                    MREQ <= '0';
-                end if;
-            else
-                if TState = "001" and NoRead = '0' then
-                    IORQ_n_i <= not IORQ;
-                    MREQ <= not IORQ;
-                    if IORQ = '0' then
-                      RD <= not Write;
-                    elsif IORQ_n_i = '0' then
-                      RD <= not Write;
+            if CEN = '1' then
+                if MCycle = "001" then
+                    if IntCycle_n = '1' then
+                        -- Normal M1 Cycle
+                        if TState = "001" then
+                            RD <= '1';
+                            MREQ <= '1';
+                            IORQ_n_i <= '1';
+                        end if;
+                    else
+                        -- Interupt Ack Cycle
+                        -- 5 T-states: T1 T1 (auto wait) T1 (auto wait) T2 T3
+                        -- Assert IORQ in middle of third T1
+                        if TState = "001" then
+                            iack1 <= '1';
+                            iack2 <= iack1;
+                        else
+                            iack1 <= '0';
+                            iack2 <= '0';
+                        end if;
+                        if iack2 = '1' then
+                            IORQ_n_i <= '0';
+                        end if;
+                    end if;
+                    if TState = "011" then
+                        RD <= '0';
+                        IORQ_n_i <= '1';
+                        MREQ <= '1';
+                    end if;
+                    if TState = "100" then
+                        MREQ <= '0';
+                    end if;
+                else
+                    if TState = "001" and NoRead = '0' then
+                        IORQ_n_i <= not IORQ;
+                        MREQ <= not IORQ;
+                        RD <= not Write;    -- DMB
+                    end if;
+                    if TState = "011" then
+                        RD <= '0';
+                        IORQ_n_i <= '1';
+                        MREQ <= '0';
                     end if;
-                end if;
-                if TState = "011" then
-                    RD <= '0';
-                    IORQ_n_i <= '1';
-                    MREQ <= '0';
                 end if;
             end if;
         end if;
     end process;
 
     TS <= TState;
+
+    PdcData <= (not HALT_n_int) & (not NMICycle_n) & (not IntCycle_n) & "00000";
+
 end;

src/UnknownAdapter.v

@@ -0,0 +1,38 @@
+module UnknownAdapter
+  (
+   input       clock,
+   input       mode,
+   input [3:0] id,
+   output      led1, // red
+   output      led2, // trig 1
+   output      led3, // trig 2
+   output      ld1,
+   output      ld2,
+   output      ld3,
+   output      ld4,
+   output      ld5,
+   output      ld6,
+   output      ld7,
+   output      ld8
+   );
+
+   reg [24:0]  counter;
+
+   always@(posedge clock) begin
+      counter <= counter + 1;
+   end
+
+   assign led1 = counter[24];
+   assign led2 = 1'b0;
+   assign led3 = 1'b0;
+
+   assign ld1 = counter[24];
+   assign ld2 = 1'b0;
+   assign ld3 = 1'b0;
+   assign ld4 = mode;
+   assign ld5 = id[3];
+   assign ld6 = id[2];
+   assign ld7 = id[1];
+   assign ld8 = id[0];
+
+endmodule

src/W65C02CpuMon.vhd

@@ -1,174 +0,0 @@
---------------------------------------------------------------------------------
--- Copyright (c) 2019 David Banks
---
---------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /
--- \   \   \/
---  \   \
---  /   /         Filename  : W65C02CpuMon.vhd
--- /___/   /\     Timestamp : 20/09/2019
--- \   \  /  \
---  \___\/\___\
---
---Design Name: W65C02CpuMon
---Device: XC6SLX9
---
---
--- This is a small wrapper around AtomCpuMon that add the following signals:
---   OEAH_n
---   OEAL_n
---   OED_n
---   DIRD
---   BE
---   ML_n
---   VP_n
--- (these are not fully implemented yet)
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity W65C02CpuMon is
-   generic (
-       UseT65Core     : boolean := true;
-       UseAlanDCore   : boolean := false;
-       LEDsActiveHigh : boolean := true;     -- default value for EEPIZZA
-       SW1ActiveHigh  : boolean := false;    -- default value for EEPIZZA
-       SW2ActiveHigh  : boolean := false;    -- default value for EEPIZZA
-       ClkMult        : integer :=  8;       -- default value for EEPIZZA
-       ClkDiv         : integer := 25;       -- default value for EEPIZZA
-       ClkPer         : real    := 16.000    -- default value for EEPIZZA
-       );
-    port (
-        clock           : in    std_logic;
-
-        -- 6502 Signals
-        PhiIn           : in    std_logic;
-        Phi1Out         : out   std_logic;
-        Phi2Out         : out   std_logic;
-        IRQ_n           : in    std_logic;
-        NMI_n           : in    std_logic;
-        Sync            : out   std_logic;
-        Addr            : out   std_logic_vector(15 downto 0);
-        R_W_n           : out   std_logic_vector(1 downto 0);
-        Data            : inout std_logic_vector(7 downto 0);
-        SO_n            : in    std_logic;
-        Res_n           : inout std_logic;
-        Rdy             : in    std_logic;
-
-        -- 65C02 Signals
-        BE              : in    std_logic;
-        ML_n            : out   std_logic;
-        VP_n            : out   std_logic;
-
-        -- Level Shifter Controls
-        OERW_n          : out   std_logic;
-        OEAH_n          : out   std_logic;
-        OEAL_n          : out   std_logic;
-        OED_n           : out   std_logic;
-        DIRD            : out   std_logic;
-
-        -- External trigger inputs
-        trig            : in    std_logic_vector(1 downto 0);
-
-        -- ID/mode inputs
-        mode            : in    std_logic;
-        id              : in    std_logic_vector(3 downto 0);
-
-        -- Serial Console
-        avr_RxD         : in    std_logic;
-        avr_TxD         : out   std_logic;
-
-        -- Switches
-        sw1              : in   std_logic;
-        sw2              : in   std_logic;
-
-        -- LEDs
-        led1             : out  std_logic;
-        led2             : out  std_logic;
-        led3             : out  std_logic;
-
-        -- OHO_DY1 LED display
-        tmosi            : out  std_logic;
-        tdin             : out  std_logic;
-        tcclk            : out  std_logic
-    );
-end W65C02CpuMon;
-
-architecture behavioral of W65C02CpuMon is
-
-    signal R_W_n_int     : std_logic;
-
-begin
-
-    acm : entity work.AtomCpuMon
-    generic map (
-       UseT65Core     => UseT65Core,
-       UseAlanDCore   => UseAlanDCore,
-       LEDsActiveHigh => LEDsActiveHigh,
-       SW1ActiveHigh  => SW1ActiveHigh,
-       SW2ActiveHigh  => SW2ActiveHigh,
-       ClkMult        => ClkMult,
-       ClkDiv         => ClkDiv,
-       ClkPer         => ClkPer
-    )
-    port map (
-        clock49         => clock,
-
-        -- 6502 Signals
-        Phi0            => PhiIn,
-        Phi1            => Phi1Out,
-        Phi2            => Phi2Out,
-        IRQ_n           => IRQ_n,
-        NMI_n           => NMI_n,
-        Sync            => Sync,
-        Addr            => Addr,
-        R_W_n           => R_W_n_int,
-        Data            => Data,
-        SO_n            => SO_n,
-        Res_n           => Res_n,
-        Rdy             => Rdy,
-
-        -- External trigger inputs
-        trig            => trig,
-
-        -- Jumpers
-        fakeTube_n      => '1',
-
-        -- Serial Console
-        avr_RxD         => avr_RxD,
-        avr_TxD         => avr_TxD,
-
-        -- Switches
-        sw1              => sw1,
-        sw2              => sw2,
-
-        -- LEDs
-        led3             => led2, -- trig 0
-        led6             => led3, -- trig 1
-        led8             => led1, -- break
-
-        -- OHO_DY1 LED display
-        tmosi            => tmosi,
-        tdin             => tdin,
-        tcclk            => tcclk
-    );
-
-    -- 6502 Outputs
-    R_W_n <= R_W_n_int & R_W_n_int;
-
-    -- 65C02 Outputs
-    ML_n   <= '1';
-    VP_n   <= '1';
-
-    -- Level Shifter Controls
-    OERW_n <= not (BE);
-    OEAH_n <= not (BE);
-    OEAL_n <= not (BE);
-    OED_n  <= not (BE and PhiIn); -- TODO: might need to use a slightly delayed version of Phi2 here
-    DIRD   <= R_W_n_int;
-
-end behavioral;

src/Z80CpuMon.vhd

@@ -22,16 +22,14 @@ use ieee.numeric_std.all;
 
 entity Z80CpuMon is
     generic (
-       UseT80Core     : boolean := true;
-       LEDsActiveHigh : boolean := false;    -- default value correct for GODIL
-       SW1ActiveHigh  : boolean := true;     -- default value correct for GODIL
-       SW2ActiveHigh  : boolean := false;    -- default value correct for GODIL
-       ClkMult        : integer := 10;       -- default value correct for GODIL
-       ClkDiv         : integer := 31;       -- default value correct for GODIL
-       ClkPer         : real    := 20.345    -- default value correct for GODIL
+       ClkMult           : integer;
+       ClkDiv            : integer;
+       ClkPer            : real;
+       num_comparators   : integer;
+       avr_prog_mem_size : integer
        );
     port (
-        clock49         : in    std_logic;
+        clock           : in    std_logic;
 
         -- Z80 Signals
         RESET_n         : in    std_logic;
@@ -50,7 +48,14 @@ entity Z80CpuMon is
         BUSAK_n         : out   std_logic;
         Addr            : out   std_logic_vector(15 downto 0);
         Data            : inout std_logic_vector(7 downto 0);
-        DOE_n           : out   std_logic;
+
+        -- Buffer Control Signals
+        DIRD            : out   std_logic;
+        tristate_n      : out   std_logic;
+        tristate_ad_n   : out   std_logic;
+
+        -- Mode jumper, tie low to generate NOPs when paused
+        mode            : in    std_logic;
 
         -- External trigger inputs
         trig            : in    std_logic_vector(1 downto 0);
@@ -59,14 +64,14 @@ entity Z80CpuMon is
         avr_RxD         : in    std_logic;
         avr_TxD         : out   std_logic;
 
-        -- GODIL Switches
-        sw1             : in    std_logic;
-        sw2             : in    std_logic;
+        -- Switches
+        sw_reset_cpu    : in    std_logic;
+        sw_reset_avr    : in    std_logic;
 
-        -- GODIL LEDs
-        led3            : out   std_logic;
-        led6            : out   std_logic;
-        led8            : out   std_logic;
+        -- LEDs
+        led_bkpt        : out   std_logic;
+        led_trig0       : out   std_logic;
+        led_trig1       : out   std_logic;
 
         -- OHO_DY1 connected to test connector
         tmosi           : out   std_logic;
@@ -84,32 +89,38 @@ end Z80CpuMon;
 
 architecture behavioral of Z80CpuMon is
 
-type state_type is (idle, resume, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, rd_t3, wr_t1, wr_wa, wr_t2, wr_t3);
+type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, rd_t3, wr_t1, wr_wa, wr_t2, wr_t3, busack);
 
-    signal state  : state_type;
+    signal state          : state_type;
 
     signal clock_avr      : std_logic;
 
-    signal RESET_n_int    : std_logic;
+    signal cpu_reset_n    : std_logic;
     signal cpu_clk        : std_logic;
+    signal cpu_clken      : std_logic;
     signal busmon_clk     : std_logic;
 
     signal Addr_int       : std_logic_vector(15 downto 0);
+    signal Addr1          : std_logic_vector(15 downto 0);
+    signal Addr2          : std_logic_vector(15 downto 0);
     signal RD_n_int       : std_logic;
     signal WR_n_int       : std_logic;
     signal MREQ_n_int     : std_logic;
     signal IORQ_n_int     : std_logic;
     signal RFSH_n_int     : std_logic;
     signal M1_n_int       : std_logic;
-    signal WAIT_n_int     : std_logic;
+    signal BUSAK_n_int    : std_logic;
+    signal WAIT_n_latched : std_logic;
     signal TState         : std_logic_vector(2 downto 0);
     signal SS_Single      : std_logic;
     signal SS_Step        : std_logic;
     signal SS_Step_held   : std_logic;
     signal CountCycle     : std_logic;
+    signal int_ctrl       : std_logic_vector(7 downto 0);
     signal skipNextOpcode : std_logic;
 
     signal Regs           : std_logic_vector(255 downto 0);
+    signal PdcData        : std_logic_vector(7 downto 0);
     signal io_not_mem     : std_logic;
     signal io_rd          : std_logic;
     signal io_wr          : std_logic;
@@ -124,64 +135,49 @@ type state_type is (idle, resume, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa,
     signal io_wr1         : std_logic;
     signal memory_rd1     : std_logic;
     signal memory_wr1     : std_logic;
+    signal mon_m1_n       : std_logic;
+    signal mon_xx_n       : std_logic; -- shorten MREQ and RD in M1 NOP cycle
+    signal mon_yy         : std_logic; -- delay IORQ/RD/WR in IO cycle
     signal mon_mreq_n     : std_logic;
     signal mon_iorq_n     : std_logic;
     signal mon_rfsh_n     : std_logic;
     signal mon_rd_n       : std_logic;
     signal mon_wr_n       : std_logic;
-    signal mon_wait_n     : std_logic;
+    signal mon_busak_n1   : std_logic;
+    signal mon_busak_n2   : std_logic;
+    signal mon_busak_n    : std_logic;
 
+    signal BUSRQ_n_sync   : std_logic;
     signal INT_n_sync     : std_logic;
     signal NMI_n_sync     : std_logic;
+    signal RESET_n_sync   : std_logic;
 
-    signal Rdy            : std_logic;
     signal Read_n         : std_logic;
     signal Read_n0        : std_logic;
-    signal Read_n1        : std_logic;
     signal Write_n        : std_logic;
     signal Write_n0       : std_logic;
     signal ReadIO_n       : std_logic;
     signal ReadIO_n0      : std_logic;
-    signal ReadIO_n1      : std_logic;
     signal WriteIO_n      : std_logic;
     signal WriteIO_n0     : std_logic;
     signal Sync           : std_logic;
     signal Sync0          : std_logic;
     signal Sync1          : std_logic;
-    signal Mem_IO_n       : std_logic;
-    signal nRST           : std_logic;
-
-    signal MemState       : std_logic_vector(2 downto 0);
 
     signal Din            : std_logic_vector(7 downto 0);
     signal Dout           : std_logic_vector(7 downto 0);
     signal Den            : std_logic;
     signal ex_data        : std_logic_vector(7 downto 0);
     signal rd_data        : std_logic_vector(7 downto 0);
+    signal wr_data        : std_logic_vector(7 downto 0);
     signal mon_data       : std_logic_vector(7 downto 0);
 
-    signal led3_n         : std_logic;  -- led to indicate ext trig 0 is active
-    signal led6_n         : std_logic;  -- led to indicate ext trig 1 is active
-    signal led8_n         : std_logic;  -- led to indicate CPU has hit a breakpoint (and is stopped)
-    signal sw_interrupt_n : std_logic;  -- switch to pause the CPU
-    signal sw_reset_n     : std_logic;  -- switch to reset the CPU
-
     signal avr_TxD_int    : std_logic;
 
-    signal clock_49_ctr   : std_logic_vector(23 downto 0);
-    signal clock_avr_ctr  : std_logic_vector(23 downto 0);
-
     signal rfsh_addr      : std_logic_vector(15 downto 0);
 
 begin
 
-    -- Generics allows polarity of switches/LEDs to be tweaked from the project file
-    sw_interrupt_n <= not sw1 when SW1ActiveHigh else sw1;
-    sw_reset_n     <= not sw2 when SW2ActiveHigh else sw2;
-    led3           <= not led3_n when LEDsActiveHigh else led3_n;
-    led6           <= not led6_n when LEDsActiveHigh else led6_n;
-    led8           <= not led8_n when LEDsActiveHigh else led8_n;
-
     --------------------------------------------------------
     -- Clocking
     --------------------------------------------------------
@@ -193,7 +189,7 @@ begin
         ClkPer       => ClkPer
       )
       port map(
-        CLKIN_IN     => clock49,
+        CLKIN_IN     => clock,
         CLKFX_OUT    => clock_avr
       );
 
@@ -206,8 +202,8 @@ begin
 
     mon : entity work.BusMonCore
       generic map (
-        num_comparators => 4,
-        avr_prog_mem_size => 1024 * 9
+        num_comparators => num_comparators,
+        avr_prog_mem_size => avr_prog_mem_size
       )
       port map (
         clock_avr    => clock_avr,
@@ -222,26 +218,23 @@ begin
         RdIO_n       => ReadIO_n,
         WrIO_n       => WriteIO_n,
         Sync         => Sync,
-        Rdy          => Rdy,
-        nRSTin       => RESET_n_int,
-        nRSTout      => nRST,
+        Rdy          => open,
+        nRSTin       => RESET_n_sync,
+        nRSTout      => cpu_reset_n,
         CountCycle   => CountCycle,
         trig         => trig,
-        lcd_rs       => open,
-        lcd_rw       => open,
-        lcd_e        => open,
-        lcd_db       => open,
         avr_RxD      => avr_RxD,
         avr_TxD      => avr_TxD_int,
-        sw1          => '0',
-        nsw2         => sw_reset_n,
-        led3         => led3_n,
-        led6         => led6_n,
-        led8         => led8_n,
+        sw_reset_cpu => sw_reset_cpu,
+        sw_reset_avr => sw_reset_avr,
+        led_bkpt     => led_bkpt,
+        led_trig0    => led_trig0,
+        led_trig1    => led_trig1,
         tmosi        => tmosi,
         tdin         => tdin,
         tcclk        => tcclk,
         Regs         => Regs,
+        PdcData      => PdcData,
         RdMemOut     => memory_rd,
         WrMemOut     => memory_wr,
         RdIOOut      => io_rd,
@@ -250,6 +243,7 @@ begin
         DataOut      => memory_dout,
         DataIn       => memory_din,
         Done         => memory_done,
+        int_ctrl     => int_ctrl,
         SS_Single    => SS_Single,
         SS_Step      => SS_Step
     );
@@ -258,30 +252,30 @@ begin
     -- T80
     --------------------------------------------------------
 
-    GenT80Core: if UseT80Core generate
-        inst_t80: entity work.T80a port map (
-            TS      => TState,
-            Regs    => Regs,
-            RESET_n => RESET_n_int,
-            CLK_n   => cpu_clk,
-            WAIT_n  => WAIT_n_int,
-            INT_n   => INT_n_sync,
-            NMI_n   => NMI_n_sync,
-            BUSRQ_n => BUSRQ_n,
-            M1_n    => M1_n_int,
-            MREQ_n  => MREQ_n_int,
-            IORQ_n  => IORQ_n_int,
-            RD_n    => RD_n_int,
-            WR_n    => WR_n_int,
-            RFSH_n  => RFSH_n_int,
-            HALT_n  => HALT_n,
-            BUSAK_n => BUSAK_n,
-            A       => Addr_int,
-            Din     => Din,
-            Dout    => Dout,
-            DEn     => Den
+    inst_t80: entity work.T80a port map (
+        TS      => TState,
+        Regs    => Regs,
+        PdcData => PdcData,
+        RESET_n => cpu_reset_n,
+        CLK_n   => cpu_clk,
+        CEN     => cpu_clken,
+        WAIT_n  => WAIT_n,
+        INT_n   => INT_n_sync,
+        NMI_n   => NMI_n_sync,
+        BUSRQ_n => BUSRQ_n,
+        M1_n    => M1_n_int,
+        MREQ_n  => MREQ_n_int,
+        IORQ_n  => IORQ_n_int,
+        RD_n    => RD_n_int,
+        WR_n    => WR_n_int,
+        RFSH_n  => RFSH_n_int,
+        HALT_n  => HALT_n,
+        BUSAK_n => BUSAK_n_int,
+        A       => Addr_int,
+        Din     => Din,
+        Dout    => Dout,
+        DEn     => Den
         );
-    end generate;
 
     --------------------------------------------------------
     -- Synchronise external interrupts
@@ -290,8 +284,31 @@ begin
     int_gen : process(CLK_n)
     begin
         if rising_edge(CLK_n) then
-            NMI_n_sync <= NMI_n;
-            INT_n_sync <= INT_n;
+
+            if int_ctrl(1) = '1' then
+                BUSRQ_n_sync <= int_ctrl(0);
+            else
+                BUSRQ_n_sync <= BUSRQ_n or (int_ctrl(0) and SS_single);
+            end if;
+
+            if int_ctrl(3) = '1' then
+                INT_n_sync <= int_ctrl(2);
+            else
+                INT_n_sync <= INT_n or (int_ctrl(2) and SS_single);
+            end if;
+
+            if int_ctrl(5) = '1' then
+                NMI_n_sync <= int_ctrl(4);
+            else
+                NMI_n_sync <= NMI_n or (int_ctrl(4) and SS_single);
+            end if;
+
+            if int_ctrl(7) = '1' then
+                RESET_n_sync <= int_ctrl(6);
+            else
+                RESET_n_sync <= RESET_n or (int_ctrl(6) and SS_single);
+            end if;
+
         end if;
     end process;
 
@@ -301,20 +318,16 @@ begin
 
     CountCycle <= '1' when state = idle else '0';
 
-    -- For the break point logic to work, the following must happen
-    -- SS_Single taken high by BusMonCore on the rising edge at the start of T2
-    -- WAIT_n_int must be taken low before the falling edge in the middle of T2
-    -- This implies a combinatorial path from SS_Single to WAIT_n_int
-
-    WAIT_n_int <= '0'    when state = idle and SS_Single = '1' and Sync1 = '1'            else
+    -- The breakpoint logic stops the Z80 in M1/T3 using cpu_clken
+    cpu_clken  <= '0'    when state = idle and SS_Single = '1' and Sync1 = '1'            else
                   '0'    when state /= idle                                               else
-                  WAIT_n;
+                  '1';
 
     -- Logic to ignore the second M1 in multi-byte opcodes
     skip_opcode_latch : process(CLK_n)
     begin
         if rising_edge(CLK_n) then
-            if (M1_n_int = '0' and WAIT_n_int = '1' and TState = "010") then
+            if (M1_n_int = '0' and WAIT_n_latched = '1' and TState = "010") then
                 if (skipNextOpcode = '0' and (Data = x"CB" or Data = x"DD" or Data = x"ED" or Data = x"FD")) then
                     skipNextOpcode <= '1';
                 else
@@ -327,37 +340,35 @@ begin
     -- For instruction breakpoints, we make the monitoring decision as early as possibe
     -- to allow time to stop the current instruction, which is possible because we don't
     -- really care about the data (it's re-read from memory by the disassembler).
-    Sync0    <= '1' when M1_n_int = '0' and TState = "001" and skipNextOpcode = '0' else '0';
+    Sync0    <= '1' when WAIT_n = '1' and M1_n_int = '0' and TState = "010" and skipNextOpcode = '0' else '0';
 
-    -- For memory reads/write breakpoints we make the monitoring decision in the middle of T2
-    -- but only if WAIT_n is '1' so we catch the right data.
-    Read_n0  <= not (WAIT_n_int and (not RD_n_int) and (not MREQ_n_int) and     (M1_n_int)) when TState = "010" else '1';
-    Write_n0 <= not (WAIT_n_int and (not WR_n_int) and (not MREQ_n_int) and     (M1_n_int)) when TState = "010" else '1';
-
-    ReadIO_n0  <= not (WAIT_n_int and (not RD_n_int) and (not IORQ_n_int) and     (M1_n_int)) when TState = "010" else '1';
-    WriteIO_n0 <= not (               (    RD_n_int) and (not IORQ_n_int) and     (M1_n_int)) when TState = "011" else '1';
+    -- For reads/write breakpoints we make the monitoring decision in the middle of T3
+    Read_n0    <= not ((not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "011" else '1';
+    Write_n0   <= not ((    RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "011" else '1';
+    ReadIO_n0  <= not ((not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "011" else '1';
+    WriteIO_n0 <= not ((    RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "011" else '1';
 
     -- Hold the monitoring decision so it is valid on the rising edge of the clock
-    -- For instruction fetches and writes, the monitor sees these at the start of T3
-    -- For reads, the data can arrive in the middle of T3 so delay until end of T3
+    -- For instruction fetches the monitor sees these at the end of T2
+    -- For reads and writes, the data is sampled in the middle of T3 so delay until end of T3
     watch_gen : process(CLK_n)
     begin
         if falling_edge(CLK_n) then
-            Sync     <= Sync0;
-            Read_n1  <= Read_n0;
-            Read_n   <= Read_n1;
-            Write_n  <= Write_n0;
-            ReadIO_n1  <= ReadIO_n0;
-            ReadIO_n   <= ReadIO_n1;
-            WriteIO_n  <= WriteIO_n0;
+            Sync        <= Sync0;
+            Read_n      <= Read_n0;
+            Write_n     <= Write_n0;
+            ReadIO_n    <= ReadIO_n0;
+            WriteIO_n   <= WriteIO_n0;
+            -- Latch wait seen by T80 on the falling edge, for use on the next rising edge
+            WAIT_n_latched <= WAIT_n;
         end if;
     end process;
 
-    -- Register the exec/write data on the rising at the end of T2
+    -- Register the exec data on the rising edge of the clock at the end of T2
     ex_data_latch : process(CLK_n)
     begin
         if rising_edge(CLK_n) then
-            if (Sync = '1' or Write_n = '0' or WriteIO_n = '0') then
+            if Sync = '1' then
                 ex_data <= Data;
             end if;
         end if;
@@ -367,15 +378,27 @@ begin
     rd_data_latch : process(CLK_n)
     begin
         if falling_edge(CLK_n) then
-            if (Read_n1 = '0' or ReadIO_n1 = '0') then
+            if Read_n0 = '0' or ReadIO_n0 = '0' then
                 rd_data <= Data;
             end if;
             memory_din <= Data;
         end if;
     end process;
 
+    -- Register the read data on the falling edge of clock in the middle of T3
+    wr_data_latch : process(CLK_n)
+    begin
+        if falling_edge(CLK_n) then
+            if Write_n0 = '0' or WriteIO_n0 = '0' then
+                wr_data <= Data;
+            end if;
+        end if;
+    end process;
+
     -- Mux the data seen by the bus monitor appropriately
-    mon_data <= rd_data when Read_n <= '0' or ReadIO_n = '0' else ex_data;
+    mon_data <= rd_data when Read_n = '0'  or ReadIO_n = '0'  else
+                wr_data when Write_n = '0' or WriteIO_n = '0' else
+                ex_data;
 
     -- Mark the memory access as done when t3 is reached
     memory_done <= '1' when state = rd_t3 or state = wr_t3 else '0';
@@ -384,33 +407,59 @@ begin
     -- The _int versions come from the T80
     -- The mon_ versions come from the state machine below
 
-    -- TODO: Also need to take account of BUSRQ_n/BUSAK_n
+    MREQ_n  <= MREQ_n_int  when state = idle else mon_mreq_n and mon_xx_n;
+    IORQ_n  <= IORQ_n_int  when state = idle else (mon_iorq_n or mon_yy);
+    WR_n    <= WR_n_int    when state = idle else (mon_wr_n or mon_yy);
+    RD_n    <= RD_n_int    when state = idle else (mon_rd_n or mon_yy) and mon_xx_n;
+    RFSH_n  <= RFSH_n_int  when state = idle else mon_rfsh_n;
+    M1_n    <= M1_n_int    when state = idle else mon_m1_n;
 
-    MREQ_n <= MREQ_n_int  when state = idle or state = resume else mon_mreq_n;
-    IORQ_n <= IORQ_n_int  when state = idle or state = resume else mon_iorq_n;
-    RFSH_n <= RFSH_n_int  when state = idle or state = resume else mon_rfsh_n;
-    WR_n   <= WR_n_int    when state = idle or state = resume else mon_wr_n;
-    RD_n   <= RD_n_int    when state = idle or state = resume else mon_rd_n;
-    M1_n   <= M1_n_int    when state = idle or state = resume else '1';
+    Addr1   <= x"0000"     when state = nop_t1 or state = nop_t2 else
+               rfsh_addr   when state = nop_t3 or state = nop_t4 else
+               memory_addr when state /= idle                    else
+               Addr_int;
 
-    Addr   <= Addr_int    when state = idle or state = resume else
-              x"0000"     when state = nop_t1 or state = nop_t2 else
-              rfsh_addr   when state = nop_t3 or state = nop_t4 else
-              memory_addr;
+    tristate_n <= BUSAK_n_int when state = idle else mon_busak_n1;
 
-    Data   <= memory_dout when state = wr_wa or state = wr_t2 or state = wr_t3 else
-                     Dout when state = idle and Den = '1' else
+    BUSAK_n    <= BUSAK_n_int when state = idle else mon_busak_n;
+
+    -- Force the address and databus to tristate when reset is asserted
+    tristate_ad_n <= '0'         when RESET_n_sync = '0' else
+                     BUSAK_n_int when state = idle  else
+                     mon_busak_n1;
+
+-- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1
+-- and MREQ being released at the start of T3. Otherwise, the ROM switching
+-- during NMI doesn't work reliably due to glitches. See:
+-- https://stardot.org.uk/forums/viewtopic.php?p=212096#p212096
+--
+-- Reordering the above Addr expression so Addr_int is last instead of
+-- first seems to fix the issue, but is clearly very dependent on how the Xilinx
+-- tools route the design.
+--
+-- If the problem recurs, we should switch to something like:
+--
+    addr_delay : process(clock)
+    begin
+        if rising_edge(clock) then
+            Addr2 <= Addr1;
+            Addr <= Addr2;
+        end if;
+    end process;
+
+    Data   <= memory_dout when (state = wr_t1 and io_not_mem = '1') or state = wr_wa or state = wr_t2 or state = wr_t3 else
+              Dout        when state = idle and Den = '1' else
               (others => 'Z');
 
-    DOE_n  <= '0' when state = wr_wa or state = wr_t2 or state = wr_t3 else
+    DIRD   <= '0' when (state = wr_t1 and io_not_mem = '1') or state = wr_wa or state = wr_t2 or state = wr_t3 else
               '0' when state = idle and Den = '1' else
               '1';
 
-    Din    <= Data;
+    Din <= Data;
 
-    men_access_machine_rising : process(CLK_n, RESET_n)
+    men_access_machine_rising : process(CLK_n, cpu_reset_n)
     begin
-        if (RESET_n = '0') then
+        if (cpu_reset_n = '0') then
             state <= idle;
             memory_rd1 <= '0';
             memory_wr1 <= '0';
@@ -418,6 +467,10 @@ begin
             io_wr1 <= '0';
             SS_Step_held <= '0';
             mon_rfsh_n <= '1';
+            mon_m1_n <= '1';
+            mon_xx_n <= '1';
+            mon_yy <= '0';
+            mon_busak_n1 <= '1';
 
         elsif rising_edge(CLK_n) then
 
@@ -449,7 +502,7 @@ begin
                 SS_Step_held <= '0';
             end if;
 
-            Sync1 <= Sync0;
+            Sync1 <= Sync;
 
             -- Main state machine, generating refresh, read and write cycles
             -- (the timing should exactly match those of the Z80)
@@ -457,42 +510,55 @@ begin
                 -- Idle is when T80 is running
                 when idle =>
                     if SS_Single = '1' and Sync1 = '1' then
-                        -- If the T80 is stopped, start genering refresh cycles
-                        state <= nop_t1;
                         -- Load the initial refresh address from I/R in the T80
                         rfsh_addr <= Regs(199 downto 192) & Regs(207 downto 200);
+                        -- Start genering NOP cycles
+                        mon_rfsh_n <= '0';
+                        state <= nop_t3;
                     end if;
 
-                -- Refresh cycle
+                -- NOP cycle
                 when nop_t1 =>
                     state <= nop_t2;
                     -- Increment the refresh address (7 bits, just like the Z80)
                     rfsh_addr(6 downto 0) <= rfsh_addr(6 downto 0) + 1;
+                    mon_xx_n <= mode;
                 when nop_t2 =>
-                    mon_rfsh_n <= '0';
-                    state <= nop_t3;
+                    if WAIT_n_latched = '1' then
+                        mon_m1_n <= '1';
+                        mon_xx_n <= '1';
+                        if SS_Step_held = '1' or SS_Single = '0' then
+                            state <= idle;
+                        else
+                            mon_rfsh_n <= '0';
+                            state <= nop_t3;
+                        end if;
+                    end if;
                 when nop_t3 =>
                     state <= nop_t4;
                 when nop_t4 =>
                     mon_rfsh_n <= '1';
-                    if memory_wr1 = '1' or io_wr1 = '1' then
+                    -- Sample BUSRQ_n at the *start* of the final T-state
+                    -- (hence using BUSRQ_n_sync)
+                    if BUSRQ_n_sync = '0' then
+                        state <= busack;
+                        mon_busak_n1 <= '0';
+                    elsif memory_wr1 = '1' or io_wr1 = '1' then
                         state <= wr_t1;
                         io_not_mem <= io_wr1;
+                        mon_yy <= io_wr1;
                     elsif memory_rd1 = '1' or io_rd1 = '1' then
                         state <= rd_t1;
                         io_not_mem <= io_rd1;
-                    elsif SS_Step_held = '1' or SS_Single = '0' then
-                        state <= resume;
+                        mon_yy <= io_rd1;
                     else
                         state <= nop_t1;
+                        mon_m1_n <= mode;
                     end if;
 
-                    -- Resume,
-                when resume =>
-                    state <= idle;
-
                 -- Read cycle
                 when rd_t1 =>
+                    mon_yy <= '0';
                     if io_not_mem = '1' then
                         state <= rd_wa;
                     else
@@ -501,14 +567,23 @@ begin
                 when rd_wa =>
                     state <= rd_t2;
                 when rd_t2 =>
-                    if mon_wait_n = '1' then
+                    if WAIT_n_latched = '1' then
                         state <= rd_t3;
                     end if;
                 when rd_t3 =>
-                    state <= nop_t1;
+                    -- Sample BUSRQ_n at the *start* of the final T-state
+                    -- (hence using BUSRQ_n_sync)
+                    if BUSRQ_n_sync = '0' then
+                        state <= busack;
+                        mon_busak_n1 <= '0';
+                    else
+                        state <= nop_t1;
+                        mon_m1_n <= mode;
+                    end if;
 
                 -- Write cycle
                 when wr_t1 =>
+                    mon_yy <= '0';
                     if io_not_mem = '1' then
                         state <= wr_wa;
                     else
@@ -517,16 +592,34 @@ begin
                 when wr_wa =>
                     state <= wr_t2;
                 when wr_t2 =>
-                    if mon_wait_n = '1' then
+                    if WAIT_n_latched = '1' then
                         state <= wr_t3;
                     end if;
                 when wr_t3 =>
-                    state <= nop_t1;
+                    -- Sample BUSRQ_n at the *start* of the final T-state
+                    -- (hence using BUSRQ_n_sync)
+                    if BUSRQ_n_sync = '0' then
+                        state <= busack;
+                        mon_busak_n1 <= '0';
+                    else
+                        state <= nop_t1;
+                        mon_m1_n <= mode;
+                    end if;
+
+                -- Bus Request/Ack cycle
+                when busack =>
+                    -- Release BUSAK_n on the next rising edge after BUSRQ_n seen
+                    -- (hence using BUSRQ_n)
+                    if BUSRQ_n_sync = '1' then
+                        state <= nop_t1;
+                        mon_m1_n <= mode;
+                        mon_busak_n1 <= '1';
+                    end if;
             end case;
         end if;
     end process;
 
-    men_access_machine_falling : process(RESET_n)
+    men_access_machine_falling : process(CLK_n)
     begin
         if falling_edge(CLK_n) then
             -- For memory access cycles, mreq/iorq/rd/wr all change in the middle of
@@ -541,8 +634,8 @@ begin
                     mon_mreq_n <= '1';
                     mon_iorq_n <= '0';
                 end if;
-            elsif state = nop_t3 then
-                -- Refresh cycle
+            elsif (state = nop_t1 and mode = '0') or state = nop_t3 then
+                -- M1 cycle
                 mon_mreq_n <= '0';
                 mon_iorq_n <= '1';
             else
@@ -551,51 +644,29 @@ begin
                 mon_iorq_n <= '1';
             end if;
             -- Read strobe
-            if state = rd_t1 or state = rd_wa or state = rd_t2 then
+            if (state = nop_t1 and mode = '0') or state = rd_t1 or state = rd_wa or state = rd_t2 then
                 mon_rd_n <= '0';
             else
                 mon_rd_n <= '1';
             end if;
             -- Write strobe
-            if state = wr_wa or state = wr_t2 then
+            if (state = wr_t1 and io_not_mem = '1') or state = wr_wa or state = wr_t2 then
                 mon_wr_n <= '0';
             else
                 mon_wr_n <= '1';
             end if;
-            -- Sample wait on the falling edge of the clock
-            mon_wait_n <= WAIT_n;
+            -- Half-cycle delayed version of BUSRQ_n_sync
+            mon_busak_n2 <= BUSRQ_n_sync;
         end if;
     end process;
 
-
-    RESET_n_int <= RESET_n and sw_interrupt_n and nRST;
+    mon_busak_n <= mon_busak_n1 or mon_busak_n2;
 
     avr_TxD <= avr_Txd_int;
 
-    test1 <= sw_interrupt_n and sw_reset_n;
-
-    process(clock_avr)
-    begin
-        if rising_edge(clock_avr) then
-            clock_avr_ctr <= clock_avr_ctr + 1;
-            test2 <= sw_interrupt_n or clock_avr_ctr(23);
-        end if;
-    end process;
-
-    process(clock49)
-    begin
-        if rising_edge(clock49) then
-            clock_49_ctr <= clock_49_ctr + 1;
-            test3 <= sw_reset_n or clock_49_ctr(23);
-        end if;
-    end process;
-
-    test4 <= not avr_TxD_int;
-
-    --test1 <= TState(0);
-    --test2 <= TState(1);
-    --test3 <= TState(2);
-    --test4 <= CLK_n;
-
+    test1 <= Sync1;
+    test2 <= TState(0);
+    test3 <= TState(1);
+    test4 <= TState(2);
 
 end behavioral;

src/Z80CpuMonALS.vhd

@@ -21,6 +21,10 @@ use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 
 entity Z80CpuMonALS is
+    generic (
+        num_comparators   : integer := 8;        -- default value for lx9core board
+        avr_prog_mem_size : integer := 1024 * 16 -- default value for lx9core board
+        );
     port (
         clock           : in    std_logic;
 
@@ -75,90 +79,128 @@ entity Z80CpuMonALS is
         tcclk           : out   std_logic;
 
         -- Optional Debugging signals
-        test1           : out   std_logic;
-        test2           : out   std_logic;
-        test3           : out   std_logic;
-        test4           : out   std_logic
+        test            : out   std_logic_vector(9 downto 0)
 
-    );
+        );
 end Z80CpuMonALS;
 
 architecture behavioral of Z80CpuMonALS is
 
-    signal BUSAK_n_int : std_logic;
-    signal WR_n_int    : std_logic;
-    signal DOE_n       : std_logic;
+    signal MREQ_n_int   : std_logic;
+    signal IORQ_n_int   : std_logic;
+    signal M1_n_int     : std_logic;
+    signal RD_n_int     : std_logic;
+    signal WR_n_int     : std_logic;
+    signal RFSH_n_int   : std_logic;
+    signal HALT_n_int   : std_logic;
+    signal BUSAK_n_int  : std_logic;
+    signal tristate_n   : std_logic;
+    signal tristate_ad_n: std_logic;
 
+    signal sw_reset_cpu : std_logic;
+    signal sw_reset_avr : std_logic;
+    signal led_bkpt     : std_logic;
+    signal led_trig0    : std_logic;
+    signal led_trig1    : std_logic;
+
+    signal TState       : std_logic_vector(2 downto 0);
 begin
 
-    BUSAK_n <= BUSAK_n_int;
+    sw_reset_cpu <= not sw1;
+    sw_reset_avr <= not sw2;
+    led1         <= led_bkpt;
+    led2         <= led_trig0;
+    led3         <= led_trig1;
+
+    MREQ_n  <= MREQ_n_int;
+    IORQ_n  <= IORQ_n_int;
+    M1_n    <= M1_n_int;
+    RD_n    <= RD_n_int;
     WR_n    <= WR_n_int;
+    RFSH_n  <= RFSH_n_int;
+    HALT_n  <= HALT_n_int;
+    BUSAK_n <= BUSAK_n_int;
 
-    OEC_n   <= not BUSAK_n_int;
-    OEA1_n  <= not BUSAK_n_int;
-    OEA2_n  <= not BUSAK_n_int;
-
-    OED_n   <= not BUSAK_n_int;
-    DIRD    <= DOE_n;
+    OEC_n   <= not tristate_n;
+    OEA1_n  <= not tristate_ad_n;
+    OEA2_n  <= not tristate_ad_n;
+    OED_n   <= not tristate_ad_n;
 
     wrapper : entity work.Z80CpuMon
         generic map (
-            UseT80Core     => true,
-            LEDsActiveHigh => true,
-            SW1ActiveHigh  => false,
-            SW2ActiveHigh  => false,
-            ClkMult        => 8,
-            ClkDiv         => 25,
-            ClkPer         => 20.000
+            ClkMult           => 12,
+            ClkDiv            => 25,
+            ClkPer            => 20.000,
+            num_comparators   => num_comparators,
+            avr_prog_mem_size => avr_prog_mem_size
             )
-      port map (
-          clock49         => clock,
+        port map (
+            clock             => clock,
 
-          -- Z80 Signals
-          RESET_n         => RESET_n,
-          CLK_n           => CLK_n,
-          WAIT_n          => WAIT_n,
-          INT_n           => INT_n,
-          NMI_n           => NMI_n,
-          BUSRQ_n         => BUSRQ_n,
-          M1_n            => M1_n,
-          MREQ_n          => MREQ_n,
-          IORQ_n          => IORQ_n,
-          RD_n            => RD_n,
-          WR_n            => WR_n_int,
-          RFSH_n          => RFSH_n,
-          HALT_n          => HALT_n,
-          BUSAK_n         => BUSAK_n_int,
-          Addr            => Addr,
-          Data            => Data,
-          DOE_n           => DOE_n,
+            -- Z80 Signals
+            RESET_n           => RESET_n,
+            CLK_n             => CLK_n,
+            WAIT_n            => WAIT_n,
+            INT_n             => INT_n,
+            NMI_n             => NMI_n,
+            BUSRQ_n           => BUSRQ_n,
+            M1_n              => M1_n_int,
+            MREQ_n            => MREQ_n_int,
+            IORQ_n            => IORQ_n_int,
+            RD_n              => RD_n_int,
+            WR_n              => WR_n_int,
+            RFSH_n            => RFSH_n_int,
+            HALT_n            => HALT_n_int,
+            BUSAK_n           => BUSAK_n_int,
+            Addr              => Addr,
+            Data              => Data,
 
-          -- External trigger inputs
-          trig            => trig,
+            -- Buffer Control Signals
+            DIRD              => DIRD,
+            tristate_n        => tristate_n,
+            tristate_ad_n     => tristate_ad_n,
 
-          -- Serial Console
-          avr_RxD         => avr_RxD,
-          avr_TxD         => avr_TxD,
+            -- Mode jumper, tie low to generate NOPs when paused
+            mode              => mode,
 
-          -- Switches
-          sw1             => sw1,
-          sw2             => sw2,
+            -- External trigger inputs
+            trig              => trig,
 
-          -- LEDs
-          led3            => led2, -- trig 0
-          led6            => led3, -- trig 1
-          led8            => led1, -- break
+            -- Serial Console
+            avr_RxD           => avr_RxD,
+            avr_TxD           => avr_TxD,
 
-          -- OHO_DY1 connected to test connector
-          tmosi           => tmosi,
-          tdin            => tdin,
-          tcclk           => tcclk,
+            -- Switches
+            sw_reset_cpu      => sw_reset_cpu,
+            sw_reset_avr      => sw_reset_avr,
 
-          -- Debugging signals
-          test1           => test1,
-          test2           => test2,
-          test3           => test3,
-          test4           => test4
-          );
+            -- LEDs
+            led_bkpt          => led_bkpt,
+            led_trig0         => led_trig0,
+            led_trig1         => led_trig1,
+
+            -- OHO_DY1 connected to test connector
+            tmosi             => tmosi,
+            tdin              => tdin,
+            tcclk             => tcclk,
+
+            -- Debugging signals
+            test1             => open,
+            test2             => TState(0),
+            test3             => TState(1),
+            test4             => TSTate(2)
+            );
+
+    -- Test outputs
+    test(0) <= M1_n_int;
+    test(1) <= RD_n_int;
+    test(2) <= WR_n_int;
+    test(3) <= MREQ_n_int;
+    test(4) <= IORQ_n_int;
+    test(5) <= WAIT_n;
+    test(6) <= CLK_n;
+    test(7) <= TState(2);
+    test(8) <= TState(1);
+    test(9) <= TState(0);
 
 end behavioral;

src/Z80CpuMonGODIL.vhd

@@ -0,0 +1,178 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : Z80CpuMonGODIL.vhd
+-- /___/   /\     Timestamp : 14/10/2018
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: Z80CpuMonGODIL
+--Device: XC3S500E
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity Z80CpuMonGODIL is
+    generic (
+        num_comparators   : integer := 8;        -- default value correct for GODIL
+        avr_prog_mem_size : integer := 1024 * 16 -- default value correct for GODIL
+        );
+    port (
+        clock49         : in    std_logic;
+
+        -- Z80 Signals
+        RESET_n         : in    std_logic;
+        CLK_n           : in    std_logic;
+        WAIT_n          : in    std_logic;
+        INT_n           : in    std_logic;
+        NMI_n           : in    std_logic;
+        BUSRQ_n         : in    std_logic;
+        M1_n            : out   std_logic;
+        MREQ_n          : out   std_logic;
+        IORQ_n          : out   std_logic;
+        RD_n            : out   std_logic;
+        WR_n            : out   std_logic;
+        RFSH_n          : out   std_logic;
+        HALT_n          : out   std_logic;
+        BUSAK_n         : out   std_logic;
+        Addr            : out   std_logic_vector(15 downto 0);
+        Data            : inout std_logic_vector(7 downto 0);
+
+        -- Mode jumper, tie low to generate NOPs when paused
+        mode            : in    std_logic;
+
+        -- External trigger inputs
+        trig            : in    std_logic_vector(1 downto 0);
+
+        -- Serial Console
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
+
+        -- GODIL Switches
+        sw1             : in    std_logic;
+        sw2             : in    std_logic;
+
+        -- GODIL LEDs
+        led3            : out   std_logic;
+        led6            : out   std_logic;
+        led8            : out   std_logic;
+
+        -- OHO_DY1 connected to test connector
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
+
+        -- Debugging signals
+        test1           : out   std_logic;
+        test2           : out   std_logic;
+        test3           : out   std_logic;
+        test4           : out   std_logic
+
+        );
+end Z80CpuMonGODIL;
+
+architecture behavioral of Z80CpuMonGODIL is
+
+    signal sw_reset_avr : std_logic;
+    signal sw_reset_cpu : std_logic;
+    signal led_bkpt     : std_logic;
+    signal led_trig0    : std_logic;
+    signal led_trig1    : std_logic;
+
+    signal MREQ_n_int   : std_logic;
+    signal IORQ_n_int   : std_logic;
+    signal RD_n_int     : std_logic;
+    signal WR_n_int     : std_logic;
+    signal Addr_int     : std_logic_vector(15 downto 0);
+
+    signal tristate_n   : std_logic;
+    signal tristate_ad_n: std_logic;
+
+begin
+    sw_reset_cpu <= sw1;
+    sw_reset_avr <= not sw2;
+    led3         <= not led_trig0;
+    led6         <= not led_trig1;
+    led8         <= not led_bkpt;
+
+    -- Tristateable output drivers
+    MREQ_n <= 'Z'             when tristate_n = '0' else MREQ_n_int;
+    IORQ_n <= 'Z'             when tristate_n = '0' else IORQ_n_int;
+    RD_n   <= 'Z'             when tristate_n = '0' else RD_n_int;
+    WR_n   <= 'Z'             when tristate_n = '0' else WR_n_int;
+    Addr   <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
+
+    wrapper : entity work.Z80CpuMon
+        generic map (
+            ClkMult           => 10,
+            ClkDiv            => 31,
+            ClkPer            => 20.345,
+            num_comparators   => num_comparators,
+            avr_prog_mem_size => avr_prog_mem_size
+            )
+        port map(
+            clock           =>  clock49,
+
+            -- Z80 Signals
+            RESET_n         =>  RESET_n,
+            CLK_n           =>  CLK_n,
+            WAIT_n          =>  WAIT_n,
+            INT_n           =>  INT_n,
+            NMI_n           =>  NMI_n,
+            BUSRQ_n         =>  BUSRQ_n,
+            M1_n            =>  M1_n,
+            MREQ_n          =>  MREQ_n_int,
+            IORQ_n          =>  IORQ_n_int,
+            RD_n            =>  RD_n_int,
+            WR_n            =>  WR_n_int,
+            RFSH_n          =>  RFSH_n,
+            HALT_n          =>  HALT_n,
+            BUSAK_n         =>  BUSAK_n,
+            Addr            =>  Addr_int,
+            Data            =>  Data,
+
+            -- Buffer Control Signals
+            tristate_n      =>  tristate_n,
+            tristate_ad_n   =>  tristate_ad_n,
+            DIRD            =>  open,
+
+            -- Mode jumper, tie low to generate NOPs when paused
+            mode            =>  mode,
+
+            -- External trigger inputs
+            trig            =>  trig,
+
+            -- Serial Console
+            avr_RxD         =>  avr_RxD,
+            avr_TxD         =>  avr_TxD,
+
+            -- Switches
+            sw_reset_cpu    => sw_reset_cpu,
+            sw_reset_avr    => sw_reset_avr,
+
+            -- LEDs
+            led_bkpt        => led_bkpt,
+            led_trig0       => led_trig0,
+            led_trig1       => led_trig1,
+
+            -- OHO_DY1 connected to test connector
+            tmosi           =>  tmosi,
+            tdin            =>  tdin,
+            tcclk           =>  tcclk,
+
+            -- Debugging signals
+            test1           =>  test1,
+            test2           =>  test2,
+            test3           =>  test3,
+            test4           =>  test4
+            );
+
+end behavioral;

src/Z80CpuMonLX9.vhd

@@ -0,0 +1,179 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 2019 David Banks
+--
+--------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/
+--  \   \
+--  /   /         Filename  : Z80CpuMonLX9.vhd
+-- /___/   /\     Timestamp : 14/10/2018
+-- \   \  /  \
+--  \___\/\___\
+--
+--Design Name: Z80CpuMonLX9
+--Device: XC6SLX9
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity Z80CpuMonLX9 is
+    generic (
+        num_comparators   : integer := 8;        -- default value correct for LX9
+        avr_prog_mem_size : integer := 1024 * 16 -- default value correct for LX9
+        );
+    port (
+        clock           : in    std_logic;
+
+        -- Z80 Signals
+        RESET_n         : in    std_logic;
+        CLK_n           : in    std_logic;
+        WAIT_n          : in    std_logic;
+        INT_n           : in    std_logic;
+        NMI_n           : in    std_logic;
+        BUSRQ_n         : in    std_logic;
+        M1_n            : out   std_logic;
+        MREQ_n          : out   std_logic;
+        IORQ_n          : out   std_logic;
+        RD_n            : out   std_logic;
+        WR_n            : out   std_logic;
+        RFSH_n          : out   std_logic;
+        HALT_n          : out   std_logic;
+        BUSAK_n         : out   std_logic;
+        Addr            : out   std_logic_vector(15 downto 0);
+        Data            : inout std_logic_vector(7 downto 0);
+
+        -- Mode jumper, tie low to generate NOPs when paused
+        mode            : in    std_logic;
+
+        -- External trigger inputs
+        trig            : in    std_logic_vector(1 downto 0);
+
+        -- Serial Console
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
+
+        -- LX9 Switches
+        sw1             : in    std_logic;
+        sw2             : in    std_logic;
+
+        -- LX9 LEDs
+        led3            : out   std_logic;
+        led6            : out   std_logic;
+        led8            : out   std_logic;
+
+        -- OHO_DY1 connected to test connector
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
+
+        -- Debugging signals
+        test1           : out   std_logic;
+        test2           : out   std_logic;
+        test3           : out   std_logic;
+        test4           : out   std_logic
+
+        );
+end Z80CpuMonLX9;
+
+architecture behavioral of Z80CpuMonLX9 is
+
+    signal sw_reset_avr : std_logic;
+    signal sw_reset_cpu : std_logic;
+    signal led_bkpt     : std_logic;
+    signal led_trig0    : std_logic;
+    signal led_trig1    : std_logic;
+
+    signal MREQ_n_int   : std_logic;
+    signal IORQ_n_int   : std_logic;
+    signal RD_n_int     : std_logic;
+    signal WR_n_int     : std_logic;
+    signal Addr_int     : std_logic_vector(15 downto 0);
+
+    signal tristate_n   : std_logic;
+    signal tristate_ad_n: std_logic;
+
+begin
+
+    sw_reset_cpu <= sw1;
+    sw_reset_avr <= sw2;
+    led3         <= led_trig0;
+    led6         <= led_trig1;
+    led8         <= led_bkpt;
+
+    -- Tristateable output drivers
+    MREQ_n <= 'Z'             when tristate_n = '0' else MREQ_n_int;
+    IORQ_n <= 'Z'             when tristate_n = '0' else IORQ_n_int;
+    RD_n   <= 'Z'             when tristate_n = '0' else RD_n_int;
+    WR_n   <= 'Z'             when tristate_n = '0' else WR_n_int;
+    Addr   <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
+
+    wrapper : entity work.Z80CpuMon
+        generic map (
+            ClkMult           => 8,
+            ClkDiv            => 25,
+            ClkPer            => 20.000,
+            num_comparators   => num_comparators,
+            avr_prog_mem_size => avr_prog_mem_size
+            )
+        port map(
+            clock           =>  clock,
+
+            -- Z80 Signals
+            RESET_n         =>  RESET_n,
+            CLK_n           =>  CLK_n,
+            WAIT_n          =>  WAIT_n,
+            INT_n           =>  INT_n,
+            NMI_n           =>  NMI_n,
+            BUSRQ_n         =>  BUSRQ_n,
+            M1_n            =>  M1_n,
+            MREQ_n          =>  MREQ_n_int,
+            IORQ_n          =>  IORQ_n_int,
+            RD_n            =>  RD_n_int,
+            WR_n            =>  WR_n_int,
+            RFSH_n          =>  RFSH_n,
+            HALT_n          =>  HALT_n,
+            BUSAK_n         =>  BUSAK_n,
+            Addr            =>  Addr_int,
+            Data            =>  Data,
+
+            -- Buffer Control Signals
+            tristate_n      =>  tristate_n,
+            tristate_ad_n   =>  tristate_ad_n,
+            DIRD            =>  open,
+
+            -- Mode jumper, tie low to generate NOPs when paused
+            mode            =>  mode,
+
+            -- External trigger inputs
+            trig            =>  trig,
+
+            -- Serial Console
+            avr_RxD         =>  avr_RxD,
+            avr_TxD         =>  avr_TxD,
+
+            -- Switches
+            sw_reset_cpu    => sw_reset_cpu,
+            sw_reset_avr    => sw_reset_avr,
+
+            -- LEDs
+            led_bkpt        => led_bkpt,
+            led_trig0       => led_trig0,
+            led_trig1       => led_trig1,
+
+            -- OHO_DY1 connected to test connector
+            tmosi           =>  tmosi,
+            tdin            =>  tdin,
+            tcclk           =>  tcclk,
+
+            -- Debugging signals
+            test1           =>  test1,
+            test2           =>  test2,
+            test3           =>  test3,
+            test4           =>  test4
+            );
+
+end behavioral;

target/Makefile

@@ -1,4 +1,4 @@
-SUB_DIRS = godil_250 godil_500 lx9_jason lx9_jason_flipped
+SUB_DIRS = lx9_dave godil_250 godil_500 lx9_jason lx9_jason_flipped
 
 build:
 	for dir in $(SUB_DIRS); do \

target/common/Makefile.inc

@@ -8,6 +8,10 @@ SHELL      := env PATH=$(PATH) /bin/bash
 # Frequency of the AVR CPU
 F_CPU       ?= 15855484
 
+# Default Baud Rate of serial interface
+# Note: F_CPU / 16 / BAUD need to be close to an integer
+BAUD        ?= 57600
+
 # Path of the back anotated block memory map file
 BMM_FILE    ?= memory_bd.bmm
 
@@ -18,14 +22,15 @@ OBJCOPY=avr-objcopy
 
 PROG = avr_progmem
 
-CFLAGS=$(CPU_CFLAGS) -DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
+CFLAGS=$(CPU_CFLAGS) -DF_CPU=${F_CPU}UL -DBAUD=${BAUD} -std=c99 -mmcu=$(MCU) -Wall -Os -mcall-prologues
 
-OBJECTS=AtomBusMon.o status.o $(CPU_OBJECTS) 
+OBJECTS=AtomBusMon.o status.o $(CPU_OBJECTS)
 
 build: $(TARGET).mcs
 
 $(TARGET).mcs: $(TARGET).bit
 	promgen -u 0 $(TARGET).bit -o $(TARGET).mcs -p mcs -w -spi -s 8192
+	promgen -u 0 $(TARGET).bit -o $(TARGET).bin -p bin -w -spi -s 8192
 	rm -f $(TARGET).cfi $(TARGET).prm
 
 working/$(PROJECT).bit:
@@ -37,25 +42,23 @@ working/$(PROJECT).bit:
 $(TARGET).bit: $(PROG).mem working/$(PROJECT).bit
 	data2mem -bm $(BMM_FILE) -bd $(PROG).mem -bt working/$(PROJECT).bit -o b $(TARGET).bit
 
-$(PROG).mem: $(PROG).hex
-	srec_cat  $< -Intel -Byte_Swap 2  -Data_Only -o tmp.mem -vmem 8
-	gawk ' BEGIN{FS=" ";} { $$1= ""; print}' tmp.mem > $@
-	rm tmp.mem
+$(PROG).mem: $(PROG).bin
+	od -An -tx1 -w16 -v <$(PROG).bin >$(PROG).mem
 
-$(PROG).hex : $(PROG).out 
-	$(OBJCOPY) -R .eeprom -O ihex $(PROG).out $(PROG).hex 
+$(PROG).bin : $(PROG).out
+	$(OBJCOPY) -R .comment --reverse-bytes=2 -O binary $(PROG).out $(PROG).bin
 
 $(PROG).out : $(OBJECTS)
 	$(CC) $(CFLAGS) -o $(PROG).out -Wl,-Map,$(PROG).map $^
 
-%.o : %.c 
+%.o : %.c
 	$(CC) $(CFLAGS) -Os -c $<
 
 %.o : %.S
 	$(CC) $(CFLAGS) -Os -c $<
 
 clean:
-	rm -f $(TARGET).bit $(TARGET).mcs $(PROG).mem $(PROG).hex $(PROG).out $(PROG).map *.o
+	rm -f $(TARGET).bit $(TARGET).mcs $(PROG).mem $(PROG).bin $(PROG).out $(PROG).map *.o
 
 clobber: clean
-	rm -rf $(BMM_FILE) working/ iceconfig/
+	rm -rf $(BMM_FILE) working/ iseconfig/

target/common/Makefile_ice6502.inc

@@ -1,5 +1,5 @@
 # CPU specfic build flags
-CPU_CFLAGS = -DCPU=6502 -DCPUEMBEDDED 
+CPU_CFLAGS = -DCPU_6502
 
 # CPU specfic object files
-CPU_OBJECTS = dis6502.o regs6502.o 
+CPU_OBJECTS = dis6502.o regs6502.o

target/common/Makefile_ice6502fast.inc

@@ -1,5 +0,0 @@
-# CPU specfic build flags
-CPU_CFLAGS = -DCPU=6502 -DCPUEMBEDDED 
-
-# CPU specfic object files
-CPU_OBJECTS = dis6502.o regs6502.o 

target/common/Makefile_ice6502mon.inc

@@ -1,5 +0,0 @@
-# CPU specfic build flags
-CPU_CFLAGS = -DCPU=6502
-
-# CPU specfic object files
-CPU_OBJECTS = hd44780.o 

target/common/Makefile_ice65c02.inc

@@ -0,0 +1,5 @@
+# CPU specfic build flags
+CPU_CFLAGS = -DCPU_65C02
+
+# CPU specfic object files
+CPU_OBJECTS = dis65c02.o regs6502.o

target/common/Makefile_ice6809.inc

@@ -1,5 +1,5 @@
 # CPU specfic build flags
-CPU_CFLAGS = -DCPU=6809 -DCPUEMBEDDED 
+CPU_CFLAGS = -DCPU_6809
 
 # CPU specfic object files
-CPU_OBJECTS = dis6809.o regs6809.o 
+CPU_OBJECTS = dis6809.o regs6809.o

target/common/Makefile_icez80.inc

@@ -1,5 +1,5 @@
 # CPU specfic build flags
-CPU_CFLAGS = -DCPU=Z80 -DCPUEMBEDDED 
+CPU_CFLAGS = -DCPU_Z80
 
 # CPU specfic object files
-CPU_OBJECTS = disz80.o regsz80.o 
+CPU_OBJECTS = disz80.o regsz80.o

target/common/Makefile_loader.inc

@@ -0,0 +1,18 @@
+XILINX      ?= /opt/Xilinx/14.7
+
+PATH       := $(PATH):${XILINX}/ISE_DS/ISE/bin/lin64:${PAPILIO}/linux64
+SHELL      := env PATH=$(PATH) /bin/bash
+
+build: $(TARGET).bit
+
+$(TARGET).bit:
+	# create a working directory if necessary
+	mkdir -p working
+	# use the xilinx tools to synthesise the project and generate a bitstream file
+	xtclsh $(COMMON)/ise_build.tcl $(TARGET).xise
+	cp working/$(TARGET).bit $(TARGET).bit
+
+clean:
+	rm -rf working/ iceconfig/
+
+clobber: clean

target/godil_250/_icez80/board.ucf

@@ -0,0 +1,78 @@
+
+NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "clock49"  LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator
+
+NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1
+NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 2
+NET "Addr<13>" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 3
+NET "Addr<14>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 4
+NET "Addr<15>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 5
+NET "CLK_n"    LOC="P22" | IOSTANDARD = LVCMOS33 | PERIOD = 125.00ns       ; # Z80 pin 6
+NET "Data<4>"  LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 7
+NET "Data<3>"  LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 8
+NET "Data<5>"  LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 9
+NET "Data<6>"  LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 10
+#NET "VCC"     LOC="P40" | IOSTANDARD = LVCMOS33                           ; # Z80 pin 11
+NET "Data<2>"  LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 12
+NET "Data<7>"  LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 13
+NET "Data<0>"  LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 14
+NET "Data<1>"  LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 15
+NET "INT_n"    LOC="P54" | IOSTANDARD = LVCMOS33                           ; # Z80 pin 16
+NET "NMI_n"    LOC="P57" | IOSTANDARD = LVCMOS33                           ; # Z80 pin 17
+NET "HALT_n"   LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 18
+NET "MREQ_n"   LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 19
+NET "IORQ_n"   LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 20
+NET "RD_n"     LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 21
+NET "WR_n"     LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 22
+NET "BUSAK_n"  LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 23
+NET "WAIT_n"   LOC="P71" | IOSTANDARD = LVCMOS33                           ; # Z80 pin 24
+NET "BUSRQ_n"  LOC="P86" | IOSTANDARD = LVCMOS33                           ; # Z80 pin 25
+NET "RESET_n"  LOC="P84" | IOSTANDARD = LVCMOS33                           ; # Z80 pin 26
+NET "M1_n"     LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 27
+NET "RFSH_n"   LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 28
+#NET "GND"     LOC="P79" | IOSTANDARD = LVCMOS33                           ; # Z80 pin 29
+NET "Addr<0>"  LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 30
+NET "Addr<1>"  LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 31
+NET "Addr<2>"  LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 32
+NET "Addr<3>"  LOC="P3"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 33
+NET "Addr<4>"  LOC="P2"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 34
+NET "Addr<5>"  LOC="P4"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 35
+NET "Addr<6>"  LOC="P5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 36
+NET "Addr<7>"  LOC="P90" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 37
+NET "Addr<8>"  LOC="P9"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 38
+NET "Addr<9>"  LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 39
+NET "Addr<10>" LOC="P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 40
+
+NET "led3"     LOC="P43" | IOSTANDARD = LVCMOS33                           ; # Red LED (near SW1)
+NET "led6"     LOC="P25" | IOSTANDARD = LVCMOS33                           ; # Red LED (just left of FPGA)
+NET "led8"     LOC="P47" | IOSTANDARD = LVCMOS33                           ; # Green LED (near SW1)
+NET "sw1"      LOC="P39" | IOSTANDARD = LVCMOS33                           ; # Left Switch
+NET "sw2"      LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP                  ; # Right Switch
+
+# I/O's for test connector
+#NET tvs1      LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2
+#NET tvs0      LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3
+NET tmosi      LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4
+NET tdin       LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5
+NET tcclk      LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6
+#NET tm1       LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7
+#NET thsw      LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8
+
+NET "avr_TxD"  LOC="P26" | IOSTANDARD = LVCMOS33 ;
+NET "avr_RxD"  LOC="P15" | IOSTANDARD = LVCMOS33 ;
+
+NET "trig<0>"  LOC="P62" | IOSTANDARD = LVCMOS33 ;
+NET "trig<1>"  LOC="P63" | IOSTANDARD = LVCMOS33 ;
+
+NET "test1"    LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test2"    LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test3"    LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test4"    LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# This input controls whether the idle mode includes M1 cycles
+NET "mode"     LOC="P88" | IOSTANDARD = LVCMOS33 | PULLUP;

target/godil_250/_icez80/icez80.xise

@@ -32,11 +32,11 @@
     </file>
     <file xil_pn:name="../../../src/T80/T80_ALU.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
     </file>
     <file xil_pn:name="../../../src/T80/T80_MCode.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
     </file>
     <file xil_pn:name="../../../src/T80/T80_Reg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
@@ -44,7 +44,7 @@
     </file>
     <file xil_pn:name="../../../src/T80/T80_Pack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
     </file>
     <file xil_pn:name="../../../src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
@@ -60,7 +60,7 @@
     </file>
     <file xil_pn:name="../ipcore/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/CommonPacks/avr_adr_pack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
@@ -72,7 +72,7 @@
     </file>
     <file xil_pn:name="../../../src/AVR8/CommonPacks/spi_mod_comp_pack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/CommonPacks/std_library.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
@@ -92,7 +92,7 @@
     </file>
     <file xil_pn:name="../../../src/AVR8/Core/avr_core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/Core/bit_processor.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
@@ -124,7 +124,7 @@
     </file>
     <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
@@ -156,11 +156,11 @@
     </file>
     <file xil_pn:name="../../../src/AVR8/MemArbAndMux/ArbiterAndMux.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemAccessCompPack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
@@ -168,15 +168,15 @@
     </file>
     <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemRdMux.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/Peripheral/SynchronizerCompPack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
@@ -192,11 +192,11 @@
     </file>
     <file xil_pn:name="../../../src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
@@ -208,19 +208,19 @@
     </file>
     <file xil_pn:name="../../../src/AVR8/spi_mod/spi_mod.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
@@ -228,34 +228,38 @@
     </file>
     <file xil_pn:name="../../../src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/uC/RAMDataReg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
     </file>
     <file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../../../src/oho_dy1/OhoPack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
     </file>
     <file xil_pn:name="../../../src/AVR8/Memory/XPM_Xilinx.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+    </file>
+    <file xil_pn:name="../../../src/Z80CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
     </file>
     <file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -365,9 +369,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Z80CpuMon|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/Z80CpuMon.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Z80CpuMon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Z80CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/Z80CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Z80CpuMonGODIL" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -425,7 +429,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="Z80CpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="Z80CpuMonGODIL" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -437,10 +441,10 @@
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Z80CpuMon_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Z80CpuMon_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Z80CpuMon_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Z80CpuMon_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Z80CpuMonGODIL_translate.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@@ -460,7 +464,7 @@
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Z80CpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Z80CpuMonGODIL" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>

target/godil_250/_icez80/memory.bmm

@@ -0,0 +1,42 @@
+ADDRESS_MAP avrmap PPC405 0
+
+    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+        END_BUS_BLOCK;
+
+        BUS_BLOCK
+	    wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
+        END_BUS_BLOCK;
+
+    END_ADDRESS_SPACE;
+
+END_ADDRESS_MAP;

target/godil_250/ice6502/Makefile

@@ -5,7 +5,7 @@ ROOT       = ../../..
 COMMON     = ../../common
 
 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = AtomCpuMon
+PROJECT    = MOS6502CpuMonGODIL
 
 # The target .bit file to be generated including the monitor program
 TARGET     = ice6502

target/godil_250/ice6502/board.ucf

@@ -2,81 +2,72 @@ NET "clock49" TNM_NET = clk_period_grp_49;
 TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
 
 NET "Phi0" TNM_NET = clk_period_grp_phi0;
-TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 500ns LOW;
+TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
 
-NET "clock49"  LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
-#NET "VSS"      LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
-#NET "Rdy"      LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
-NET "Phi1"     LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
-NET "IRQ_n"    LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 4
-#NET "NC"      LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
-NET "NMI_n"    LOC="P22" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 6
-NET "Sync"     LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
-#NET "VCC"     LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
-NET "Addr<0>"  LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
-NET "Addr<1>"  LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
-NET "Addr<2>"  LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
-NET "Addr<3>"  LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
-NET "Addr<4>"  LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
-NET "Addr<5>"  LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
-NET "Addr<6>"  LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
-NET "Addr<7>"  LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
-NET "Addr<8>"  LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
-NET "Addr<9>"  LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
-NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
-NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
 
-#NET "VSS"     LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
-NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
-NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
-NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
-NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
-NET "Data<7>"  LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
-NET "Data<6>"  LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
-NET "Data<5>"  LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
-NET "Data<4>"  LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
-NET "Data<3>"  LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
-NET "Data<2>"  LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
-NET "Data<1>"  LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
-NET "Data<0>"  LOC="P3"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
-NET "R_W_n"    LOC="P2"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
-#NET "NC"      LOC="P4"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
-#NET "NC"      LOC="P5"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
-NET "Phi0"     LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37
-NET "SO_n"     LOC="P9"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
-NET "Phi2"     LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
-NET "Res_n"    LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
+NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33                           ; # 49.152 MHz Oscillator
+#NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 1
+NET "Rdy"        LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 2
+NET "Phi1"       LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 3
+NET "IRQ_n"      LOC="P17" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 4
+#NET "NC"        LOC="P94" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 5
+NET "NMI_n"      LOC="P22" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 6
+NET "Sync"       LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 7
+#NET "VCC"       LOC="P33" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 8
+NET "Addr<0>"    LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 9
+NET "Addr<1>"    LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 10
+NET "Addr<2>"    LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 11
+NET "Addr<3>"    LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 12
+NET "Addr<4>"    LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 13
+NET "Addr<5>"    LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 14
+NET "Addr<6>"    LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 15
+NET "Addr<7>"    LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 16
+NET "Addr<8>"    LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 17
+NET "Addr<9>"    LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 18
+NET "Addr<10>"   LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 19
+NET "Addr<11>"   LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 20
 
-NET "led3"       LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
-NET "led6"       LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
-NET "led8"       LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
-NET "sw1"        LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
-NET "sw2"        LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
+#NET "VSS"       LOC="P67" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 21
+NET "Addr<12>"   LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 22
+NET "Addr<13>"   LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 23
+NET "Addr<14>"   LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 24
+NET "Addr<15>"   LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 25
+NET "Data<7>"    LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 26
+NET "Data<6>"    LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 27
+NET "Data<5>"    LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 28
+NET "Data<4>"    LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 29
+NET "Data<3>"    LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 30
+NET "Data<2>"    LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 31
+NET "Data<1>"    LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 32
+NET "Data<0>"    LOC="P3"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 33
+NET "R_W_n"      LOC="P2"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 34
+#NET "NC"        LOC="P4"  | IOSTANDARD = LVCMOS33                           ; # 6502 pin 35
+#NET "NC"        LOC="P5"  | IOSTANDARD = LVCMOS33                           ; # 6502 pin 36
+NET "Phi0"       LOC="P90" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 37
+NET "SO_n"       LOC="P9"  | IOSTANDARD = LVCMOS33                           ; # 6502 pin 38
+NET "Phi2"       LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 39
+NET "Res_n"      LOC="P11" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 40
+
+NET "led3"       LOC="P43" | IOSTANDARD = LVCMOS33                           ; # Red LED (near SW1)
+NET "led6"       LOC="P25" | IOSTANDARD = LVCMOS33                           ; # Red LED (just left of FPGA)
+NET "led8"       LOC="P47" | IOSTANDARD = LVCMOS33                           ; # Green LED (near SW1)
+NET "sw1"        LOC="P39" | IOSTANDARD = LVCMOS33                           ; # Bottom Switch
+NET "sw2"        LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP                  ; # Top Switch
 
 # I/O's for test connector
-#NET tvs1                      LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-#NET tvs0                      LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-NET tmosi                     LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-NET tdin                      LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-NET tcclk                     LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-#NET tm1                       LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-#NET thsw                      LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
+#NET tvs1        LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2
+#NET tvs0        LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3
+NET tmosi        LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4
+NET tdin         LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5
+NET tcclk        LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6
+#NET tm1         LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7
+#NET thsw        LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8
 
-NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
-NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
+NET "avr_TxD"    LOC="P26" | IOSTANDARD = LVCMOS33                           ;
+NET "avr_RxD"    LOC="P15" | IOSTANDARD = LVCMOS33                           ;
 
-NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
-NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
+NET "trig<0>"    LOC="P62" | IOSTANDARD = LVCMOS33                           ;
+NET "trig<1>"    LOC="P63" | IOSTANDARD = LVCMOS33                           ;
 
-NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ;
-
-# NET ""  LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 
-# NET ""  LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
-# NET ""  LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
-# NET ""  LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
-# NET ""  LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
-# NET ""  LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
-# NET ""  LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
-
-
- 
+NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33                           ;

target/godil_250/ice6502/ice6502.xise

@@ -18,10 +18,6 @@
     <file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../../src/AtomCpuMon.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
-    </file>
     <file xil_pn:name="../../../src/T6502/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
@@ -257,6 +253,14 @@
     <file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="../../../src/MOS6502CpuMon.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
+    </file>
+    <file xil_pn:name="../../../src/MOS6502CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
+    </file>
     <file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
@@ -366,9 +370,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomCpuMon|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/AtomCpuMon.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomCpuMon" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MOS6502CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MOS6502CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MOS6502CpuMonGODIL" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -426,7 +430,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -438,10 +442,10 @@
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@@ -461,7 +465,7 @@
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>

target/godil_250/ice6502/memory.bmm

@@ -2,35 +2,35 @@ ADDRESS_MAP avrmap PPC405 0
 
     ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
+	    wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
+	    wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
+	    wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
+	    wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
+	    wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
+	    wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
+	    wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
         END_BUS_BLOCK;
 
         BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
+	    wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
         END_BUS_BLOCK;
 
     END_ADDRESS_SPACE;

target/godil_250/ice6502fast/board.ucf

@@ -1,83 +0,0 @@
-
-NET "clock49"  LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator
-
-NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
-PIN "inst_dcm0/DCM_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
-NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
-PIN "inst_dcm2/DCM_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
-   
-#NET "VSS"    LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
-#NET "Rdy"      LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
-NET "Phi1"     LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
-NET "IRQ_n"    LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 4
-#NET "NC"      LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
-NET "NMI_n"    LOC="P22" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 6
-NET "Sync"     LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
-#NET "VCC"     LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
-NET "Addr<0>"  LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
-NET "Addr<1>"  LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
-NET "Addr<2>"  LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
-NET "Addr<3>"  LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
-NET "Addr<4>"  LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
-NET "Addr<5>"  LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
-NET "Addr<6>"  LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
-NET "Addr<7>"  LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
-NET "Addr<8>"  LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
-NET "Addr<9>"  LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
-NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
-NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
-
-#NET "VSS"     LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
-NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
-NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
-NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
-NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
-NET "Data<7>"  LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
-NET "Data<6>"  LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
-NET "Data<5>"  LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
-NET "Data<4>"  LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
-NET "Data<3>"  LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
-NET "Data<2>"  LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
-NET "Data<1>"  LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
-NET "Data<0>"  LOC="P3"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
-NET "R_W_n"    LOC="P2"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
-#NET "NC"      LOC="P4"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
-#NET "NC"      LOC="P5"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
-NET "Phi0"     LOC="P90" | IOSTANDARD = LVCMOS33 | PERIOD = 500.0 ; # 6502 pin 37
-NET "SO_n"     LOC="P9"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
-NET "Phi2"     LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
-NET "Res_n"    LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
-
-NET "led3"       LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
-NET "led6"       LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
-NET "led8"       LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
-NET "sw1"        LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
-NET "sw2"       LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
-
-# I/O's for test connector
-#NET tvs1                      LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-#NET tvs0                      LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-NET tmosi                     LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-NET tdin                      LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-NET tcclk                     LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-#NET tm1                       LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-#NET thsw                      LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-
-NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
-NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
-
-NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
-NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
-
-#NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ;
-
-# NET ""  LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 
-# NET ""  LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
-# NET ""  LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
-# NET ""  LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
-# NET ""  LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
-# NET ""  LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
-# NET ""  LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
-
-
- 

target/godil_250/ice6502fast/memory.bmm

@@ -1,38 +0,0 @@
-ADDRESS_MAP avrmap PPC405 0
-
-    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
-        BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
-        END_BUS_BLOCK;
-
-    END_ADDRESS_SPACE;
-
-END_ADDRESS_MAP;

target/godil_250/ice6502mon/board.ucf

@@ -1,76 +0,0 @@
-
-NET "clock49"  LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator
-
-#NET "VSS"    LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
-NET "Rdy"      LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
-#NET "Phi1"     LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
-#NET "IRQ_n"    LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 4
-#NET "NC"      LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
-#NET "NMI_n"    LOC="P22" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 6
-NET "Sync"     LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
-#NET "VCC"     LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
-NET "Addr<0>"  LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
-NET "Addr<1>"  LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
-NET "Addr<2>"  LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
-NET "Addr<3>"  LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
-NET "Addr<4>"  LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
-NET "Addr<5>"  LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
-NET "Addr<6>"  LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
-NET "Addr<7>"  LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
-NET "Addr<8>"  LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
-NET "Addr<9>"  LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
-NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
-NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
-
-#NET "VSS"     LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
-NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
-NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
-NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
-NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
-#NET "Data<7>"  LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
-#NET "Data<6>"  LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
-#NET "Data<5>"  LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
-#NET "Data<4>"  LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
-#NET "Data<3>"  LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
-#NET "Data<2>"  LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
-#NET "Data<1>"  LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
-#NET "Data<0>"  LOC="P3"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
-NET "RNW"    LOC="P2"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
-#NET "NC"      LOC="P4"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
-#NET "NC"      LOC="P5"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
-#NET "Phi0"     LOC="P90" | IOSTANDARD = LVCMOS33 | PERIOD = 500.0 ; # 6502 pin 37
-#NET "SO_n"     LOC="P9"  | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
-NET "Phi2"     LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
-NET "nRST"    LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
-
-NET "led3"       LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
-NET "led6"       LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
-NET "led8"       LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
-NET "sw1"        LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
-NET "sw2"        LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
-
-# I/O's for test connector
-#NET tvs1                      LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-#NET tvs0                      LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-NET tmosi                     LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-NET tdin                      LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-NET tcclk                     LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-#NET tm1                       LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-#NET thsw                      LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
-
-NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
-NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
-
-NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
-NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
-
-# NET ""  LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2 
-# NET ""  LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
-# NET ""  LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
-# NET ""  LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
-# NET ""  LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
-# NET ""  LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
-# NET ""  LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
-
-
- 

target/godil_250/ice6502mon/ice6502mon.xise

@@ -1,549 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="../../../src/AtomBusMon.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
-    </file>
-    <file xil_pn:name="../../../src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Core/avr_core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Core/alu_avr.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Core/bit_processor.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Core/io_adr_dec.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Core/io_reg_file.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Core/pm_fetch_dec.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Core/reg_file.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/ArbiterAndMux.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemAccessCompPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/MemRdMux.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Peripheral/SynchronizerCompPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Peripheral/SynchronizerDFF.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Peripheral/SynchronizerLatch.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/resync/rsnc_comp_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/spi_mod/spi_mod_comp_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/spi_mod/spi_mod.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/uC/RAMDataReg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/CommonPacks/avr_adr_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/CommonPacks/AVRuCPackage.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/CommonPacks/std_library.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/CommonPacks/SynthCtrlPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Core/AVR_Core_CompPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
-    </file>
-    <file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="../../../src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
-    </file>
-    <file xil_pn:name="../../../src/oho_dy1/OhoPack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
-    </file>
-    <file xil_pn:name="../../../src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
-    </file>
-    <file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="../ipcore/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
-    </file>
-    <file xil_pn:name="../../../src/AVR8/Memory/XPM_Xilinx.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
-    </file>
-    <file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc3s250e" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomBusMon|behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/AtomBusMon.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomBusMon" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="AtomBusMon" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomBusMon_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomBusMon_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomBusMon_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomBusMon_translate.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomBusMon" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="AtomBusMon" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-05-24T15:45:55" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6944A56AEEC704FF66BE3C0F54DA91A8" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>

target/godil_250/ice6502mon/memory.bmm

@@ -1,38 +0,0 @@
-ADDRESS_MAP avrmap PPC405 0
-
-    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
-        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
-        END_BUS_BLOCK;
-
-        BUS_BLOCK
-	    mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
-        END_BUS_BLOCK;
-
-    END_ADDRESS_SPACE;
-
-END_ADDRESS_MAP;

target/godil_250/ice65c02/Makefile

@@ -5,10 +5,10 @@ ROOT       = ../../..
 COMMON     = ../../common
 
 # The project .bit file produced by the Xilinx .xise project
-PROJECT    = AtomFast6502
+PROJECT    = MOS6502CpuMonGODIL
 
 # The target .bit file to be generated including the monitor program
-TARGET     = ice6502fast
+TARGET     = ice65c02
 
 # Common include files
 include $(COMMON)/Makefile_$(TARGET).inc

target/godil_250/ice65c02/board.ucf

@@ -0,0 +1,73 @@
+NET "clock49" TNM_NET = clk_period_grp_49;
+TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
+
+NET "Phi0" TNM_NET = clk_period_grp_phi0;
+TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
+
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33                           ; # 49.152 MHz Oscillator
+#NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 1
+NET "Rdy"        LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 2
+NET "Phi1"       LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 3
+NET "IRQ_n"      LOC="P17" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 4
+#NET "NC"        LOC="P94" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 5
+NET "NMI_n"      LOC="P22" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 6
+NET "Sync"       LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 7
+#NET "VCC"       LOC="P33" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 8
+NET "Addr<0>"    LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 9
+NET "Addr<1>"    LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 10
+NET "Addr<2>"    LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 11
+NET "Addr<3>"    LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 12
+NET "Addr<4>"    LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 13
+NET "Addr<5>"    LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 14
+NET "Addr<6>"    LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 15
+NET "Addr<7>"    LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 16
+NET "Addr<8>"    LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 17
+NET "Addr<9>"    LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 18
+NET "Addr<10>"   LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 19
+NET "Addr<11>"   LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 20
+
+#NET "VSS"       LOC="P67" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 21
+NET "Addr<12>"   LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 22
+NET "Addr<13>"   LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 23
+NET "Addr<14>"   LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 24
+NET "Addr<15>"   LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 25
+NET "Data<7>"    LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 26
+NET "Data<6>"    LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 27
+NET "Data<5>"    LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 28
+NET "Data<4>"    LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 29
+NET "Data<3>"    LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 30
+NET "Data<2>"    LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 31
+NET "Data<1>"    LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 32
+NET "Data<0>"    LOC="P3"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 33
+NET "R_W_n"      LOC="P2"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 34
+#NET "NC"        LOC="P4"  | IOSTANDARD = LVCMOS33                           ; # 6502 pin 35
+#NET "NC"        LOC="P5"  | IOSTANDARD = LVCMOS33                           ; # 6502 pin 36
+NET "Phi0"       LOC="P90" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 37
+NET "SO_n"       LOC="P9"  | IOSTANDARD = LVCMOS33                           ; # 6502 pin 38
+NET "Phi2"       LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # 6502 pin 39
+NET "Res_n"      LOC="P11" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 40
+
+NET "led3"       LOC="P43" | IOSTANDARD = LVCMOS33                           ; # Red LED (near SW1)
+NET "led6"       LOC="P25" | IOSTANDARD = LVCMOS33                           ; # Red LED (just left of FPGA)
+NET "led8"       LOC="P47" | IOSTANDARD = LVCMOS33                           ; # Green LED (near SW1)
+NET "sw1"        LOC="P39" | IOSTANDARD = LVCMOS33                           ; # Bottom Switch
+NET "sw2"        LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP                  ; # Top Switch
+
+# I/O's for test connector
+#NET tvs1        LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2
+#NET tvs0        LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3
+NET tmosi        LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4
+NET tdin         LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5
+NET tcclk        LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6
+#NET tm1         LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7
+#NET thsw        LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8
+
+NET "avr_TxD"    LOC="P26" | IOSTANDARD = LVCMOS33                           ;
+NET "avr_RxD"    LOC="P15" | IOSTANDARD = LVCMOS33                           ;
+
+NET "trig<0>"    LOC="P62" | IOSTANDARD = LVCMOS33                           ;
+NET "trig<1>"    LOC="P63" | IOSTANDARD = LVCMOS33                           ;
+
+NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33                           ;