Update firmware version to 0.984

Change-Id: I2793e20f7b949c3d3c2a73d2a2a8604cc5d51391

firmware/AtomBusMon.c

@@ -14,7 +14,7 @@
  * VERSION and NAME are used in the start-up message
  ********************************************************/
 
-#define VERSION "0.981 (custom for Bram)"
+#define VERSION "0.984"
 
 #if defined(CPU_Z80)
   #define NAME "ICE-Z80"
@@ -70,7 +70,6 @@ char *cmdStrings[] = {
   "load",
   "save",
   "srec",
-  "ihex",
   "special",
   "reset",
   "trace",
@@ -124,7 +123,6 @@ void (*cmdFuncs[])(char *params) = {
   doCmdLoad,
   doCmdSave,
   doCmdSRec,
-  doCmdIHex,
   doCmdSpecial,
   doCmdReset,
   doCmdTrace,
@@ -192,51 +190,50 @@ static const uint8_t helpMeta[] PROGMEM = {
 #endif
   17, 15, // help
    9,  8, // continue
-  25,  7, // next
-  33,  6, // step
-  28,  7, // regs
+  24,  7, // next
+  32,  6, // step
+  27,  7, // regs
   12, 10, // dis
   16,  7, // flush
   13, 11, // fill
   11,  9, // crc
   10, 13, // copy
    8, 13, // compare
-  23,  1, // mem
-  27,  2, // rd
-  42,  3, // wr
+  22,  1, // mem
+  26,  2, // rd
+  41,  3, // wr
 #if defined(CPU_Z80)
-  21,  1, // io
-  20,  2, // in
-  26,  3, // out
+  20,  1, // io
+  19,  2, // in
+  25,  3, // out
 #endif
 #if defined(CPU_6502) || defined(CPU_65C02)
   14,  0, // go
   15, 16, // exec
-  24, 14, // mode
+  23, 14, // mode
 #endif
-  34, 12, // test
-  22,  0, // load
-  30,  9, // save
-  32,  7, // srec
-  19,  7, // ihex
-  31, 14, // special
-  29,  7, // reset
-  35,  6, // trace
+  33, 12, // test
+  21,  0, // load
+  29,  9, // save
+  31,  7, // srec
+  30, 14, // special
+  28,  7, // reset
+  34,  6, // trace
    1,  7, // blist
    6,  4, // breakx
-  41,  4, // watchx
+  40,  4, // watchx
    4,  4, // breakr
-  39,  4, // watchr
+  38,  4, // watchr
    5,  4, // breakw
-  40,  4, // watchw
+  39,  4, // watchw
 #if defined(CPU_Z80)
    2,  4, // breaki
-  37,  4, // watchi
+  36,  4, // watchi
    3,  4, // breako
-  38,  4, // watcho
+  37,  4, // watcho
 #endif
    7,  0, // clear
-  36,  5, // trigger
+  35,  5, // trigger
    0,  0
 };
 
@@ -1056,6 +1053,9 @@ uint8_t logDetails() {
 }
 
 void logAddr() {
+  // Delay works around a race condition with slow CPUs
+  // (really the STEP and RESET commands should be synchronous)
+  Delay_us(100);
   memAddr = hwRead16(OFFSET_IAL);
   // Update the serial console
   logCycleCount(OFFSET_CNTL, OFFSET_CNTH);
@@ -1975,10 +1975,6 @@ void doCmdSRec(char *params) {
   }
 }
 
-void doCmdIHex(char *params) {
-   logstr("TODO: implement intel hex command\n");
-}
-
 void logSpecial(char *function, uint8_t value) {
   logs(function);
   if (value) {

firmware/AtomBusMon.h

@@ -62,7 +62,6 @@ void doCmdHelp(char *params);
 void doCmdHistory(char *params);
 void helpForCommand(uint8_t i);
 #endif
-void doCmdIHex(char *params);
 void doCmdIO(char *params);
 void doCmdList(char *params);
 void doCmdLoad(char *params);

src/MOS6502CpuMonALS.vhd

@@ -104,26 +104,13 @@ architecture behavioral of MOS6502CpuMonALS is
     signal led_trig0    : std_logic;
     signal led_trig1    : std_logic;
 
-
-    signal int_Phi0_div : unsigned(4 downto 0); -- internal Phi0 clock divider
-    signal int_Phi0     : std_logic;            -- internal Phi0 clock
+    signal PhiIn1       : std_logic;
+    signal PhiIn2       : std_logic;
+    signal PhiIn3       : std_logic;
+    signal PhiIn4       : std_logic;
 
 begin
 
-    -- Hack to use an internal 1MHz clock instead of Phi0
-    -- from the 50MHz clock on the EEPIZZA board
-    process(clock)
-    begin
-        if rising_edge(clock) then
-            if int_Phi0_div = 24 then
-                int_Phi0 <= not int_Phi0; -- toggle int_Phi2 every 25 cycles
-                int_Phi0_div <= (others => '0');
-            else
-                int_Phi0_div <= int_Phi0_div + 1;
-            end if;
-        end if;
-    end process;
-
     sw_reset_cpu <= not sw1;
     sw_reset_avr <= not sw2;
     led1         <= led_bkpt;
@@ -144,7 +131,7 @@ begin
             clock             => clock,
 
             -- 6502 Signals
-            Phi0              => int_Phi0, -- hack to use internal Phi0
+            Phi0              => PhiIn,
             Phi1              => Phi1Out,
             Phi2              => Phi2Out,
             IRQ_n             => IRQ_n,
@@ -189,11 +176,22 @@ begin
     ML_n   <= '1';
     VP_n   <= '1';
 
+    process(clock)
+    begin
+        if rising_edge(clock) then
+            PhiIn1 <= PhiIn;
+            PhiIn2 <= PhiIn1;
+            PhiIn3 <= PhiIn2;
+            PhiIn4 <= PhiIn3;
+        end if;
+
+    end process;
+
     -- Level Shifter Controls
-    OERW_n <= not (BE);
-    OEAH_n <= not (BE);
-    OEAL_n <= not (BE);
-    OED_n  <= not (BE and int_Phi0); -- hack to use interal Phi0
+    OERW_n <= '0'; -- not (BE);
+    OEAH_n <= '0'; -- not (BE);
+    OEAL_n <= '0'; -- not (BE);
+    OED_n  <= not (BE and PhiIn and PhiIn4); -- TODO: might need to use a slightly delayed version of Phi2 here
     DIRD   <= R_W_n_int;
 
 end behavioral;

src/Z80CpuMon.vhd

@@ -52,6 +52,7 @@ entity Z80CpuMon is
         -- Buffer Control Signals
         DIRD            : out   std_logic;
         tristate_n      : out   std_logic;
+        tristate_ad_n   : out   std_logic;
 
         -- Mode jumper, tie low to generate NOPs when paused
         mode            : in    std_logic;
@@ -415,6 +416,11 @@ begin
 
     BUSAK_n    <= BUSAK_n_int when state = idle else mon_busak_n;
 
+    -- Force the address and databus to tristate when reset is asserted
+    tristate_ad_n <= '0'         when RESET_n = '0' else
+                     BUSAK_n_int when state = idle  else
+                     mon_busak_n1;
+
 -- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1
 -- and MREQ being released at the start of T3. Otherwise, the ROM switching
 -- during NMI doesn't work reliably due to glitches. See:

src/Z80CpuMonALS.vhd

@@ -95,6 +95,7 @@ architecture behavioral of Z80CpuMonALS is
     signal HALT_n_int   : std_logic;
     signal BUSAK_n_int  : std_logic;
     signal tristate_n   : std_logic;
+    signal tristate_ad_n: std_logic;
 
     signal sw_reset_cpu : std_logic;
     signal sw_reset_avr : std_logic;
@@ -121,9 +122,9 @@ begin
     BUSAK_n <= BUSAK_n_int;
 
     OEC_n   <= not tristate_n;
-    OEA1_n  <= not tristate_n;
-    OEA2_n  <= not tristate_n;
-    OED_n   <= not tristate_n;
+    OEA1_n  <= not tristate_ad_n;
+    OEA2_n  <= not tristate_ad_n;
+    OED_n   <= not tristate_ad_n;
 
     wrapper : entity work.Z80CpuMon
         generic map (
@@ -157,6 +158,7 @@ begin
             -- Buffer Control Signals
             DIRD              => DIRD,
             tristate_n        => tristate_n,
+            tristate_ad_n     => tristate_ad_n,
 
             -- Mode jumper, tie low to generate NOPs when paused
             mode              => mode,

src/Z80CpuMonGODIL.vhd

@@ -94,6 +94,7 @@ architecture behavioral of Z80CpuMonGODIL is
     signal Addr_int     : std_logic_vector(15 downto 0);
 
     signal tristate_n   : std_logic;
+    signal tristate_ad_n: std_logic;
 
 begin
     sw_reset_cpu <= sw1;
@@ -107,7 +108,7 @@ begin
     IORQ_n <= 'Z'             when tristate_n = '0' else IORQ_n_int;
     RD_n   <= 'Z'             when tristate_n = '0' else RD_n_int;
     WR_n   <= 'Z'             when tristate_n = '0' else WR_n_int;
-    Addr   <= (others => 'Z') when tristate_n = '0' else Addr_int;
+    Addr   <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
 
     wrapper : entity work.Z80CpuMon
         generic map (
@@ -140,6 +141,7 @@ begin
 
             -- Buffer Control Signals
             tristate_n      =>  tristate_n,
+            tristate_ad_n   =>  tristate_ad_n,
             DIRD            =>  open,
 
             -- Mode jumper, tie low to generate NOPs when paused

src/Z80CpuMonLX9.vhd

@@ -94,6 +94,7 @@ architecture behavioral of Z80CpuMonLX9 is
     signal Addr_int     : std_logic_vector(15 downto 0);
 
     signal tristate_n   : std_logic;
+    signal tristate_ad_n: std_logic;
 
 begin
 
@@ -108,7 +109,7 @@ begin
     IORQ_n <= 'Z'             when tristate_n = '0' else IORQ_n_int;
     RD_n   <= 'Z'             when tristate_n = '0' else RD_n_int;
     WR_n   <= 'Z'             when tristate_n = '0' else WR_n_int;
-    Addr   <= (others => 'Z') when tristate_n = '0' else Addr_int;
+    Addr   <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
 
     wrapper : entity work.Z80CpuMon
         generic map (
@@ -141,6 +142,7 @@ begin
 
             -- Buffer Control Signals
             tristate_n      =>  tristate_n,
+            tristate_ad_n   =>  tristate_ad_n,
             DIRD            =>  open,
 
             -- Mode jumper, tie low to generate NOPs when paused