Update firmware version to 0.984

Change-Id: I2793e20f7b949c3d3c2a73d2a2a8604cc5d51391

firmware/AtomBusMon.c

@@ -14,7 +14,7 @@
  * VERSION and NAME are used in the start-up message
  ********************************************************/
 
-#define VERSION "0.981"
+#define VERSION "0.984"
 
 #if defined(CPU_Z80)
   #define NAME "ICE-Z80"
@@ -1053,6 +1053,9 @@ uint8_t logDetails() {
 }
 
 void logAddr() {
+  // Delay works around a race condition with slow CPUs
+  // (really the STEP and RESET commands should be synchronous)
+  Delay_us(100);
   memAddr = hwRead16(OFFSET_IAL);
   // Update the serial console
   logCycleCount(OFFSET_CNTL, OFFSET_CNTH);

src/MOS6502CpuMonALS.vhd

@@ -104,6 +104,11 @@ architecture behavioral of MOS6502CpuMonALS is
     signal led_trig0    : std_logic;
     signal led_trig1    : std_logic;
 
+    signal PhiIn1       : std_logic;
+    signal PhiIn2       : std_logic;
+    signal PhiIn3       : std_logic;
+    signal PhiIn4       : std_logic;
+
 begin
 
     sw_reset_cpu <= not sw1;
@@ -171,11 +176,22 @@ begin
     ML_n   <= '1';
     VP_n   <= '1';
 
+    process(clock)
+    begin
+        if rising_edge(clock) then
+            PhiIn1 <= PhiIn;
+            PhiIn2 <= PhiIn1;
+            PhiIn3 <= PhiIn2;
+            PhiIn4 <= PhiIn3;
+        end if;
+
+    end process;
+
     -- Level Shifter Controls
-    OERW_n <= not (BE);
-    OEAH_n <= not (BE);
-    OEAL_n <= not (BE);
-    OED_n  <= not (BE and PhiIn); -- TODO: might need to use a slightly delayed version of Phi2 here
+    OERW_n <= '0'; -- not (BE);
+    OEAH_n <= '0'; -- not (BE);
+    OEAL_n <= '0'; -- not (BE);
+    OED_n  <= not (BE and PhiIn and PhiIn4); -- TODO: might need to use a slightly delayed version of Phi2 here
     DIRD   <= R_W_n_int;
 
 end behavioral;

src/Z80CpuMon.vhd

@@ -52,6 +52,7 @@ entity Z80CpuMon is
         -- Buffer Control Signals
         DIRD            : out   std_logic;
         tristate_n      : out   std_logic;
+        tristate_ad_n   : out   std_logic;
 
         -- Mode jumper, tie low to generate NOPs when paused
         mode            : in    std_logic;
@@ -415,6 +416,11 @@ begin
 
     BUSAK_n    <= BUSAK_n_int when state = idle else mon_busak_n;
 
+    -- Force the address and databus to tristate when reset is asserted
+    tristate_ad_n <= '0'         when RESET_n = '0' else
+                     BUSAK_n_int when state = idle  else
+                     mon_busak_n1;
+
 -- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1
 -- and MREQ being released at the start of T3. Otherwise, the ROM switching
 -- during NMI doesn't work reliably due to glitches. See:

src/Z80CpuMonALS.vhd

@@ -95,6 +95,7 @@ architecture behavioral of Z80CpuMonALS is
     signal HALT_n_int   : std_logic;
     signal BUSAK_n_int  : std_logic;
     signal tristate_n   : std_logic;
+    signal tristate_ad_n: std_logic;
 
     signal sw_reset_cpu : std_logic;
     signal sw_reset_avr : std_logic;
@@ -121,9 +122,9 @@ begin
     BUSAK_n <= BUSAK_n_int;
 
     OEC_n   <= not tristate_n;
-    OEA1_n  <= not tristate_n;
-    OEA2_n  <= not tristate_n;
-    OED_n   <= not tristate_n;
+    OEA1_n  <= not tristate_ad_n;
+    OEA2_n  <= not tristate_ad_n;
+    OED_n   <= not tristate_ad_n;
 
     wrapper : entity work.Z80CpuMon
         generic map (
@@ -157,6 +158,7 @@ begin
             -- Buffer Control Signals
             DIRD              => DIRD,
             tristate_n        => tristate_n,
+            tristate_ad_n     => tristate_ad_n,
 
             -- Mode jumper, tie low to generate NOPs when paused
             mode              => mode,

src/Z80CpuMonGODIL.vhd

@@ -94,6 +94,7 @@ architecture behavioral of Z80CpuMonGODIL is
     signal Addr_int     : std_logic_vector(15 downto 0);
 
     signal tristate_n   : std_logic;
+    signal tristate_ad_n: std_logic;
 
 begin
     sw_reset_cpu <= sw1;
@@ -107,7 +108,7 @@ begin
     IORQ_n <= 'Z'             when tristate_n = '0' else IORQ_n_int;
     RD_n   <= 'Z'             when tristate_n = '0' else RD_n_int;
     WR_n   <= 'Z'             when tristate_n = '0' else WR_n_int;
-    Addr   <= (others => 'Z') when tristate_n = '0' else Addr_int;
+    Addr   <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
 
     wrapper : entity work.Z80CpuMon
         generic map (
@@ -140,6 +141,7 @@ begin
 
             -- Buffer Control Signals
             tristate_n      =>  tristate_n,
+            tristate_ad_n   =>  tristate_ad_n,
             DIRD            =>  open,
 
             -- Mode jumper, tie low to generate NOPs when paused

src/Z80CpuMonLX9.vhd

@@ -94,6 +94,7 @@ architecture behavioral of Z80CpuMonLX9 is
     signal Addr_int     : std_logic_vector(15 downto 0);
 
     signal tristate_n   : std_logic;
+    signal tristate_ad_n: std_logic;
 
 begin
 
@@ -108,7 +109,7 @@ begin
     IORQ_n <= 'Z'             when tristate_n = '0' else IORQ_n_int;
     RD_n   <= 'Z'             when tristate_n = '0' else RD_n_int;
     WR_n   <= 'Z'             when tristate_n = '0' else WR_n_int;
-    Addr   <= (others => 'Z') when tristate_n = '0' else Addr_int;
+    Addr   <= (others => 'Z') when tristate_ad_n = '0' else Addr_int;
 
     wrapper : entity work.Z80CpuMon
         generic map (
@@ -141,6 +142,7 @@ begin
 
             -- Buffer Control Signals
             tristate_n      =>  tristate_n,
+            tristate_ad_n   =>  tristate_ad_n,
             DIRD            =>  open,
 
             -- Mode jumper, tie low to generate NOPs when paused