Updated XPM_T65 to 0.998

Change-Id: I3152215ec4d3d2148c23a4ecb1a6eefcd79329af

.gitignore

@@ -8,6 +8,7 @@ nohup.out
 target/**/*.o
 target/**/*.bit
 target/**/*.mcs
+target/**/*.bin
 target/**/avr_progmem.*
 target/*/ipcore/WatchEvents.asy
 target/*/ipcore/WatchEvents.gise

firmware/AtomBusMon.c

@@ -14,16 +14,35 @@
  * VERSION and NAME are used in the start-up message
  ********************************************************/
 
-#define VERSION "0.984"
+#define VERSION "0.998"
+
+// The X commands allows the various interrupt inputs to be overridded
+// They are named after the data sheet pin name
 
 #if defined(CPU_Z80)
   #define NAME "ICE-Z80"
+  #define XCMD0 "xbusrq"
+  #define XCMD1 "xint"
+  #define XCMD2 "xnmi"
+  #define XCMD3 "xres"
 #elif defined(CPU_6502)
   #define NAME "ICE-6502"
+  #define XCMD0 "xirq"
+  #define XCMD1 "xnmi"
+  #define XCMD2 "xres"
+  #define XCMD3 "xso "
 #elif defined(CPU_65C02)
   #define NAME "ICE-65C02"
+  #define XCMD0 "xirq"
+  #define XCMD1 "xnmi"
+  #define XCMD2 "xres"
+  #define XCMD3 "xso "
 #elif defined(CPU_6809)
   #define NAME "ICE-6809"
+  #define XCMD0 "xfiq"
+  #define XCMD1 "xirq"
+  #define XCMD2 "xnmi"
+  #define XCMD3 "xres"
 #else
   #error "Unsupported CPU type"
 #endif
@@ -70,7 +89,6 @@ char *cmdStrings[] = {
   "load",
   "save",
   "srec",
-  "special",
   "reset",
   "trace",
   "blist",
@@ -87,7 +105,13 @@ char *cmdStrings[] = {
   "watcho",
 #endif
   "clear",
-  "trigger"
+  "trigger",
+  "timermode",
+  "timeout",
+  XCMD0,
+  XCMD1,
+  XCMD2,
+  XCMD3
 };
 
 // Must be kept in step with cmdStrings (just above)
@@ -123,7 +147,6 @@ void (*cmdFuncs[])(char *params) = {
   doCmdLoad,
   doCmdSave,
   doCmdSRec,
-  doCmdSpecial,
   doCmdReset,
   doCmdTrace,
   doCmdList,
@@ -140,7 +163,13 @@ void (*cmdFuncs[])(char *params) = {
   doCmdWatchWrIO,
 #endif
   doCmdClear,
-  doCmdTrigger
+  doCmdTrigger,
+  doCmdTimerMode,
+  doCmdTimeout,
+  doCmdXCmd0,
+  doCmdXCmd1,
+  doCmdXCmd2,
+  doCmdXCmd3
 };
 
 #if defined(EXTENDED_HELP)
@@ -162,6 +191,8 @@ static const char ARGS13[] PROGMEM = "<start> <end> <to>";
 static const char ARGS14[] PROGMEM = "[ <value> ]";
 static const char ARGS15[] PROGMEM = "[ <command> ]";
 static const char ARGS16[] PROGMEM = "<op1> [ <op2> [ <op3> ] ]";
+static const char ARGS17[] PROGMEM = "[ <source> [ <prescale> [ <reset address> ] ] ]";
+static const char ARGS18[] PROGMEM = "e|c|d|f";
 
 static const char * const argsStrings[] PROGMEM = {
   ARGS00,
@@ -180,7 +211,9 @@ static const char * const argsStrings[] PROGMEM = {
   ARGS13,
   ARGS14,
   ARGS15,
-  ARGS16
+  ARGS16,
+  ARGS17,
+  ARGS18
 };
 
 // Must be kept in step with cmdStrings (just above)
@@ -190,8 +223,8 @@ static const uint8_t helpMeta[] PROGMEM = {
 #endif
   17, 15, // help
    9,  8, // continue
-  24,  7, // next
-  32,  6, // step
+  24,  1, // next
+  31,  6, // step
   27,  7, // regs
   12, 10, // dis
   16,  7, // flush
@@ -201,7 +234,7 @@ static const uint8_t helpMeta[] PROGMEM = {
    8, 13, // compare
   22,  1, // mem
   26,  2, // rd
-  41,  3, // wr
+  42,  3, // wr
 #if defined(CPU_Z80)
   20,  1, // io
   19,  2, // in
@@ -212,28 +245,33 @@ static const uint8_t helpMeta[] PROGMEM = {
   15, 16, // exec
   23, 14, // mode
 #endif
-  33, 12, // test
+  32, 12, // test
   21,  0, // load
   29,  9, // save
-  31,  7, // srec
-  30, 14, // special
+  30,  7, // srec
   28,  7, // reset
-  34,  6, // trace
+  35,  6, // trace
    1,  7, // blist
    6,  4, // breakx
-  40,  4, // watchx
+  41,  4, // watchx
    4,  4, // breakr
-  38,  4, // watchr
+  39,  4, // watchr
    5,  4, // breakw
-  39,  4, // watchw
+  40,  4, // watchw
 #if defined(CPU_Z80)
    2,  4, // breaki
-  36,  4, // watchi
+  37,  4, // watchi
    3,  4, // breako
-  37,  4, // watcho
+  38,  4, // watcho
 #endif
    7,  0, // clear
-  35,  5, // trigger
+  36,  5, // trigger
+  34, 17, // timermode
+  33, 14, // timeout
+  43, 18, // xcmd0
+  44, 18, // xcmd1
+  45, 18, // xcmd2
+  46, 18, // xcmd3
    0,  0
 };
 
@@ -248,42 +286,42 @@ static const uint8_t helpMeta[] PROGMEM = {
 #define CTRL_DDR          DDRB
 #define CTRL_DIN          PINB
 
-// A 0->1 transition on bit 5 actually sends a command
-#define CMD_EDGE          0x20
+// A 0->1 transition on bit 6 actually sends a command
+#define CMD_EDGE          0x40
 
-// Commands are placed on bits 4..0
-#define CMD_MASK          0x1F
-
-// Bits 7..6 are the special function output bits
-// On the 6502, these are used to mask IRQ and NMI
-#define SPECIAL_0            6
-#define SPECIAL_1            7
-#define SPECIAL_MASK      ((1<<SPECIAL_0) | (1<<SPECIAL_1))
+// Commands are placed on bits 5..0
+#define CMD_MASK          0x3F
 
 // Hardware Commands:
 //
-// 0000x Enable/Disable single strpping
-// 0001x Enable/Disable breakpoints / watches
-// 0010x Load breakpoint / watch register
-// 0011x Reset CPU
-// 01000 Singe Step CPU
-// 01001 Read FIFO
-// 01010 Reset FIFO
-// 01011 Unused
-// 0110x Load address/data register
-// 0111x Unused
-// 10000 Read Memory
-// 10001 Read Memory and Auto Inc Address
-// 10010 Write Memory
-// 10011 Write Memory and Auto Inc Address
-// 10100 Read IO
-// 10101 Read IO and Auto Inc Address
-// 10110 Write IO
-// 10111 Write IO and Auto Inc Address
-// 11000 Exec Go
-// 11xx1 Unused
-// 11x1x Unused
-// 111xx Unused
+// 00000x Enable/Disable single strpping
+// 00001x Enable/Disable breakpoints / watches
+// 00010x Load breakpoint / watch register
+// 00011x Reset CPU
+// 001000 Singe Step CPU
+// 001001 Read FIFO
+// 001010 Reset FIFO
+// 001011 Unused
+// 00110x Load address/data register
+// 00111x Unused
+// 010000 Read Memory
+// 010001 Read Memory and Auto Inc Address
+// 010010 Write Memory
+// 010011 Write Memory and Auto Inc Address
+// 010100 Read IO
+// 010101 Read IO and Auto Inc Address
+// 010110 Write IO
+// 010111 Write IO and Auto Inc Address
+// 011000 Exec Go
+// 011xx1 Unused
+// 011x1x Unused
+// 0111xx Unused
+// 10xxxx Int Ctrl
+// 1100xx Timer Mode
+//     00 - count cpu cycles where clken = 1 and CountCycle = 1
+//     01 - count cpu cycles where clken = 1 (ignoring CountCycle)
+//     10 - free running timer, using busmon_clk as the source
+//     11 - free running timer, using trig0 as the source
 
 #define CMD_SINGLE_ENABLE 0x00
 #define CMD_BRKPT_ENABLE  0x02
@@ -302,6 +340,8 @@ static const uint8_t helpMeta[] PROGMEM = {
 #define CMD_WR_IO         0x16
 #define CMD_WR_IO_INC     0x17
 #define CMD_EXEC_GO       0x18
+#define CMD_INT_CTRL      0x20
+#define CMD_TIMER_MODE    0x30
 
 /********************************************************
  * AVR Status Register Definitions
@@ -446,6 +486,10 @@ modes_t modes[MAXBKPTS];
 #define WATCH_EXEC      9
 #define TRANSIENT      10
 
+// Mask to test if the breakpoint/watchpoint is a Z80 IO
+#if defined(CPU_Z80)
+#define MASK_IO ((1 << BRKPT_IO_READ) |  (1 << WATCH_IO_READ) |  (1 << BRKPT_IO_WRITE) |  (1 << WATCH_IO_WRITE))
+#endif
 
 static const char MODE0[] PROGMEM = "Mem Rd Brkpt";
 static const char MODE1[] PROGMEM = "Mem Rd Watch";
@@ -474,6 +518,21 @@ static const char *modeStrings[NUM_MODES] = {
   MODE10
 };
 
+// The number of different timer sources
+#define NUM_TIMERS   4
+
+static const char TIMER0[] PROGMEM = "Normal Cycles";
+static const char TIMER1[] PROGMEM = "All Cycles";
+static const char TIMER2[] PROGMEM = "Internal Timer";
+static const char TIMER3[] PROGMEM = "External Timer";
+
+static const char *timerStrings[NUM_TIMERS] = {
+  TIMER0,
+  TIMER1,
+  TIMER2,
+  TIMER3
+};
+
 // For convenience, several masks are defined that group similar types of breakpoint/watch
 
 // Mask for all breakpoint types
@@ -580,6 +639,24 @@ static const char * triggerStrings[NUM_TRIGGERS] = {
 
 #define TRIGGER_UNDEFINED 31
 
+/********************************************************
+ * Interrupt controls
+ ********************************************************/
+
+static const uint8_t cmd_map[] = { 1, 3, 0, 2 };
+
+static const char INTCTRL0[] PROGMEM = "Enabled";
+static const char INTCTRL1[] PROGMEM = "Conditional";
+static const char INTCTRL2[] PROGMEM = "Forced";
+static const char INTCTRL3[] PROGMEM = "Disabled";
+
+static const char *int_ctrl_strings[] = {
+   INTCTRL0,
+   INTCTRL1,
+   INTCTRL2,
+   INTCTRL3
+};
+
 /********************************************************
  * Other global variables
  ********************************************************/
@@ -587,6 +664,9 @@ static const char * triggerStrings[NUM_TRIGGERS] = {
 // The current memory address (e.g. used when disassembling)
 addr_t memAddr = 0;
 
+// The current memory timeout value, in microseconds.
+uint16_t memTimeout = 0x1000;
+
 // The address of the next instruction
 addr_t nextAddr = 0;
 
@@ -605,6 +685,16 @@ uint8_t cmd_id = 0xff;
 #define MASK_CLOCK_ERROR   1
 #define MASK_TIMEOUT_ERROR 2
 
+// Current timer mode setting
+uint8_t timer_mode = 0x00;
+uint8_t timer_prescale = 0x01;
+addr_t  timer_resetaddr = 0xffff;
+unsigned long timer_offset = 0;
+
+// Current interrupts controls
+uint8_t int_ctrl = 0;
+
+
 /********************************************************
  * User Command Processor
  ********************************************************/
@@ -746,9 +836,13 @@ uint8_t checkargs(char *params) {
  ********************************************************/
 
 // Send a single hardware command
+//
 void hwCmd(cmd_t cmd, cmd_t param) {
   uint8_t status = STATUS_DIN;
-  uint16_t timeout = 10000;
+  // An interation of the inner loop with a 32-bit loop variable
+  // is 9 instructions. So use F_CPU to scale to the timeout
+  // value is approx microseconds.
+  uint32_t timeout =  ((uint32_t) memTimeout) * ((F_CPU / 1000000) / 9);
   cmd |= param;
   CTRL_PORT &= ~CMD_MASK;
   CTRL_PORT ^= cmd | CMD_EDGE;
@@ -877,7 +971,7 @@ void writeIOByteInc() {
 
 addr_t disMem(addr_t addr) {
   loadAddr(addr);
-  return disassemble(addr);
+  return disassemble(addr, MODE_NORMAL);
 }
 
 void genericDump(char *params, data_t (*readFunc)()) {
@@ -957,8 +1051,9 @@ void genericRead(char *params, data_t (*readFunc)()) {
  * Logging Helpers
  ********************************************************/
 
-void logCycleCount(int offsetLow, int offsetHigh) {
-  unsigned long count = (((unsigned long) hwRead8(offsetHigh)) << 16) | hwRead16(offsetLow);
+void logCycleCount(int offsetLow, int offsetHigh, uint8_t clear) {
+  unsigned long original_count = (((unsigned long) hwRead8(offsetHigh)) << 16) | hwRead16(offsetLow);
+  unsigned long count = ((original_count - timer_offset) & 0xFFFFFF) / timer_prescale;
   char buffer[16];
   uint8_t i;
   // count is 24 bits so a maximum of 16777215
@@ -976,6 +1071,11 @@ void logCycleCount(int offsetLow, int offsetHigh) {
     }
   }
   logs(" : ");
+  // Deal with clearing the counter
+  if (clear) {
+    logs("\n00.000000 : ");
+    timer_offset = original_count;
+  }
 }
 
 void logMode(modes_t mode) {
@@ -1012,6 +1112,8 @@ uint8_t logDetails() {
 
   // Process the dropped counter
   uint8_t dropped = mode >> 4;
+  // Whether to clear timer
+  uint8_t clear = i_addr == timer_resetaddr;
   if (dropped) {
     logstr("          : ");
     if (dropped == 15) {
@@ -1030,7 +1132,7 @@ uint8_t logDetails() {
 
   // Update the serial console
   if (mode & W_MASK) {
-    logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
+    logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH, clear);
   }
   logMode(mode);
   logstr(" hit at ");
@@ -1046,7 +1148,7 @@ uint8_t logDetails() {
   logc('\n');
   if (mode & B_RDWR_MASK) {
     // It's only safe to do this for brkpts, as it makes memory accesses
-    logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
+    logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH, clear);
     disMem(i_addr);
   }
   return watch;
@@ -1058,7 +1160,7 @@ void logAddr() {
   Delay_us(100);
   memAddr = hwRead16(OFFSET_IAL);
   // Update the serial console
-  logCycleCount(OFFSET_CNTL, OFFSET_CNTH);
+  logCycleCount(OFFSET_CNTL, OFFSET_CNTH, memAddr == timer_resetaddr);
   nextAddr = disMem(memAddr);
   return;
 }
@@ -1189,7 +1291,11 @@ void clearBreakpoint(bknum_t n) {
 void genericBreakpoint(char *params, unsigned int mode) {
   bknum_t i;
   addr_t addr;
+#if defined(CPU_Z80)
+  addr_t mask = (mode & MASK_IO) ? 0xFF : 0xFFFF;
+#else
   addr_t mask = 0xFFFF;
+#endif
   trigger_t trigger = TRIGGER_UNDEFINED;
   params = parsehex4required(params, &addr);
   if (checkargs(params)) {
@@ -1366,7 +1472,7 @@ void helpForCommand(uint8_t i) {
   logstr("   ");
   logs(cmdStrings[i]);
   tmp = strlen(cmdStrings[i]);
-  while (tmp++ < 9) {
+  while (tmp++ < 10) {
     logc(' ');
   }
   while ((tmp = pgm_read_byte(ip++))) {
@@ -1469,7 +1575,7 @@ void doCmdDis(char *params) {
   memAddr = startAddr;
   loadAddr(memAddr);
   do {
-    memAddr = disassemble(memAddr);
+     memAddr = disassemble(memAddr, MODE_DIS_CMD);
     i++;
   } while ((!endAddr && i < 10) || (endAddr && memAddr > startAddr && memAddr <= endAddr));
 }
@@ -1975,23 +2081,89 @@ void doCmdSRec(char *params) {
   }
 }
 
-void logSpecial(char *function, uint8_t value) {
-  logs(function);
-  if (value) {
-    logstr(" inhibited\n");
-  } else {
-    logstr(" enabled\n");
-  }
+void set_int_ctrl(uint8_t offset, char *params) {
+   // (C) 01 Conditional
+   // (D) 11 Disabled
+   // (E) 00 Enabled
+   // (F) 10 Forced
+   while (*params == ' ') {
+      params++;
+   }
+   if (!*params) {
+      uint8_t tmp = int_ctrl;
+      for (int i = 0; i < 4; i++) {
+         logs(cmdStrings[NUM_CMDS - 4 + i]);
+         logstr(" = ");
+         logpgmstr(int_ctrl_strings[tmp & 3]);
+         logc('\n');
+         tmp >>= 2;
+      }
+   } else {
+      *params &= 0xdf;
+      if (*params >= 'C' && *params <= 'F') {
+         uint8_t val = cmd_map[*params - 'C'];
+         hwCmd(CMD_INT_CTRL, (offset << 1) | val);
+         int_ctrl &= (0x03 << offset) ^ 0xFF;
+         int_ctrl |= (val  << offset);
+      } else {
+         logstr("Illegal option\n");
+      }
+   }
 }
 
-void doCmdSpecial(char *params) {
-  uint8_t special = 0xff;
-  parsehex2(params, &special);
-  if (special <= 3) {
-    CTRL_PORT = (CTRL_PORT & ~SPECIAL_MASK) | (special << SPECIAL_0);
+void doCmdXCmd0(char *params) {
+   set_int_ctrl(0, params);
+}
+
+void doCmdXCmd1(char *params) {
+   set_int_ctrl(2, params);
+}
+
+void doCmdXCmd2(char *params) {
+   set_int_ctrl(4, params);
+}
+
+void doCmdXCmd3(char *params) {
+   set_int_ctrl(6, params);
+}
+
+void doCmdTimerMode(char *params) {
+  uint8_t      mode = 0xff;
+  uint8_t  prescale = 0xff;
+  addr_t       addr = 0xffff;
+
+  params = parsehex2(params, &mode);
+  params = parsehex2(params, &prescale);
+  params = parsehex4(params, &addr);
+  if (mode <= NUM_TIMERS) {
+    timer_mode = mode;
+    hwCmd(CMD_TIMER_MODE, timer_mode);
   }
-  logSpecial("NMI", CTRL_PORT & (1 << SPECIAL_1));
-  logSpecial("IRQ", CTRL_PORT & (1 << SPECIAL_0));
+  if (prescale < 0xff) {
+    timer_prescale = prescale;
+  }
+  if (addr < 0xffff) {
+    timer_resetaddr = addr;
+  }
+  logstr("mode: ");
+  logpgmstr(timerStrings[timer_mode]);
+  logstr("; prescale=");
+  loghex4(timer_prescale);
+  logstr("; reset address=");
+  loghex4(timer_resetaddr);
+  logstr("\n");
+}
+
+void doCmdTimeout(char *params) {
+  parsehex4(params, &memTimeout);
+  // Small timeouts values cause bogus timeout errors, so enforce a minimum
+  // of 16us, which is less much than one character time at 115,200 (86us)
+  if (memTimeout < 0x10) {
+     memTimeout = 0x10;
+  }
+  logstr("timeout=");
+  loghex4(memTimeout);
+  logstr(" microseconds (hex)\n");
 }
 
 void doCmdTrace(char *params) {
@@ -2113,8 +2285,13 @@ void doCmdNext(char *params) {
     logTooManyBreakpoints();
     return;
   }
+  addr_t addr = 0xFFFF;
+  params = parsehex4(params, &addr);
+  if (addr == 0xFFFF) {
+     addr = nextAddr;
+  }
   numbkpts++;
-  setBreakpoint(numbkpts - 1, nextAddr, 0xffff, (1 << BRKPT_EXEC) | (1 << TRANSIENT), TRIGGER_ALWAYS);
+  setBreakpoint(numbkpts - 1, addr, 0xffff, (1 << BRKPT_EXEC) | (1 << TRANSIENT), TRIGGER_ALWAYS);
   doCmdContinue(params);
 }
 

firmware/AtomBusMon.h

@@ -76,7 +76,8 @@ void doCmdStep(char *params);
 void doCmdTest(char *params);
 void doCmdSave(char *params);
 void doCmdSRec(char *params);
-void doCmdSpecial(char *params);
+void doCmdTimerMode(char *params);
+void doCmdTimeout(char *params);
 void doCmdTrace(char *params);
 void doCmdTrigger(char *params);
 void doCmdWatchI(char *params);
@@ -86,5 +87,9 @@ void doCmdWatchWrIO(char *params);
 void doCmdWatchWrMem(char *params);
 void doCmdWriteIO(char *params);
 void doCmdWriteMem(char *params);
+void doCmdXCmd0(char *params);
+void doCmdXCmd1(char *params);
+void doCmdXCmd2(char *params);
+void doCmdXCmd3(char *params);
 
 #endif

firmware/dis.h

@@ -6,6 +6,10 @@
 #define PDC_DDR          DDRA
 #define PDC_DIN          PINA
 
-addr_t disassemble(addr_t addr);
+#define MODE_NORMAL      0
+#define MODE_DIS_CMD     1
+
+addr_t disassemble(addr_t addr, uint8_t m);
+
 
 #endif

firmware/dis6502.c

@@ -149,7 +149,7 @@ static const unsigned char dopname[256] PROGMEM =
 
 static const unsigned char dopaddr[256] PROGMEM =
 {
-/*00*/ IMP, INDX,  IMP, IMP,  IMP,  ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  IMP,    ABS,   ABS,  IMP,
+/*00*/ IMM, INDX,  IMP, IMP,  IMP,  ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  IMP,    ABS,   ABS,  IMP,
 /*10*/ BRA, INDY,  IMP, IMP,  IMP,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  IMP,    ABSX,  ABSX, IMP,
 /*20*/ ABS, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
 /*30*/ BRA, INDY,  IMP, IMP,  IMP,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  IMP,    ABSX,  ABSX, IMP,
@@ -167,7 +167,7 @@ static const unsigned char dopaddr[256] PROGMEM =
 /*F0*/ BRA, INDY,  IMP, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP
 };
 
-addr_t disassemble(addr_t addr)
+addr_t disassemble(addr_t addr, uint8_t m)
 {
 
   char buffer[40];

firmware/dis65c02.c

@@ -169,7 +169,7 @@ static const unsigned char dopname[256] PROGMEM =
 
 static const unsigned char dopaddr[256] PROGMEM =
 {
-/*00*/ IMP, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
+/*00*/ IMM, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
 /*10*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMPA,  IMP,  ABS,    ABSX,  ABSX, IMP,
 /*20*/ ABS, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
 /*30*/ BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMPA,  IMP,  ABSX,   ABSX,  ABSX, IMP,
@@ -187,7 +187,7 @@ static const unsigned char dopaddr[256] PROGMEM =
 /*F0*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP
 };
 
-addr_t disassemble(addr_t addr)
+addr_t disassemble(addr_t addr, uint8_t m)
 {
 
   char buffer[40];

firmware/dis6809.c

@@ -647,7 +647,7 @@ static char *strcc(char *ptr, uint8_t val) {
 
 /* disassemble one instruction at address addr and return the address of the next instruction */
 
-addr_t disassemble(addr_t addr) {
+addr_t disassemble(addr_t addr, uint8_t m) {
   uint8_t d = get_memb(addr);
   uint8_t s;
   int8_t i;

firmware/disz80.c

@@ -530,9 +530,9 @@ static const unsigned char cmd_ED40[192] PROGMEM = {
     NOP,0,0
   };
 
-static const char word_EX_HALT[] PROGMEM = "**HALT**";
-static const char word_EX_INT[] PROGMEM = "**INT**";
-static const char word_EX_NMI[] PROGMEM = "**NMI**";
+static const char msg_HALT[] PROGMEM = "**HALT**\n";
+static const char msg_INT[] PROGMEM = "**INT**\n";
+static const char msg_NMI[] PROGMEM = "**NMI**\n";
 
 unsigned char cmd_halt[] = { HALT,0,0 };
 unsigned char cmd_nop[]  = { NOP,0,0 };
@@ -887,12 +887,15 @@ char * disassem (char *ptr, unsigned int *ip) {
   return ptr;
 }
 
-addr_t disassemble(addr_t addr) {
+addr_t disassemble(addr_t addr, uint8_t m) {
   static char buffer[64];
 
   char *ptr;
   addr_t addr2 = addr;
 
+  // Ignore the current CPU state in the disassemble connamd
+  uint8_t pdc = (m == MODE_DIS_CMD) ? 0 : PDC_DIN;
+
   // 0123456789012345678901234567890123456789
   // AAAA : HH HH HH HH : LD   RR,($XXXX)
 
@@ -905,17 +908,18 @@ addr_t disassemble(addr_t addr) {
 
   // Opcode
   ptr = buffer + 21;
-  if (PDC_DIN & 0x80) {
-    strcpy_P(ptr, PSTR("**HALT**"));
-  } else if (PDC_DIN & 0x40) {
-    strcpy(ptr, PSTR("**NMI**"));
-  } else if (PDC_DIN & 0x20) {
-    strcpy(ptr, PSTR("**INT**"));
+
+  if (pdc & 0x80) {
+    strcpy_P(ptr, msg_HALT);
+  } else if (pdc & 0x40) {
+    strcpy(ptr, msg_NMI);
+  } else if (pdc & 0x20) {
+    strcpy(ptr, msg_INT);
   } else {
     ptr = disassem(ptr, &addr2);
+    *ptr++ = '\n';
+    *ptr++ = '\0';
   }
-  *ptr++ = '\n';
-  *ptr++ = '\0';
 
   // Hex
   loadAddr(addr);

release.sh

@@ -16,8 +16,9 @@ pushd target
 make clean
 make
 
-cp --parents */*/*.bit ../${DIR}
-cp --parents */*/*.mcs ../${DIR}
+cp --parents */*/ice*.bit ../${DIR}
+cp --parents */*/ice*.bin ../${DIR}
+cp --parents */*/ice*.mcs ../${DIR}
 
 popd
 
@@ -27,5 +28,3 @@ popd
 
 echo "Built release in: "${DIR}
 unzip -l releases/${NAME}.zip
-
- 

src/BusMonCore.vhd

@@ -71,8 +71,8 @@ entity BusMonCore is
         DataIn           : in std_logic_vector(7 downto 0);
         Done             : in std_logic;
 
-        -- Special outputs (function is CPU specific)
-        Special          : out std_logic_vector(1 downto 0);
+        -- External Interrupt Control
+        int_ctrl         : out std_logic_vector(7 downto 0) := x"00";
 
         -- Single Step interface
         SS_Single        : out std_logic;
@@ -124,15 +124,18 @@ architecture behavioral of BusMonCore is
     signal cmd_ack         : std_logic;
     signal cmd_ack1        : std_logic;
     signal cmd_ack2        : std_logic;
-    signal cmd             : std_logic_vector(4 downto 0);
+    signal cmd             : std_logic_vector(5 downto 0);
 
     signal addr_sync       : std_logic_vector(15 downto 0);
     signal addr_inst       : std_logic_vector(15 downto 0);
     signal Addr1           : std_logic_vector(15 downto 0);
     signal Data1           : std_logic_vector(7 downto 0);
 
+    signal ext_clk         : std_logic;
+    signal timer0Count     : std_logic_vector(23 downto 0);
+    signal timer1Count     : std_logic_vector(23 downto 0);
     signal cycleCount      : std_logic_vector(23 downto 0);
-    signal cycleCount_inst : std_logic_vector(23 downto 0);
+    signal instrCount      : std_logic_vector(23 downto 0);
 
     signal single          : std_logic;
     signal reset           : std_logic;
@@ -181,6 +184,8 @@ architecture behavioral of BusMonCore is
 
     signal dropped_counter : std_logic_vector(3 downto 0);
 
+    signal timer_mode      : std_logic_vector(1 downto 0);
+
 begin
 
     inst_oho_dy1 : entity work.Oho_Dy1 port map (
@@ -224,9 +229,9 @@ begin
         portbout(2)          => cmd(2),
         portbout(3)          => cmd(3),
         portbout(4)          => cmd(4),
-        portbout(5)          => cmd_edge,
-        portbout(6)          => Special(0),
-        portbout(7)          => Special(1),
+        portbout(5)          => cmd(5),
+        portbout(6)          => cmd_edge,
+        portbout(7)          => open,
 
         -- Status Port
         portdin(0)           => '0',
@@ -289,7 +294,7 @@ begin
     -- DataWr1 is the data being written delayed by 1 cycle
     -- DataRd is the data being read, that is already one cycle late
     -- bw_state1(1) is 1 for writes, and 0 for reads
-    fifo_din <= cycleCount_inst & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
+    fifo_din <= instrCount & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
 
     -- Implement a 4-bit saturating counter of the number of dropped events
     process (busmon_clk)
@@ -325,9 +330,9 @@ begin
     mux <= addr_inst(7 downto 0)            when muxsel = 0 else
            addr_inst(15 downto 8)           when muxsel = 1 else
            din_reg                          when muxsel = 2 else
-           cycleCount(23 downto 16)         when muxsel = 3 else
-           cycleCount(7 downto 0)           when muxsel = 4 else
-           cycleCount(15 downto 8)          when muxsel = 5 else
+           instrCount(23 downto 16)         when muxsel = 3 else
+           instrCount(7 downto 0)           when muxsel = 4 else
+           instrCount(15 downto 8)          when muxsel = 5 else
 
            fifo_dout(7 downto 0)            when muxsel = 6 else
            fifo_dout(15 downto 8)           when muxsel = 7 else
@@ -432,40 +437,55 @@ begin
     end process;
 
     -- CPU Control Commands
-    -- 0000x Enable/Disable single stepping
-    -- 0001x Enable/Disable breakpoints / watches
-    -- 0010x Load breakpoint / watch register
-    -- 0011x Reset CPU
-    -- 01000 Singe Step CPU
-    -- 01001 Read FIFO
-    -- 01010 Reset FIFO
-    -- 01011 Unused
-    -- 0110x Load address/data register
-    -- 0111x Unused
-    -- 10000 Read Memory
-    -- 10001 Read Memory and Auto Inc Address
-    -- 10010 Write Memory
-    -- 10011 Write Memory and Auto Inc Address
-    -- 10100 Read IO
-    -- 10101 Read IO and Auto Inc Address
-    -- 10110 Write IO
-    -- 10111 Write IO and Auto Inc Address
-    -- 11000 Execute 6502 instruction
-    -- 111xx Unused
-    -- 11x1x Unused
-    -- 11xx1 Unused
+    -- 00000x Enable/Disable single stepping
+    -- 00001x Enable/Disable breakpoints / watches
+    -- 00010x Load breakpoint / watch register
+    -- 00011x Reset CPU
+    -- 001000 Singe Step CPU
+    -- 001001 Read FIFO
+    -- 001010 Reset FIFO
+    -- 001011 Unused
+    -- 00110x Load address/data register
+    -- 00111x Unused
+    -- 010000 Read Memory
+    -- 010001 Read Memory and Auto Inc Address
+    -- 010010 Write Memory
+    -- 010011 Write Memory and Auto Inc Address
+    -- 010100 Read IO
+    -- 010101 Read IO and Auto Inc Address
+    -- 010110 Write IO
+    -- 010111 Write IO and Auto Inc Address
+    -- 011000 Execute 6502 instruction
+    -- 0111xx Unused
+    -- 011x1x Unused
+    -- 011xx1 Unused
+    -- 10xxxx Int Ctrl
+    -- 1100xx Timer Mode
+    --     00 - count cpu cycles where clken = 1 and CountCycle = 1
+    --     01 - count cpu cycles where clken = 1 (ignoring CountCycle)
+    --     10 - free running timer, using busmon_clk as the source
+    --     11 - free running timer, using trig0 as the source
+
+    -- Use trig0 to drive a free running counter for absolute timings
+    ext_clk <= trig(0);
+    timer1Process: process (ext_clk)
+    begin
+        if rising_edge(ext_clk) then
+            timer1Count <= timer1Count + 1;
+        end if;
+    end process;
 
     cpuProcess: process (busmon_clk)
     begin
         if rising_edge(busmon_clk) then
+            timer0Count <= timer0Count + 1;
             if busmon_clken = '1' then
-                -- Cycle counter, wraps every 16s at 1MHz
+                -- Cycle counter
                 if (cpu_reset_n = '0') then
                     cycleCount <= (others => '0');
-                elsif (CountCycle = '1') then
+                elsif (CountCycle = '1' or timer_mode(0) = '1') then
                     cycleCount <= cycleCount + 1;
                 end if;
-
                 -- Command processing
                 cmd_edge1 <= cmd_edge;
                 cmd_edge2 <= cmd_edge1;
@@ -479,60 +499,68 @@ begin
                 exec      <= '0';
                 SS_Step   <= '0';
                 if (cmd_edge2 /= cmd_edge1) then
-                    if (cmd(4 downto 1) = "0000") then
+                    if (cmd(5 downto 1) = "00000") then
                         single <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 1) = "0001") then
+                    if (cmd(5 downto 1) = "00001") then
                         brkpt_enable <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 1) = "0010") then
+                    if (cmd(5 downto 1) = "00010") then
                         brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
                     end if;
 
-                    if (cmd(4 downto 1) = "0110") then
+                    if (cmd(5 downto 1) = "00110") then
                         addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
                     end if;
 
-                    if (cmd(4 downto 1) = "0011") then
+                    if (cmd(5 downto 1) = "00011") then
                         reset <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 0) = "01001") then
+                    if (cmd(5 downto 0) = "01001") then
                         fifo_rd <= '1';
                     end if;
 
-                    if (cmd(4 downto 0) = "01010") then
+                    if (cmd(5 downto 0) = "01010") then
                         fifo_rst <= '1';
                     end if;
 
-                    if (cmd(4 downto 1) = "1000") then
+                    if (cmd(5 downto 1) = "01000") then
                         memory_rd <= '1';
                         auto_inc  <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 1) = "1001") then
+                    if (cmd(5 downto 1) = "01001") then
                         memory_wr <= '1';
                         auto_inc  <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 1) = "1010") then
+                    if (cmd(5 downto 1) = "01010") then
                         io_rd <= '1';
                         auto_inc  <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 1) = "1011") then
+                    if (cmd(5 downto 1) = "01011") then
                         io_wr <= '1';
                         auto_inc  <= cmd(0);
                     end if;
 
-                    if (cmd(4 downto 0) = "11000") then
+                    if (cmd(5 downto 0) = "011000") then
                         exec <= '1';
                     end if;
 
+                    if (cmd(5 downto 4) = "10") then
+                        int_ctrl(to_integer(unsigned(cmd(3 downto 2))) * 2 + 1 downto to_integer(unsigned(cmd(3 downto 2))) * 2) <= cmd(1 downto 0);
+                    end if;
+
+                    if (cmd(5 downto 2) = "1100") then
+                        timer_mode <= cmd(1 downto 0);
+                    end if;
+
                     -- Acknowlege certain commands immediately
-                    if cmd(4) = '0' then
+                    if cmd(5 downto 4) /= "01" then
                         cmd_ack <= not cmd_ack;
                     end if;
 
@@ -552,7 +580,7 @@ begin
                     single <= '1';
                 end if;
 
-                if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "01000")) then
+                if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "001000")) then
                     Rdy_int <= (not brkpt_active);
                     SS_Step <= (not brkpt_active);
                 else
@@ -562,7 +590,13 @@ begin
                 -- Latch instruction address for the whole cycle
                 if (Sync = '1') then
                     addr_inst <= Addr;
-                    cycleCount_inst <= cycleCount;
+                    if timer_mode = "10" then
+                        instrCount <= timer0Count;
+                    elsif timer_mode = "11" then
+                        instrCount <= timer1Count;
+                    else
+                        instrCount <= cycleCount;
+                    end if;
                 end if;
 
                 -- Breakpoints and Watches written to the FIFO

src/MC6809CpuMon.vhd

@@ -101,6 +101,7 @@ architecture behavioral of MC6809CpuMon is
     signal Addr_int       : std_logic_vector(15 downto 0);
     signal Din            : std_logic_vector(7 downto 0);
     signal Dout           : std_logic_vector(7 downto 0);
+    signal Dbusmon        : std_logic_vector(7 downto 0);
     signal Sync_int       : std_logic;
     signal hold           : std_logic;
 
@@ -123,7 +124,7 @@ architecture behavioral of MC6809CpuMon is
     signal SS_Single      : std_logic;
     signal SS_Step        : std_logic;
     signal CountCycle     : std_logic;
-    signal special        : std_logic_vector(1 downto 0);
+    signal int_ctrl       : std_logic_vector(7 downto 0);
 
     signal LIC_int        : std_logic;
 
@@ -139,9 +140,10 @@ architecture behavioral of MC6809CpuMon is
     signal data_wr        : std_logic;
     signal nRSTout        : std_logic;
 
-    signal NMI_n_masked   : std_logic;
-    signal IRQ_n_masked   : std_logic;
     signal FIRQ_n_masked  : std_logic;
+    signal IRQ_n_masked   : std_logic;
+    signal NMI_n_masked   : std_logic;
+    signal RES_n_masked   : std_logic;
 
 begin
 
@@ -176,14 +178,14 @@ begin
         cpu_clk      => cpu_clk,
         cpu_clken    => '1',
         Addr         => Addr_int,
-        Data         => Data,
+        Data         => Dbusmon,
         Rd_n         => not R_W_n_int,
         Wr_n         => R_W_n_int,
         RdIO_n       => '1',
         WrIO_n       => '1',
         Sync         => Sync_int,
         Rdy          => open,
-        nRSTin       => RES_n,
+        nRSTin       => RES_n_masked,
         nRSTout      => cpu_reset_n,
         CountCycle   => CountCycle,
         trig         => trig,
@@ -206,14 +208,28 @@ begin
         DataOut      => memory_dout,
         DataIn       => memory_din,
         Done         => memory_done,
-        Special      => special,
+        int_ctrl     => int_ctrl,
         SS_Step      => SS_Step,
         SS_Single    => SS_Single
     );
 
-    NMI_n_masked  <= NMI_n  or special(1);
-    FIRQ_n_masked <= FIRQ_n or special(1);
-    IRQ_n_masked  <= IRQ_n  or special(0);
+    -- The two int control bits work as follows
+    -- 00 -> IRQ_n                (enabled)
+    -- 01 -> IRQ_n or SS_Single   (enabled when free-running)
+    -- 10 -> 0                    (forced)
+    -- 11 -> 1                    (disabled)
+
+    FIRQ_n_masked <= int_ctrl(0) when int_ctrl(1) = '1' else
+                     FIRQ_n or (int_ctrl(0) and SS_single);
+
+    IRQ_n_masked  <= int_ctrl(2) when int_ctrl(3) = '1' else
+                     IRQ_n or (int_ctrl(2) and SS_single);
+
+    NMI_n_masked  <= int_ctrl(4) when int_ctrl(5) = '1' else
+                     NMI_n or (int_ctrl(4) and SS_single);
+
+    RES_n_masked  <= int_ctrl(6) when int_ctrl(7) = '1' else
+                     RES_n or (int_ctrl(6) and SS_single);
 
     -- The CPU is slightly pipelined and the register update of the last
     -- instruction overlaps with the opcode fetch of the next instruction.
@@ -339,6 +355,13 @@ begin
                          Dout when TSC = '0' and data_wr = '1' and R_W_n_int = '0' and memory_rd1 = '0' else
                   (others => 'Z');
 
+    -- Version of data seen by the Bus Mon need to use Din rather than the
+    -- external bus value as by the rising edge of cpu_clk we will have stopped driving
+    -- the external bus. On the ALS version we get away way this, but on the GODIL
+    -- version, due to the pullups, we don't. So all write watch breakpoints see
+    -- the data bus as 0xFF.
+    Dbusmon   <= Din when R_W_n_int = '1' else Dout;
+
     memory_done <= memory_rd1 or memory_wr1;
 
     -- Delayed/Deglitched version of the E clock

src/MOS6502CpuMon.vhd

@@ -48,14 +48,14 @@ entity MOS6502CpuMon is
         Rdy             : in    std_logic;
 
         -- External trigger inputs
-        trig             : in    std_logic_vector(1 downto 0);
+        trig            : in    std_logic_vector(1 downto 0);
 
         -- Jumpers
-        fakeTube_n      : in     std_logic;
+        fakeTube_n      : in    std_logic;
 
         -- Serial Console
-        avr_RxD         : in     std_logic;
-        avr_TxD         : out    std_logic;
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
 
         -- Switches
         sw_reset_cpu    : in    std_logic;
@@ -67,9 +67,12 @@ entity MOS6502CpuMon is
         led_trig1       : out   std_logic;
 
         -- OHO_DY1 connected to test connector
-        tmosi            : out   std_logic;
-        tdin             : out   std_logic;
-        tcclk            : out   std_logic
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
+
+        -- Test connector signals
+        test            : inout std_logic_vector(3 downto 0)
     );
 end MOS6502CpuMon;
 
@@ -141,7 +144,8 @@ begin
         led_trig1    => led_trig1,
         tmosi        => tmosi,
         tdin         => tdin,
-        tcclk        => tcclk
+        tcclk        => tcclk,
+        test         => test
     );
 
     sync_gen : process(cpu_clk)

src/MOS6502CpuMonALS.vhd

@@ -79,18 +79,21 @@ entity MOS6502CpuMonALS is
         avr_TxD          : out   std_logic;
 
         -- Switches
-        sw1               : in   std_logic;
-        sw2               : in   std_logic;
+        sw1              : in   std_logic;
+        sw2              : in   std_logic;
 
         -- LEDs
-        led1              : out  std_logic;
-        led2              : out  std_logic;
-        led3              : out  std_logic;
+        led1             : out  std_logic;
+        led2             : out  std_logic;
+        led3             : out  std_logic;
 
         -- OHO_DY1 LED display
-        tmosi             : out  std_logic;
-        tdin              : out  std_logic;
-        tcclk             : out  std_logic
+        tmosi            : out  std_logic;
+        tdin             : out  std_logic;
+        tcclk            : out  std_logic;
+
+        -- Test connector signals
+        test             : inout std_logic_vector(3 downto 0)
     );
 end MOS6502CpuMonALS;
 
@@ -166,7 +169,10 @@ begin
             -- OHO_DY1 LED display
             tmosi            => tmosi,
             tdin             => tdin,
-            tcclk            => tcclk
+            tcclk            => tcclk,
+
+            -- Test signals
+            test             => test
             );
 
     -- 6502 Outputs

src/MOS6502CpuMonCore.vhd

@@ -67,7 +67,10 @@ entity MOS6502CpuMonCore is
         -- OHO_DY1 connected to test connector
         tmosi           : out   std_logic;
         tdin            : out   std_logic;
-        tcclk           : out   std_logic
+        tcclk           : out   std_logic;
+
+        -- Test connector signals
+        test            : inout std_logic_vector(3 downto 0)
     );
 end MOS6502CpuMonCore;
 
@@ -82,8 +85,10 @@ architecture behavioral of MOS6502CpuMonCore is
     signal Din_int       : std_logic_vector(7 downto 0);
     signal Dout_int      : std_logic_vector(7 downto 0);
     signal R_W_n_int     : std_logic;
-    signal Rd_n_int      : std_logic;
-    signal Wr_n_int      : std_logic;
+    signal Rd_n_mon      : std_logic;
+    signal Wr_n_mon      : std_logic;
+    signal Sync_mon      : std_logic;
+    signal Done_mon      : std_logic;
     signal Sync_int      : std_logic;
     signal Addr_int      : std_logic_vector(23 downto 0);
 
@@ -98,7 +103,7 @@ architecture behavioral of MOS6502CpuMonCore is
     signal SS_Step       : std_logic;
     signal SS_Step_held  : std_logic;
     signal CountCycle    : std_logic;
-    signal special       : std_logic_vector(1 downto 0);
+    signal int_ctrl      : std_logic_vector(7 downto 0);
 
     signal memory_rd     : std_logic;
     signal memory_rd1    : std_logic;
@@ -109,8 +114,11 @@ architecture behavioral of MOS6502CpuMonCore is
     signal memory_din    : std_logic_vector(7 downto 0);
     signal memory_done   : std_logic;
 
-    signal NMI_n_masked  : std_logic;
+
     signal IRQ_n_masked  : std_logic;
+    signal NMI_n_masked  : std_logic;
+    signal Res_n_masked  : std_logic;
+    signal SO_n_masked   : std_logic;
 
     signal exec          : std_logic;
     signal exec_held     : std_logic;
@@ -131,13 +139,13 @@ begin
         cpu_clken    => cpu_clken,
         Addr         => Addr_int(15 downto 0),
         Data         => Data,
-        Rd_n         => Rd_n_int,
-        Wr_n         => Wr_n_int,
+        Rd_n         => Rd_n_mon,
+        Wr_n         => Wr_n_mon,
         RdIO_n       => '1',
         WrIO_n       => '1',
-        Sync         => Sync_int,
+        Sync         => Sync_mon,
         Rdy          => open,
-        nRSTin       => Res_n,
+        nRSTin       => Res_n_masked,
         nRSTout      => cpu_reset_n,
         CountCycle   => CountCycle,
         trig         => trig,
@@ -160,16 +168,35 @@ begin
         AddrOut      => memory_addr,
         DataOut      => memory_dout,
         DataIn       => memory_din,
-        Done         => memory_done,
-        Special      => special,
+        Done         => Done_mon,
+        int_ctrl     => int_ctrl,
         SS_Step      => SS_Step,
         SS_Single    => SS_Single
     );
-    Wr_n_int <= R_W_n_int;
-    Rd_n_int <= not R_W_n_int;
+    Wr_n_mon <= Rdy and R_W_n_int;
+    Rd_n_mon <= Rdy and not R_W_n_int;
+    Sync_mon <= Rdy and Sync_int;
+    Done_mon <= Rdy and memory_done;
+
     Data <= Din when R_W_n_int = '1' else Dout_int;
-    NMI_n_masked <= NMI_n or special(1);
-    IRQ_n_masked <= IRQ_n or special(0);
+
+    -- The two int control bits work as follows
+    -- 00 -> IRQ_n                (enabled)
+    -- 01 -> IRQ_n or SS_Single   (enabled when free-running)
+    -- 10 -> 0                    (forced)
+    -- 11 -> 1                    (disabled)
+
+    IRQ_n_masked <= int_ctrl(0) when int_ctrl(1) = '1' else
+                    IRQ_n or (int_ctrl(0) and SS_single);
+
+    NMI_n_masked <= int_ctrl(2) when int_ctrl(3) = '1' else
+                    NMI_n or (int_ctrl(2) and SS_single);
+
+    Res_n_masked <= int_ctrl(4) when int_ctrl(5) = '1' else
+                     Res_n or (int_ctrl(4) and SS_single);
+
+    SO_n_masked  <= int_ctrl(6) when int_ctrl(7) = '1' else
+                    SO_n or (int_ctrl(6) and SS_single);
 
     -- The CPU is slightly pipelined and the register update of the last
     -- instruction overlaps with the opcode fetch of the next instruction.
@@ -204,7 +231,7 @@ begin
         inst_t65: entity work.T65 port map (
             mode            => "00",
             Abort_n         => '1',
-            SO_n            => SO_n,
+            SO_n            => SO_n_masked,
             Res_n           => cpu_reset_n,
             Enable          => cpu_clken_ss,
             Clk             => cpu_clk,
@@ -367,4 +394,10 @@ begin
 
     memory_din <= Din;
 
+    -- Test outputs
+    test(0) <= SS_Single;     -- GODIL J5 pin 1 (46)
+    test(1) <= 'Z';           -- GODIL J5 pin 2 (47)
+    test(2) <= 'Z';           -- GODIL J5 pin 3 (48)
+    test(3) <= 'Z';           -- GODIL J5 pin 4 (56)
+
 end behavioral;

src/T80/T80.vhd

@@ -21,7 +21,7 @@
 -- ****
 -- Z80 compatible microprocessor core
 --
--- Version : 0247
+-- Version : 0250
 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
 -- All rights reserved
 --
@@ -73,14 +73,14 @@
 --      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
 --      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
 --      0247 : Fixed bus req/ack cycle
+--      0250 : Added R800 Multiplier by TobiFlex 2017.10.15
 --
 
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use IEEE.STD_LOGIC_UNSIGNED.all;
-
-use work.all;
+use work.T80_Pack.all;
 
 entity T80 is
 	generic(
@@ -120,6 +120,7 @@ entity T80 is
 		NMICycle_n : out std_logic;
 		IntE       : out std_logic;
 		Stop       : out std_logic;
+		R800_mode  : in  std_logic := '0';
 		out0       : in  std_logic := '0';  -- 0 => OUT(C),0, 1 => OUT(C),255
 		REG        : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
 
@@ -129,136 +130,6 @@ entity T80 is
 end T80;
 
 architecture rtl of T80 is
-    component T80_MCode
-        generic(
-            Mode   : integer := 0;
-            Flag_C : integer := 0;
-            Flag_N : integer := 1;
-            Flag_P : integer := 2;
-            Flag_X : integer := 3;
-            Flag_H : integer := 4;
-            Flag_Y : integer := 5;
-            Flag_Z : integer := 6;
-            Flag_S : integer := 7
-        );
-        port(
-          IR          : in std_logic_vector(7 downto 0);
-          ISet        : in std_logic_vector(1 downto 0);
-          MCycle      : in std_logic_vector(2 downto 0);
-          F           : in std_logic_vector(7 downto 0);
-          NMICycle    : in std_logic;
-          IntCycle    : in std_logic;
-          XY_State    : in std_logic_vector(1 downto 0);
-          MCycles     : out std_logic_vector(2 downto 0);
-          TStates     : out std_logic_vector(2 downto 0);
-          Prefix      : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-          Inc_PC      : out std_logic;
-          Inc_WZ      : out std_logic;
-          IncDec_16   : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-          Read_To_Reg : out std_logic;
-          Read_To_Acc : out std_logic;
-          Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-          Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-          ALU_Op      : out std_logic_vector(3 downto 0);
-             -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-          Save_ALU    : out std_logic;
-          PreserveC   : out std_logic;
-          Arith16     : out std_logic;
-          Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-          IORQ        : out std_logic;
-          Jump        : out std_logic;
-          JumpE       : out std_logic;
-          JumpXY      : out std_logic;
-          Call        : out std_logic;
-          RstP        : out std_logic;
-          LDZ         : out std_logic;
-          LDW         : out std_logic;
-          LDSPHL      : out std_logic;
-          Special_LD  : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-          ExchangeDH  : out std_logic;
-          ExchangeRp  : out std_logic;
-          ExchangeAF  : out std_logic;
-          ExchangeRS  : out std_logic;
-          I_DJNZ      : out std_logic;
-          I_CPL       : out std_logic;
-          I_CCF       : out std_logic;
-          I_SCF       : out std_logic;
-          I_RETN      : out std_logic;
-          I_BT        : out std_logic;
-          I_BC        : out std_logic;
-          I_BTR       : out std_logic;
-          I_RLD       : out std_logic;
-          I_RRD       : out std_logic;
-          I_INRC      : out std_logic;
-          SetWZ       : out std_logic_vector(1 downto 0);
-          SetDI       : out std_logic;
-          SetEI       : out std_logic;
-          IMode       : out std_logic_vector(1 downto 0);
-          Halt        : out std_logic;
-          NoRead      : out std_logic;
-          Write       : out std_logic;
-          XYbit_undoc : out std_logic
-       );
-    end component;
-
-    component T80_ALU
-        generic(
-            Mode : integer := 0;
-            Flag_C : integer := 0;
-            Flag_N : integer := 1;
-            Flag_P : integer := 2;
-            Flag_X : integer := 3;
-            Flag_H : integer := 4;
-            Flag_Y : integer := 5;
-            Flag_Z : integer := 6;
-            Flag_S : integer := 7
-        );
-        port(
-            Arith16         : in  std_logic;
-            Z16             : in  std_logic;
-            WZ              : in  std_logic_vector(15 downto 0);
-            XY_State            : in  std_logic_vector(1 downto 0);
-            ALU_Op          : in  std_logic_vector(3 downto 0);
-            IR              : in  std_logic_vector(5 downto 0);
-            ISet            : in  std_logic_vector(1 downto 0);
-            BusA            : in  std_logic_vector(7 downto 0);
-            BusB            : in  std_logic_vector(7 downto 0);
-            F_In            : in  std_logic_vector(7 downto 0);
-            Q               : out std_logic_vector(7 downto 0);
-            F_Out           : out std_logic_vector(7 downto 0)
-        );
-    end component;
-
-    component T80_Reg
-        port(
-            Clk     : in  std_logic;
-            CEN     : in  std_logic;
-            WEH     : in  std_logic;
-            WEL     : in  std_logic;
-            AddrA   : in  std_logic_vector(2 downto 0);
-            AddrB   : in  std_logic_vector(2 downto 0);
-            AddrC   : in  std_logic_vector(2 downto 0);
-            DIH     : in  std_logic_vector(7 downto 0);
-            DIL     : in  std_logic_vector(7 downto 0);
-            DOAH    : out std_logic_vector(7 downto 0);
-            DOAL    : out std_logic_vector(7 downto 0);
-            DOBH    : out std_logic_vector(7 downto 0);
-            DOBL    : out std_logic_vector(7 downto 0);
-            DOCH    : out std_logic_vector(7 downto 0);
-            DOCL    : out std_logic_vector(7 downto 0);
-            DOR     : out std_logic_vector(127 downto 0);
-            DIRSet  : in  std_logic;
-            DIR     : in  std_logic_vector(127 downto 0)
-        );
-    end component;
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
 
 	-- Registers
 	signal ACC, F               : std_logic_vector(7 downto 0);
@@ -283,9 +154,13 @@ architecture rtl of T80 is
 
 	-- Help Registers
 	signal WZ                   : std_logic_vector(15 downto 0);        -- MEMPTR register
+	signal TmpAddr2             : std_logic_vector(15 downto 0);        -- Temporary address register
 	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
 	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
 	signal RegBusA_r            : std_logic_vector(15 downto 0);
+	signal MULU_Prod32          : std_logic_vector(31 downto 0);
+	signal MULU_tmp             : std_logic_vector(31 downto 0);
+	signal MULU_Fakt1           : std_logic_vector(15 downto 0);
 
 	signal ID16                 : signed(15 downto 0);
 	signal Save_Mux             : std_logic_vector(7 downto 0);
@@ -295,8 +170,8 @@ architecture rtl of T80 is
 	signal IntE_FF1             : std_logic;
 	signal IntE_FF2             : std_logic;
 	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
+	signal BusReq_s             : std_logic := '0';
+	signal BusAck               : std_logic := '0';
 	signal ClkEn                : std_logic;
 	signal NMI_s                : std_logic;
 	signal IStatus              : std_logic_vector(1 downto 0);
@@ -344,6 +219,7 @@ architecture rtl of T80 is
 	signal Set_BusA_To          : std_logic_vector(3 downto 0);
 	signal ALU_Op               : std_logic_vector(3 downto 0);
 	signal Save_ALU             : std_logic;
+	signal Rot_Akku             : std_logic;
 	signal PreserveC            : std_logic;
 	signal Arith16              : std_logic;
 	signal Set_Addr_To          : std_logic_vector(2 downto 0);
@@ -355,6 +231,8 @@ architecture rtl of T80 is
 	signal LDZ                  : std_logic;
 	signal LDW                  : std_logic;
 	signal LDSPHL               : std_logic;
+	signal LDHLSP               : std_logic;
+	signal ADDSPdd              : std_logic;
 	signal IORQ_i               : std_logic;
 	signal Special_LD           : std_logic_vector(2 downto 0);
 	signal ExchangeDH           : std_logic;
@@ -373,12 +251,15 @@ architecture rtl of T80 is
 	signal I_RRD                : std_logic;
 	signal I_RXDD               : std_logic;
 	signal I_INRC               : std_logic;
+	signal I_MULUB              : std_logic;
+	signal I_MULU               : std_logic;
 	signal SetWZ                : std_logic_vector(1 downto 0);
 	signal SetDI                : std_logic;
 	signal SetEI                : std_logic;
 	signal IMode                : std_logic_vector(1 downto 0);
 	signal Halt                 : std_logic;
 	signal XYbit_undoc          : std_logic;
+	signal No_PC                : std_logic;
 	signal DOR                  : std_logic_vector(127 downto 0);
 
 begin
@@ -418,6 +299,7 @@ begin
 			Set_BusA_To => Set_BusA_To,
 			ALU_Op      => ALU_Op,
 			Save_ALU    => Save_ALU,
+			Rot_Akku    => Rot_Akku,
 			PreserveC   => PreserveC,
 			Arith16     => Arith16,
 			Set_Addr_To => Set_Addr_To,
@@ -430,6 +312,8 @@ begin
 			LDZ         => LDZ,
 			LDW         => LDW,
 			LDSPHL      => LDSPHL,
+			LDHLSP      => LDHLSP,
+			ADDSPdd     => ADDSPdd,
 			Special_LD  => Special_LD,
 			ExchangeDH  => ExchangeDH,
 			ExchangeRp  => ExchangeRp,
@@ -446,6 +330,8 @@ begin
 			I_RLD       => I_RLD,
 			I_RRD       => I_RRD,
 			I_INRC      => I_INRC,
+			I_MULUB     => I_MULUB,
+			I_MULU      => I_MULU,
 			SetWZ       => SetWZ,
 			SetDI       => SetDI,
 			SetEI       => SetEI,
@@ -453,6 +339,8 @@ begin
 			Halt        => Halt,
 			NoRead      => NoRead,
 			Write       => Write,
+			R800_mode   => R800_mode,
+			No_PC       => No_PC,
 			XYbit_undoc => XYbit_undoc);
 
 	alu : T80_ALU
@@ -472,6 +360,7 @@ begin
 			WZ      => WZ,
 			XY_State=> XY_State,
 			ALU_Op  => ALU_Op_r,
+			Rot_Akku    => Rot_Akku,
 			IR      => IR(5 downto 0),
 			ISet    => ISet,
 			BusA    => BusA,
@@ -496,6 +385,8 @@ begin
 	process (RESET_n, CLK_n)
 		variable n : std_logic_vector(7 downto 0);
 		variable ioq : std_logic_vector(8 downto 0);
+		variable temp_c : unsigned(8 downto 0);
+		variable temp_h : unsigned(4 downto 0);
 	begin
 		if RESET_n = '0' then
 			PC <= (others => '0');  -- Program Counter
@@ -510,6 +401,11 @@ begin
 
 			ACC <= (others => '1');
 			F <= (others => '1');
+			if Mode = 3 then
+				ACC <= (others => '0');
+				F <= "11110000";
+			end if;
+
 			Ap <= (others => '1');
 			Fp <= (others => '1');
 			I <= (others => '0');
@@ -538,7 +434,7 @@ begin
 				R   <= unsigned(DIR(47 downto 40));
 				SP  <= unsigned(DIR(63 downto 48));
 				PC  <= unsigned(DIR(79 downto 64));
-				A   <= DIR(79 downto 64);
+				A <= DIR(79 downto 64);
 				IStatus <= DIR(209 downto 208);
 
 			elsif ClkEn = '1' then
@@ -548,7 +444,27 @@ begin
 
 				MCycles <= MCycles_d;
 
-				if IMode /= "11" then
+				if LDHLSP = '1' and MCycle = "011" and TState = 1 then
+					temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
+					temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
+					F(Flag_Z) <= '0';
+					F(Flag_N) <= '0';
+					F(Flag_H) <= temp_h(4);
+					F(Flag_C) <= temp_c(8);
+				end if;
+
+				if ADDSPdd = '1' and TState = 1 then
+					temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
+					temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
+					F(Flag_Z) <= '0';
+					F(Flag_N) <= '0';
+					F(Flag_H) <= temp_h(4);
+					F(Flag_C) <= temp_c(8);
+				end if;
+
+				if Mode = 3 then
+					IStatus <= "10";
+				elsif IMode /= "11" then
 					IStatus <= IMode;
 				end if;
 
@@ -582,6 +498,11 @@ begin
 							IR <= DInst;
 						end if;
 
+						if Mode <= 1 and IntCycle = '1' and IStatus = "10" then
+							-- IM2 vector address low byte from bus
+							WZ(7 downto 0) <= DInst;
+						end if;
+
 						ISet <= "00";
 						if Prefix /= "00" then
 							if Prefix = "11" then
@@ -629,7 +550,8 @@ begin
 						elsif MCycle = MCycles and NMICycle = '1' then
 							A <= "0000000001100110";
 							PC <= "0000000001100110";
-						elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						elsif ((Mode /= 3 and MCycle = "011") or (Mode = 3 and MCycle = "100"))
+							and IntCycle = '1' and IStatus = "10" then
 							A(15 downto 8) <= I;
 							A(7 downto 0) <= WZ(7 downto 0);
 							PC(15 downto 8) <= unsigned(I);
@@ -693,7 +615,12 @@ begin
 									end if;
 								end if;
 							when others =>
-								A <= std_logic_vector(PC);
+								if ISet = "10" and IR(7 downto 4) = x"B" and IR(2 downto 1) = "01" and MCycle = 3 and No_BTR = '0' then
+									-- INIR, INDR, OTIR, OTDR
+									A <= RegBusA_r;
+								elsif No_PC = '0' or No_BTR = '1' or (I_DJNZ = '1' and IncDecZ = '1') or Mode > 1 then
+									A <= std_logic_vector(PC);
+								end if;
 							end case;
 						end if;
 
@@ -704,29 +631,50 @@ begin
 						Save_ALU_r <= Save_ALU;
 						ALU_Op_r <= ALU_Op;
 
-						if I_CPL = '1' then
-							-- CPL
-							ACC <= not ACC;
-							F(Flag_Y) <= not ACC(5);
-							F(Flag_H) <= '1';
-							F(Flag_X) <= not ACC(3);
-							F(Flag_N) <= '1';
-						end if;
-						if I_CCF = '1' then
-							-- CCF
-							F(Flag_C) <= not F(Flag_C);
-							F(Flag_Y) <= ACC(5);
-							F(Flag_H) <= F(Flag_C);
-							F(Flag_X) <= ACC(3);
-							F(Flag_N) <= '0';
-						end if;
-						if I_SCF = '1' then
-							-- SCF
-							F(Flag_C) <= '1';
-							F(Flag_Y) <= ACC(5);
-							F(Flag_H) <= '0';
-							F(Flag_X) <= ACC(3);
-							F(Flag_N) <= '0';
+						if Mode = 3 then
+							if I_CPL = '1' then
+								-- CPL
+								ACC <= not ACC;
+								F(Flag_H) <= '1';
+								F(Flag_N) <= '1';
+							end if;
+							if I_CCF = '1' then
+								-- CCF
+								F(Flag_C) <= not F(Flag_C);
+								F(Flag_H) <= '0';
+								F(Flag_N) <= '0';
+							end if;
+							if I_SCF = '1' then
+								-- SCF
+								F(Flag_C) <= '1';
+								F(Flag_H) <= '0';
+								F(Flag_N) <= '0';
+							end if;
+						else
+							if I_CPL = '1' then
+								-- CPL
+								ACC <= not ACC;
+								F(Flag_Y) <= not ACC(5);
+								F(Flag_H) <= '1';
+								F(Flag_X) <= not ACC(3);
+								F(Flag_N) <= '1';
+							end if;
+							if I_CCF = '1' then
+								-- CCF
+								F(Flag_C) <= not F(Flag_C);
+								F(Flag_Y) <= ACC(5);
+								F(Flag_H) <= F(Flag_C);
+								F(Flag_X) <= ACC(3);
+								F(Flag_N) <= '0';
+							end if;
+							if I_SCF = '1' then
+								-- SCF
+								F(Flag_C) <= '1';
+								F(Flag_Y) <= ACC(5);
+								F(Flag_H) <= '0';
+								F(Flag_X) <= ACC(3);
+								F(Flag_N) <= '0';
+							end if;
 						end if;
 					end if;
 
@@ -777,6 +725,11 @@ begin
 						end if;
 					end if;
 
+					if ADDSPdd = '1' and TState = 2 then
+						WZ <= std_logic_vector(SP);
+						SP <= unsigned(signed(SP)+signed(Save_Mux));
+					end if;
+
 					if LDSPHL = '1' then
 						SP <= unsigned(RegBusC);
 					end if;
@@ -924,7 +877,12 @@ begin
 					when "11001" =>
 						SP(15 downto 8) <= unsigned(Save_Mux);
 					when "11011" =>
-						F <= Save_Mux;
+						if Mode = 3 then
+							F(7 downto 4) <= Save_Mux(7 downto 4);
+							F(3 downto 0) <= "0000"; -- bit 3 to 0 always return 0
+						else
+							F <= Save_Mux;
+						end if;
 					when others =>
 					end case;
 					if XYbit_undoc='1' then
@@ -935,6 +893,42 @@ begin
 		end if;
 	end process;
 
+---------------------------------------------------------------------------
+--
+-- Multiply
+--
+---------------------------------------------------------------------------
+	process (CLK_n, ACC, RegBusB, MULU_tmp, MULU_Fakt1, MULU_Prod32)
+	begin
+
+		MULU_tmp(31 downto 12) <= std_logic_vector((unsigned(MULU_Fakt1)*unsigned(MULU_Prod32(3 downto 0)))+unsigned("0000"&MULU_Prod32(31 downto 16)));
+		MULU_tmp(11 downto 0) <= MULU_Prod32(15 downto 4);
+
+		if rising_edge(CLK_n) then
+			if ClkEn = '1' then
+				if T_Res='1' then
+					if I_MULUB='1' then
+						MULU_Prod32(7 downto 0) <= ACC;
+						MULU_Prod32(15 downto 8) <= "--------";
+						MULU_Prod32(31 downto 16) <= X"0000";
+						MULU_Fakt1(7 downto 0) <= "00000000";
+						if Set_BusB_To(0) = '1' then
+							MULU_Fakt1(15 downto 8) <= RegBusB(7 downto 0);
+						else
+							MULU_Fakt1(15 downto 8) <= RegBusB(15 downto 8);
+						end if;
+					else
+						MULU_Prod32(15 downto 0) <= RegBusA;
+						MULU_Prod32(31 downto 16) <= X"0000";
+						MULU_Fakt1 <= RegBusB;
+					end if;
+				else
+					MULU_Prod32 <= MULU_tmp;
+				end if;
+			end if;
+		end if;
+	end process;
+
 ---------------------------------------------------------------------------
 --
 -- BC('), DE('), HL('), IX and IY
@@ -990,7 +984,9 @@ begin
 				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
 			-- EX HL,DL
 			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			Alternate & "01" when (ExchangeDH = '1' or I_MULU = '1') and TState = 4 else
+			-- LDHLSP
+			"010" when LDHLSP = '1' and TState = 4 else
 			-- Bus A / Write
 			RegAddrA_r;
 
@@ -1003,8 +999,8 @@ begin
 	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
 			signed(RegBusA) + 1;
 
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, I_MULU, T_Res,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP)
 	begin
 		RegWEH <= '0';
 		RegWEL <= '0';
@@ -1018,11 +1014,21 @@ begin
 			end case;
 		end if;
 
+		if I_MULU = '1' and (T_Res = '1' or TState = 4) then    -- TState = 4 DE write
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
 		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
 			RegWEH <= '1';
 			RegWEL <= '1';
 		end if;
 
+		if LDHLSP = '1' and MCycle = "010" and TState = 4 then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
 		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
 			case IncDec_16(1 downto 0) is
 			when "00" | "01" | "10" =>
@@ -1033,12 +1039,29 @@ begin
 		end if;
 	end process;
 
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	TmpAddr2 <= std_logic_vector(unsigned(signed(SP) + signed(Save_Mux)));
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16, I_MULU, MULU_Prod32, MULU_tmp, T_Res,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP, TmpAddr2)
 	begin
 		RegDIH <= Save_Mux;
 		RegDIL <= Save_Mux;
 
+		if I_MULU = '1' then
+			if T_Res = '1' then
+				RegDIH <= MULU_Prod32(31 downto 24);
+				RegDIL <= MULU_Prod32(23 downto 16);
+			else
+				RegDIH <= MULU_tmp(15 downto 8);    -- TState = 4 DE write
+				RegDIL <= MULU_tmp(7 downto 0);
+			end if;
+		end if;
+
+		if LDHLSP = '1' and MCycle = "010" and TState = 4 then
+			RegDIH <= TmpAddr2(15 downto 8);
+			RegDIL <= TmpAddr2(7 downto 0);
+		end if;
+
 		if ExchangeDH = '1' and TState = 3 then
 			RegDIH <= RegBusB(15 downto 8);
 			RegDIL <= RegBusB(7 downto 0);
@@ -1169,13 +1192,12 @@ begin
 	TS <= std_logic_vector(TState);
 	DI_Reg <= DI;
 	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
+	BUSAK_n <= not (BusAck and RESET_n);
 	IntCycle_n <= not IntCycle;
 	NMICycle_n <= not NMICycle;
 	IntE <= IntE_FF1;
 	IORQ <= IORQ_i;
 	Stop <= I_DJNZ;
-
 -------------------------------------------------------------------------
 --
 -- Main state machine
@@ -1189,7 +1211,7 @@ begin
 			TState <= "000";
 			Pre_XY_F_M <= "000";
 			Halt_FF <= '0';
-			BusAck <= '0';
+			--BusAck <= '0';
 			NMICycle <= '0';
 			IntCycle <= '0';
 			IntE_FF1 <= '0';
@@ -1198,10 +1220,9 @@ begin
 			Auto_Wait_t1 <= '0';
 			Auto_Wait_t2 <= '0';
 			M1_n <= '1';
-			BusReq_s <= '0';
+			--BusReq_s <= '0';
 			NMI_s <= '0';
 		elsif rising_edge(CLK_n) then
-
 			if DIRSet = '1' then
 				IntE_FF2 <= DIR(211);
 				IntE_FF1 <= DIR(210);
@@ -1249,13 +1270,20 @@ begin
 						BusAck <= '0';
 						if TState = 2 and Wait_n = '0' then
 						elsif T_Res = '1' then
-							if Halt = '1' then
+							if Halt = '1' and  ( not(Mode = 3 and INT_n = '0' and IntE_FF1 = '0')) then  -- halt bug when Mode = 3 , INT_n = '0' and IME=0
 								Halt_FF <= '1';
 							end if;
 							if BusReq_s = '1' then
 								BusAck <= '1';
 							else
 								TState <= "001";
+								if (IntCycle = '1' and Mode = 3) then -- GB: read interrupt at MCycle 3
+									if (MCycle = "010") then
+										M1_n <= '0';
+									else
+										M1_n <= '1';
+									end if;
+								end if;
 								if NextIs_XY_Fetch = '1' then
 									MCycle <= "110";
 									Pre_XY_F_M <= MCycle;
@@ -1277,6 +1305,8 @@ begin
 										IntCycle <= '1';
 										IntE_FF1 <= '0';
 										IntE_FF2 <= '0';
+									elsif (Halt_FF = '1' and INT_n = '0' and Mode = 3) then
+										Halt_FF <= '0';
 									end if;
 								else
 									MCycle <= std_logic_vector(unsigned(MCycle) + 1);

src/T80/T80_ALU.vhd

@@ -89,6 +89,7 @@ entity T80_ALU is
 		WZ              : in  std_logic_vector(15 downto 0);
 		XY_State		    : in  std_logic_vector(1 downto 0);
 		ALU_Op          : in  std_logic_vector(3 downto 0);
+		Rot_Akku        : in  std_logic;
 		IR              : in  std_logic_vector(5 downto 0);
 		ISet            : in  std_logic_vector(1 downto 0);
 		BusA            : in  std_logic_vector(7 downto 0);
@@ -158,7 +159,7 @@ begin
 		end if;
 	end process;
 
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, WZ, XY_State)
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, Rot_Akku, WZ, XY_State)
 		variable Q_t : std_logic_vector(7 downto 0);
 		variable DAA_Q : unsigned(8 downto 0);
 	begin
@@ -220,35 +221,64 @@ begin
 			end if;
 		when "1100" =>
 			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
+			if Mode = 3 then
+				F_Out(Flag_H) <= '0';
+				F_Out(Flag_C) <= F_In(Flag_C);
+				DAA_Q(7 downto 0) := unsigned(BusA);
+				DAA_Q(8) := '0';
+				if F_In(Flag_N) = '0' then
+					-- After addition
+					-- Alow > 9 or H = 1
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+							DAA_Q := DAA_Q + 6;
+					end if;
+					-- new Ahigh > 9 or C = 1
+					if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q + 96; -- 0x60
+					end if;
+				else
+					-- After subtraction
+					if F_In(Flag_H) = '1' then
+						DAA_Q := DAA_Q - 6;
+						if F_In(Flag_C) = '0' then
+							DAA_Q(8) := '0';
+						end if;
+					end if;
+					if F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q - 96; -- 0x60
 					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
 				end if;
 			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
+				F_Out(Flag_H) <= F_In(Flag_H);
+				F_Out(Flag_C) <= F_In(Flag_C);
+				DAA_Q(7 downto 0) := unsigned(BusA);
+				DAA_Q(8) := '0';
+				if F_In(Flag_N) = '0' then
+					-- After addition
+					-- Alow > 9 or H = 1
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+						if (DAA_Q(3 downto 0) > 9) then
+							F_Out(Flag_H) <= '1';
+						else
+							F_Out(Flag_H) <= '0';
+						end if;
+						DAA_Q := DAA_Q + 6;
+					end if;
+					-- new Ahigh > 9 or C = 1
+					if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q + 96; -- 0x60
+					end if;
+				else
+					-- After subtraction
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+						if DAA_Q(3 downto 0) > 5 then
+							F_Out(Flag_H) <= '0';
+						end if;
+						DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+					end if;
+					if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q - 352; -- 0x160
 					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
 				end if;
 			end if;
 			F_Out(Flag_X) <= DAA_Q(3);
@@ -368,6 +398,9 @@ begin
 				F_Out(Flag_S) <= F_In(Flag_S);
 				F_Out(Flag_Z) <= F_In(Flag_Z);
 			end if;
+			if Mode = 3 and Rot_Akku = '1'  then
+					F_Out(Flag_Z) <= '0';
+			end if; 
 		when others =>
 			null;
 		end case;

src/T80/T80_Pack.vhd

@@ -11,7 +11,7 @@
 --
 -- Z80 compatible microprocessor core
 --
--- Version : 0242
+-- Version : 0250
 --
 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
 --
@@ -84,7 +84,7 @@ package T80_Pack is
 	port(
 		RESET_n         : in std_logic;
 		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
+		CEN             : in std_logic;
 		WAIT_n          : in std_logic;
 		INT_n           : in std_logic;
 		NMI_n           : in std_logic;
@@ -96,16 +96,18 @@ package T80_Pack is
 		RFSH_n          : out std_logic;
 		HALT_n          : out std_logic;
 		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
+		A               : out std_logic_vector(15 downto 0);
 		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
+		DI              : in std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
 		IntCycle_n      : out std_logic;
 		NMICycle_n      : out std_logic;
 		IntE            : out std_logic;
 		Stop            : out std_logic;
+		R800_mode       : in  std_logic := '0';
+		out0            : in  std_logic := '0';  -- 0 => OUT(C),0, 1 => OUT(C),255
 		REG             : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
 		DIRSet          : in  std_logic := '0';
 		DIR             : in  std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
@@ -114,24 +116,24 @@ package T80_Pack is
 
 	component T80_Reg
 	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA                   : in std_logic_vector(2 downto 0);
-		AddrB                   : in std_logic_vector(2 downto 0);
-		AddrC                   : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH                    : out std_logic_vector(7 downto 0);
-		DOAL                    : out std_logic_vector(7 downto 0);
-		DOBH                    : out std_logic_vector(7 downto 0);
-		DOBL                    : out std_logic_vector(7 downto 0);
-		DOCH                    : out std_logic_vector(7 downto 0);
-		DOCL                    : out std_logic_vector(7 downto 0);
-		DOR                     : out std_logic_vector(127 downto 0);
-		DIRSet                  : in  std_logic;
-		DIR                     : in  std_logic_vector(127 downto 0)
+		Clk             : in std_logic;
+		CEN             : in std_logic;
+		WEH             : in std_logic;
+		WEL             : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH             : in std_logic_vector(7 downto 0);
+		DIL             : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0);
+		DOR             : out std_logic_vector(127 downto 0);
+		DIRSet          : in  std_logic;
+		DIR             : in  std_logic_vector(127 downto 0)
 	);
 	end component;
 
@@ -168,6 +170,7 @@ package T80_Pack is
 		ALU_Op                  : out std_logic_vector(3 downto 0);
 			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
 		Save_ALU                : out std_logic;
+		Rot_Akku                : out std_logic;
 		PreserveC               : out std_logic;
 		Arith16                 : out std_logic;
 		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
@@ -181,7 +184,7 @@ package T80_Pack is
 		LDW                     : out std_logic;
 		LDSPHL                  : out std_logic;
 		LDHLSP                  : out std_logic;
-		ADDSPdd						: out std_logic;
+		ADDSPdd                 : out std_logic;
 		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
 		ExchangeDH              : out std_logic;
 		ExchangeRp              : out std_logic;
@@ -198,12 +201,17 @@ package T80_Pack is
 		I_RLD                   : out std_logic;
 		I_RRD                   : out std_logic;
 		I_INRC                  : out std_logic;
+		I_MULUB                 : out std_logic;
+		I_MULU                  : out std_logic;
+		SetWZ                   : out std_logic_vector(1 downto 0);
 		SetDI                   : out std_logic;
 		SetEI                   : out std_logic;
 		IMode                   : out std_logic_vector(1 downto 0);
 		Halt                    : out std_logic;
 		NoRead                  : out std_logic;
 		Write                   : out std_logic;
+		R800_mode               : in  std_logic;
+		No_PC                   : out std_logic;
 		XYbit_undoc             : out std_logic
 	);
 	end component;
@@ -223,7 +231,10 @@ package T80_Pack is
 	port(
 		Arith16         : in  std_logic;
 		Z16             : in  std_logic;
+		WZ              : in  std_logic_vector(15 downto 0);
+		XY_State        : in  std_logic_vector(1 downto 0);
 		ALU_Op          : in  std_logic_vector(3 downto 0);
+		Rot_Akku        : in  std_logic;
 		IR              : in  std_logic_vector(5 downto 0);
 		ISet            : in  std_logic_vector(1 downto 0);
 		BusA            : in  std_logic_vector(7 downto 0);

src/T80/T80a.vhd

@@ -203,7 +203,7 @@ begin
     begin
         if CLK_n'event and CLK_n = '0' then
             if CEN = '1' then
-                Wait_s <= WAIT_n;
+                Wait_s <= WAIT_n or (IORQ_n_i and MREQ_n_i);
                 if TState = "011" and BUSAK_n_i = '1' then
                     DI_Reg <= to_x01(Din);
                 end if;

src/Z80CpuMon.vhd

@@ -110,15 +110,13 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
     signal RFSH_n_int     : std_logic;
     signal M1_n_int       : std_logic;
     signal BUSAK_n_int    : std_logic;
-    signal BUSAK_n_comb   : std_logic;
     signal WAIT_n_latched : std_logic;
     signal TState         : std_logic_vector(2 downto 0);
-    signal TState1        : std_logic_vector(2 downto 0);
     signal SS_Single      : std_logic;
     signal SS_Step        : std_logic;
     signal SS_Step_held   : std_logic;
     signal CountCycle     : std_logic;
-    signal special        : std_logic_vector(1 downto 0);
+    signal int_ctrl       : std_logic_vector(7 downto 0);
     signal skipNextOpcode : std_logic;
 
     signal Regs           : std_logic_vector(255 downto 0);
@@ -152,24 +150,19 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
     signal BUSRQ_n_sync   : std_logic;
     signal INT_n_sync     : std_logic;
     signal NMI_n_sync     : std_logic;
+    signal RESET_n_sync   : std_logic;
 
-    signal Rdy            : std_logic;
     signal Read_n         : std_logic;
     signal Read_n0        : std_logic;
-    signal Read_n1        : std_logic;
     signal Write_n        : std_logic;
     signal Write_n0       : std_logic;
     signal ReadIO_n       : std_logic;
     signal ReadIO_n0      : std_logic;
-    signal ReadIO_n1      : std_logic;
     signal WriteIO_n      : std_logic;
     signal WriteIO_n0     : std_logic;
     signal Sync           : std_logic;
     signal Sync0          : std_logic;
     signal Sync1          : std_logic;
-    signal Mem_IO_n       : std_logic;
-
-    signal MemState       : std_logic_vector(2 downto 0);
 
     signal Din            : std_logic_vector(7 downto 0);
     signal Dout           : std_logic_vector(7 downto 0);
@@ -226,7 +219,7 @@ begin
         WrIO_n       => WriteIO_n,
         Sync         => Sync,
         Rdy          => open,
-        nRSTin       => RESET_n,
+        nRSTin       => RESET_n_sync,
         nRSTout      => cpu_reset_n,
         CountCycle   => CountCycle,
         trig         => trig,
@@ -250,7 +243,7 @@ begin
         DataOut      => memory_dout,
         DataIn       => memory_din,
         Done         => memory_done,
-        Special      => special,
+        int_ctrl     => int_ctrl,
         SS_Single    => SS_Single,
         SS_Step      => SS_Step
     );
@@ -291,9 +284,31 @@ begin
     int_gen : process(CLK_n)
     begin
         if rising_edge(CLK_n) then
-            BUSRQ_n_sync <= BUSRQ_n;
-            NMI_n_sync   <= NMI_n or special(1);
-            INT_n_sync   <= INT_n or special(0);
+
+            if int_ctrl(1) = '1' then
+                BUSRQ_n_sync <= int_ctrl(0);
+            else
+                BUSRQ_n_sync <= BUSRQ_n or (int_ctrl(0) and SS_single);
+            end if;
+
+            if int_ctrl(3) = '1' then
+                INT_n_sync <= int_ctrl(2);
+            else
+                INT_n_sync <= INT_n or (int_ctrl(2) and SS_single);
+            end if;
+
+            if int_ctrl(5) = '1' then
+                NMI_n_sync <= int_ctrl(4);
+            else
+                NMI_n_sync <= NMI_n or (int_ctrl(4) and SS_single);
+            end if;
+
+            if int_ctrl(7) = '1' then
+                RESET_n_sync <= int_ctrl(6);
+            else
+                RESET_n_sync <= RESET_n or (int_ctrl(6) and SS_single);
+            end if;
+
         end if;
     end process;
 
@@ -327,40 +342,32 @@ begin
     -- really care about the data (it's re-read from memory by the disassembler).
     Sync0    <= '1' when WAIT_n = '1' and M1_n_int = '0' and TState = "010" and skipNextOpcode = '0' else '0';
 
-    -- For memory reads/write breakpoints we make the monitoring decision in the middle of T2
-    -- but only if WAIT_n is '1' so we catch the right data.
-    Read_n0    <= not (WAIT_n and (not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
-    Write_n0   <= not (WAIT_n and (    RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
-
-    -- For IO reads/writes we make the monitoring decision in the middle of the second T2 cycle
-    -- but only if WAIT_n is '1' so we catch the right data.
-    -- This one cycle delay accounts for the forced wait state
-    ReadIO_n0  <= not (WAIT_n and (not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState1 = "010" else '1';
-    WriteIO_n0 <= not (WAIT_n and (    RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState1 = "010" else '1';
+    -- For reads/write breakpoints we make the monitoring decision in the middle of T3
+    Read_n0    <= not ((not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "011" else '1';
+    Write_n0   <= not ((    RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "011" else '1';
+    ReadIO_n0  <= not ((not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "011" else '1';
+    WriteIO_n0 <= not ((    RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "011" else '1';
 
     -- Hold the monitoring decision so it is valid on the rising edge of the clock
-    -- For instruction fetches and writes, the monitor sees these at the start of T3
-    -- For reads, the data can arrive in the middle of T3 so delay until end of T3
+    -- For instruction fetches the monitor sees these at the end of T2
+    -- For reads and writes, the data is sampled in the middle of T3 so delay until end of T3
     watch_gen : process(CLK_n)
     begin
         if falling_edge(CLK_n) then
             Sync        <= Sync0;
-            Read_n1     <= Read_n0;
-            Read_n      <= Read_n1;
+            Read_n      <= Read_n0;
             Write_n     <= Write_n0;
-            ReadIO_n1   <= ReadIO_n0;
-            ReadIO_n    <= ReadIO_n1;
+            ReadIO_n    <= ReadIO_n0;
             WriteIO_n   <= WriteIO_n0;
             -- Latch wait seen by T80 on the falling edge, for use on the next rising edge
             WAIT_n_latched <= WAIT_n;
         end if;
     end process;
 
-    -- Register the exec data on the rising at the end of T2
+    -- Register the exec data on the rising edge of the clock at the end of T2
     ex_data_latch : process(CLK_n)
     begin
         if rising_edge(CLK_n) then
-            TState1 <= TState;
             if Sync = '1' then
                 ex_data <= Data;
             end if;
@@ -371,14 +378,14 @@ begin
     rd_data_latch : process(CLK_n)
     begin
         if falling_edge(CLK_n) then
-            if Read_n1 = '0' or ReadIO_n1 = '0' then
+            if Read_n0 = '0' or ReadIO_n0 = '0' then
                 rd_data <= Data;
             end if;
             memory_din <= Data;
         end if;
     end process;
 
-    -- Register the write data on the falling edge in the middle of T2
+    -- Register the read data on the falling edge of clock in the middle of T3
     wr_data_latch : process(CLK_n)
     begin
         if falling_edge(CLK_n) then
@@ -417,7 +424,7 @@ begin
     BUSAK_n    <= BUSAK_n_int when state = idle else mon_busak_n;
 
     -- Force the address and databus to tristate when reset is asserted
-    tristate_ad_n <= '0'         when RESET_n = '0' else
+    tristate_ad_n <= '0'         when RESET_n_sync = '0' else
                      BUSAK_n_int when state = idle  else
                      mon_busak_n1;
 

target/common/Makefile.inc

@@ -22,7 +22,7 @@ OBJCOPY=avr-objcopy
 
 PROG = avr_progmem
 
-CFLAGS=$(CPU_CFLAGS) -DF_CPU=${F_CPU}UL -DBAUD=${BAUD} -mmcu=$(MCU) -Wall -Os -mcall-prologues
+CFLAGS=$(CPU_CFLAGS) -DF_CPU=${F_CPU}UL -DBAUD=${BAUD} -std=c99 -mmcu=$(MCU) -Wall -Os -mcall-prologues
 
 OBJECTS=AtomBusMon.o status.o $(CPU_OBJECTS)
 
@@ -30,6 +30,7 @@ build: $(TARGET).mcs
 
 $(TARGET).mcs: $(TARGET).bit
 	promgen -u 0 $(TARGET).bit -o $(TARGET).mcs -p mcs -w -spi -s 8192
+	promgen -u 0 $(TARGET).bit -o $(TARGET).bin -p bin -w -spi -s 8192
 	rm -f $(TARGET).cfi $(TARGET).prm
 
 working/$(PROJECT).bit:

target/godil_250/_icez80/board.ucf

@@ -3,6 +3,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
 
 NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock49"  LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator
 
 NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1

target/godil_250/ice6502/board.ucf

@@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
 NET "Phi0" TNM_NET = clk_period_grp_phi0;
 TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33                           ; # 49.152 MHz Oscillator
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 1
 NET "Rdy"        LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 2

target/godil_250/ice65c02/board.ucf

@@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
 NET "Phi0" TNM_NET = clk_period_grp_phi0;
 TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33                           ; # 49.152 MHz Oscillator
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 1
 NET "Rdy"        LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 2

target/godil_250/ice6809/board.ucf

@@ -3,6 +3,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
 
 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 1
 NET "NMI_n"      LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 2
 NET "IRQ_n"      LOC="P18" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 3

target/godil_500/ice6502/board.ucf

@@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
 NET "Phi0" TNM_NET = clk_period_grp_phi0;
 TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33                           ; # 49.152 MHz Oscillator
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 1
 NET "Rdy"        LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 2

target/godil_500/ice65c02/board.ucf

@@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
 NET "Phi0" TNM_NET = clk_period_grp_phi0;
 TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33                           ; # 49.152 MHz Oscillator
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 1
 NET "Rdy"        LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 2

target/godil_500/ice6809/board.ucf

@@ -3,6 +3,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
 
 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 1
 NET "NMI_n"      LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 2
 NET "IRQ_n"      LOC="P18" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 3

target/godil_500/icez80/board.ucf

@@ -5,6 +5,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
 
 NET "clock49"  LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1
 NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 2
 NET "Addr<13>" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 3

target/lx9_dave/gen_mcs.sh

@@ -16,6 +16,9 @@ NAME=${DIR}/icemulti
 
 mkdir -p ${DIR}
 
+for FORMAT in mcs bin
+do
+
 promgen                                          \
  -u      0 loader/MultiBootLoader.bit            \
  -u  54000 unknown/UnknownAdapter.bit            \
@@ -23,6 +26,8 @@ promgen                                          \
  -u  FC000 icez80/icez80.bit                     \
  -u 150000 ice65c02/ice65c02.bit                 \
  -u 1A4000 ice6809/ice6809.bit                   \
- -o $NAME.mcs  -p mcs -w -spi -s 8192
+ -o $NAME.$FORMAT  -p $FORMAT -w -spi -s 8192
+
+done
 
 rm -f $NAME.cfi $NAME.prm

target/lx9_dave/ice6502/board.ucf

@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi = PERIOD "clk_period_grp_phi" 250ns LOW;
 
 NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 NET "VP_n"     LOC="P35"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
@@ -86,7 +88,7 @@ NET "tdin"     LOC="P61"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 NET "tcclk"    LOC="P62"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 
 # Test outputs (connect to J5 on FPGA board)
-#NET "test1"    LOC="P46"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test2"    LOC="P48"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test3"    LOC="P57"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test4"    LOC="P59"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<0>"  LOC="P46"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<1>"  LOC="P47"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<2>"  LOC="P48"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<3>"  LOC="P56"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

target/lx9_dave/ice65c02/board.ucf

@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi = PERIOD "clk_period_grp_phi" 250ns LOW;
 
 NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 NET "VP_n"     LOC="P35"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
@@ -86,7 +88,7 @@ NET "tdin"     LOC="P61"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 NET "tcclk"    LOC="P62"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 
 # Test outputs (connect to J5 on FPGA board)
-#NET "test1"    LOC="P46"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test2"    LOC="P48"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test3"    LOC="P57"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test4"    LOC="P59"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<0>"  LOC="P46"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<1>"  LOC="P47"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<2>"  LOC="P48"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<3>"  LOC="P56"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

target/lx9_dave/ice6809/board.ucf

@@ -3,6 +3,8 @@ TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;
 
 NET "E" CLOCK_DEDICATED_ROUTE = FALSE;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"          LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 #NET "VSS"           LOC="P"    | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

target/lx9_dave/icez80/board.ucf

@@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_clk_n = PERIOD "clk_period_grp_clk_n" 125ns LOW;
 
 NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 NET "Addr<11>" LOC="P43"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8          ; # dip pin 1

target/lx9_dave/ipcore/WatchEvents.vhd

@@ -22,7 +22,7 @@
 --    devices, or systems.  Use in such applications are expressly            --
 --    prohibited.                                                             --
 --                                                                            --
---    (c) Copyright 1995-2017 Xilinx, Inc.                                    --
+--    (c) Copyright 1995-2020 Xilinx, Inc.                                    --
 --    All rights reserved.                                                    --
 --------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
@@ -96,7 +96,7 @@ END COMPONENT;
       c_axis_type => 0,
       c_common_clock => 1,
       c_count_type => 0,
-      c_data_count_width => 10,
+      c_data_count_width => 13,
       c_default_value => "BlankString",
       c_din_width => 72,
       c_din_width_axis => 1,
@@ -179,7 +179,7 @@ END COMPONENT;
       c_overflow_low => 0,
       c_preload_latency => 0,
       c_preload_regs => 1,
-      c_prim_fifo_type => "512x72",
+      c_prim_fifo_type => "4kx9",
       c_prog_empty_thresh_assert_val => 4,
       c_prog_empty_thresh_assert_val_axis => 1022,
       c_prog_empty_thresh_assert_val_rach => 1022,
@@ -195,14 +195,14 @@ END COMPONENT;
       c_prog_empty_type_wach => 0,
       c_prog_empty_type_wdch => 0,
       c_prog_empty_type_wrch => 0,
-      c_prog_full_thresh_assert_val => 511,
+      c_prog_full_thresh_assert_val => 4095,
       c_prog_full_thresh_assert_val_axis => 1023,
       c_prog_full_thresh_assert_val_rach => 1023,
       c_prog_full_thresh_assert_val_rdch => 1023,
       c_prog_full_thresh_assert_val_wach => 1023,
       c_prog_full_thresh_assert_val_wdch => 1023,
       c_prog_full_thresh_assert_val_wrch => 1023,
-      c_prog_full_thresh_negate_val => 510,
+      c_prog_full_thresh_negate_val => 4094,
       c_prog_full_type => 0,
       c_prog_full_type_axis => 0,
       c_prog_full_type_rach => 0,
@@ -211,10 +211,10 @@ END COMPONENT;
       c_prog_full_type_wdch => 0,
       c_prog_full_type_wrch => 0,
       c_rach_type => 0,
-      c_rd_data_count_width => 10,
-      c_rd_depth => 512,
+      c_rd_data_count_width => 13,
+      c_rd_depth => 4096,
       c_rd_freq => 1,
-      c_rd_pntr_width => 9,
+      c_rd_pntr_width => 12,
       c_rdch_type => 0,
       c_reg_slice_mode_axis => 0,
       c_reg_slice_mode_rach => 0,
@@ -242,8 +242,8 @@ END COMPONENT;
       c_wach_type => 0,
       c_wdch_type => 0,
       c_wr_ack_low => 0,
-      c_wr_data_count_width => 10,
-      c_wr_depth => 512,
+      c_wr_data_count_width => 13,
+      c_wr_depth => 4096,
       c_wr_depth_axis => 1024,
       c_wr_depth_rach => 16,
       c_wr_depth_rdch => 1024,
@@ -251,7 +251,7 @@ END COMPONENT;
       c_wr_depth_wdch => 1024,
       c_wr_depth_wrch => 16,
       c_wr_freq => 1,
-      c_wr_pntr_width => 9,
+      c_wr_pntr_width => 12,
       c_wr_pntr_width_axis => 10,
       c_wr_pntr_width_rach => 4,
       c_wr_pntr_width_rdch => 10,

target/lx9_dave/ipcore/WatchEvents.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Tue Jul 25 16:17:25 2017
+# Date: Mon Jun 22 18:58:13 2020
 #
 ##############################################################
 #
@@ -53,7 +53,7 @@ CSET clock_enable_type=Slave_Interface_Clock_Enable
 CSET clock_type_axi=Common_Clock
 CSET component_name=WatchEvents
 CSET data_count=false
-CSET data_count_width=10
+CSET data_count_width=13
 CSET disable_timing_violations=false
 CSET disable_timing_violations_axi=false
 CSET dout_reset_value=0
@@ -111,14 +111,14 @@ CSET fifo_implementation_wach=Common_Clock_Block_RAM
 CSET fifo_implementation_wdch=Common_Clock_Block_RAM
 CSET fifo_implementation_wrch=Common_Clock_Block_RAM
 CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=511
+CSET full_threshold_assert_value=4095
 CSET full_threshold_assert_value_axis=1023
 CSET full_threshold_assert_value_rach=1023
 CSET full_threshold_assert_value_rdch=1023
 CSET full_threshold_assert_value_wach=1023
 CSET full_threshold_assert_value_wdch=1023
 CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=510
+CSET full_threshold_negate_value=4094
 CSET id_width=4
 CSET inject_dbit_error=false
 CSET inject_dbit_error_axis=false
@@ -135,7 +135,7 @@ CSET inject_sbit_error_wach=false
 CSET inject_sbit_error_wdch=false
 CSET inject_sbit_error_wrch=false
 CSET input_data_width=72
-CSET input_depth=512
+CSET input_depth=4096
 CSET input_depth_axis=1024
 CSET input_depth_rach=16
 CSET input_depth_rdch=1024
@@ -144,7 +144,7 @@ CSET input_depth_wdch=1024
 CSET input_depth_wrch=16
 CSET interface_type=Native
 CSET output_data_width=72
-CSET output_depth=512
+CSET output_depth=4096
 CSET overflow_flag=false
 CSET overflow_flag_axi=false
 CSET overflow_sense=Active_High
@@ -168,7 +168,7 @@ CSET rach_type=FIFO
 CSET rdch_type=FIFO
 CSET read_clock_frequency=1
 CSET read_data_count=false
-CSET read_data_count_width=10
+CSET read_data_count_width=13
 CSET register_slice_mode_axis=Fully_Registered
 CSET register_slice_mode_rach=Fully_Registered
 CSET register_slice_mode_rdch=Fully_Registered
@@ -203,11 +203,11 @@ CSET write_acknowledge_flag=false
 CSET write_acknowledge_sense=Active_High
 CSET write_clock_frequency=1
 CSET write_data_count=false
-CSET write_data_count_width=10
+CSET write_data_count_width=13
 CSET wuser_width=1
 # END Parameters
 # BEGIN Extra information
 MISC pkg_timestamp=2012-11-19T12:39:56Z
 # END Extra information
 GENERATE
-# CRC: 3745e82a
+# CRC: ae9d5adb

target/lx9_dave/ipcore/WatchEvents.xise

@@ -30,6 +30,7 @@
 
   <properties>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
@@ -51,8 +52,8 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_DesignName" xil_pn:value="WatchEvents" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-07-25T17:19:37" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="374CFF28879B2146EB9160793669CDAF" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-06-22T19:59:58" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8443B0C0597663D41E40C7503B5D1699" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>

target/lx9_jason/ice6502/board.ucf

@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
 
 NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 #NET "VSS"     LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

target/lx9_jason/ice65c02/board.ucf

@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
 
 NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 #NET "VSS"     LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

target/lx9_jason/ice6809/board.ucf

@@ -6,6 +6,8 @@ PIN "inst_dcm1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE;
 
 NET "clock"      LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 #NET "VSS"       LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "NMI_n"      LOC="P95"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
 NET "IRQ_n"      LOC="P98"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3

target/lx9_jason/icez80/board.ucf

@@ -6,6 +6,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
 
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "Addr<11>" LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "Addr<12>" LOC="P95"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
 NET "Addr<13>" LOC="P98"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3

target/lx9_jason_flipped/ice6502/board.ucf

@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
 
 NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 #NET "VSS"     LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

target/lx9_jason_flipped/ice65c02/board.ucf

@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
 
 NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 #NET "VSS"     LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1

target/lx9_jason_flipped/ice6809/board.ucf

@@ -6,6 +6,8 @@ PIN "inst_dcm1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE;
 
 NET "clock"      LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 #NET "VSS"       LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "NMI_n"      LOC="P15"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
 NET "IRQ_n"      LOC="P17"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3

target/lx9_jason_flipped/icez80/board.ucf

@@ -6,6 +6,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
 
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "Addr<11>" LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "Addr<12>" LOC="P15"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
 NET "Addr<13>" LOC="P17"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3