Updated release script to include .bin files

Change-Id: Ic09c51f721a3c517a43282b053dbdf9a55fba902
Update build scripts to generate .bin files for programming using OpenOCD on a Pi
2025-07-25 02:24:10 +00:00 · 2021-09-21 13:20:32 +01:00 · 2021-09-21 10:57:25 +01:00 · 2021-06-30 19:45:39 +01:00 · 2021-06-30 19:45:39 +01:00 · 2021-04-10 16:15:39 +01:00
36 changed files with 3968 additions and 3714 deletions
--- a/firmware/AtomBusMon.c
+++ b/firmware/AtomBusMon.c
@@ -14,7 +14,7 @@
 * VERSION and NAME are used in the start-up message
 ********************************************************/

-#define VERSION "0.984"
+#define VERSION "0.994"

 #if defined(CPU_Z80)
  #define NAME "ICE-Z80"
@@ -87,7 +87,9 @@ char *cmdStrings[] = {
  "watcho",
 #endif
  "clear",
-  "trigger"
+  "trigger",
+  "timermode",
+  "timeout"
 };

 // Must be kept in step with cmdStrings (just above)
@@ -140,7 +142,9 @@ void (*cmdFuncs[])(char *params) = {
  doCmdWatchWrIO,
 #endif
  doCmdClear,
-  doCmdTrigger
+  doCmdTrigger,
+  doCmdTimerMode,
+  doCmdTimeout
 };

 #if defined(EXTENDED_HELP)
@@ -162,6 +166,7 @@ static const char ARGS13[] PROGMEM = "<start> <end> <to>";
 static const char ARGS14[] PROGMEM = "[ <value> ]";
 static const char ARGS15[] PROGMEM = "[ <command> ]";
 static const char ARGS16[] PROGMEM = "<op1> [ <op2> [ <op3> ] ]";
+static const char ARGS17[] PROGMEM = "[ <source> [ <prescale> [ <reset address> ] ] ]";

 static const char * const argsStrings[] PROGMEM = {
  ARGS00,
@@ -180,7 +185,8 @@ static const char * const argsStrings[] PROGMEM = {
  ARGS13,
  ARGS14,
  ARGS15,
-  ARGS16
+  ARGS16,
+  ARGS17,
 };

 // Must be kept in step with cmdStrings (just above)
@@ -190,7 +196,7 @@ static const uint8_t helpMeta[] PROGMEM = {
 #endif
  17, 15, // help
   9,  8, // continue
-  24,  7, // next
+  24,  1, // next
  32,  6, // step
  27,  7, // regs
  12, 10, // dis
@@ -201,7 +207,7 @@ static const uint8_t helpMeta[] PROGMEM = {
   8, 13, // compare
  22,  1, // mem
  26,  2, // rd
-  41,  3, // wr
+  43,  3, // wr
 #if defined(CPU_Z80)
  20,  1, // io
  19,  2, // in
@@ -218,22 +224,24 @@ static const uint8_t helpMeta[] PROGMEM = {
  31,  7, // srec
  30, 14, // special
  28,  7, // reset
-  34,  6, // trace
+  36,  6, // trace
   1,  7, // blist
   6,  4, // breakx
-  40,  4, // watchx
+  42,  4, // watchx
   4,  4, // breakr
-  38,  4, // watchr
+  40,  4, // watchr
   5,  4, // breakw
-  39,  4, // watchw
+  41,  4, // watchw
 #if defined(CPU_Z80)
   2,  4, // breaki
-  36,  4, // watchi
+  38,  4, // watchi
   3,  4, // breako
-  37,  4, // watcho
+  39,  4, // watcho
 #endif
   7,  0, // clear
-  35,  5, // trigger
+  37,  5, // trigger
+  35, 17, // timermode
+  34, 14, // timeout
   0,  0
 };

@@ -248,42 +256,42 @@ static const uint8_t helpMeta[] PROGMEM = {
 #define CTRL_DDR          DDRB
 #define CTRL_DIN          PINB

-// A 0->1 transition on bit 5 actually sends a command
-#define CMD_EDGE          0x20
+// A 0->1 transition on bit 6 actually sends a command
+#define CMD_EDGE          0x40

-// Commands are placed on bits 4..0
-#define CMD_MASK          0x1F
-
-// Bits 7..6 are the special function output bits
-// On the 6502, these are used to mask IRQ and NMI
-#define SPECIAL_0            6
-#define SPECIAL_1            7
-#define SPECIAL_MASK      ((1<<SPECIAL_0) | (1<<SPECIAL_1))
+// Commands are placed on bits 5..0
+#define CMD_MASK          0x3F

 // Hardware Commands:
 //
-// 0000x Enable/Disable single strpping
-// 0001x Enable/Disable breakpoints / watches
-// 0010x Load breakpoint / watch register
-// 0011x Reset CPU
-// 01000 Singe Step CPU
-// 01001 Read FIFO
-// 01010 Reset FIFO
-// 01011 Unused
-// 0110x Load address/data register
-// 0111x Unused
-// 10000 Read Memory
-// 10001 Read Memory and Auto Inc Address
-// 10010 Write Memory
-// 10011 Write Memory and Auto Inc Address
-// 10100 Read IO
-// 10101 Read IO and Auto Inc Address
-// 10110 Write IO
-// 10111 Write IO and Auto Inc Address
-// 11000 Exec Go
-// 11xx1 Unused
-// 11x1x Unused
-// 111xx Unused
+// 00000x Enable/Disable single strpping
+// 00001x Enable/Disable breakpoints / watches
+// 00010x Load breakpoint / watch register
+// 00011x Reset CPU
+// 001000 Singe Step CPU
+// 001001 Read FIFO
+// 001010 Reset FIFO
+// 001011 Unused
+// 00110x Load address/data register
+// 00111x Unused
+// 010000 Read Memory
+// 010001 Read Memory and Auto Inc Address
+// 010010 Write Memory
+// 010011 Write Memory and Auto Inc Address
+// 010100 Read IO
+// 010101 Read IO and Auto Inc Address
+// 010110 Write IO
+// 010111 Write IO and Auto Inc Address
+// 011000 Exec Go
+// 011xx1 Unused
+// 011x1x Unused
+// 0111xx Unused
+// 100xxx Special
+// 1010xx Timer Mode
+//     00 - count cpu cycles where clken = 1 and CountCycle = 1
+//     01 - count cpu cycles where clken = 1 (ignoring CountCycle)
+//     10 - free running timer, using busmon_clk as the source
+//     11 - free running timer, using trig0 as the source

 #define CMD_SINGLE_ENABLE 0x00
 #define CMD_BRKPT_ENABLE  0x02
@@ -302,6 +310,8 @@ static const uint8_t helpMeta[] PROGMEM = {
 #define CMD_WR_IO         0x16
 #define CMD_WR_IO_INC     0x17
 #define CMD_EXEC_GO       0x18
+#define CMD_SPECIAL       0x20
+#define CMD_TIMER_MODE    0x28

 /********************************************************
 * AVR Status Register Definitions
@@ -446,6 +456,10 @@ modes_t modes[MAXBKPTS];
 #define WATCH_EXEC      9
 #define TRANSIENT      10

+// Mask to test if the breakpoint/watchpoint is a Z80 IO
+#if defined(CPU_Z80)
+#define MASK_IO ((1 << BRKPT_IO_READ) |  (1 << WATCH_IO_READ) |  (1 << BRKPT_IO_WRITE) |  (1 << WATCH_IO_WRITE))
+#endif

 static const char MODE0[] PROGMEM = "Mem Rd Brkpt";
 static const char MODE1[] PROGMEM = "Mem Rd Watch";
@@ -474,6 +488,21 @@ static const char *modeStrings[NUM_MODES] = {
  MODE10
 };

+// The number of different timer sources
+#define NUM_TIMERS   4
+
+static const char TIMER0[] PROGMEM = "Normal Cycles";
+static const char TIMER1[] PROGMEM = "All Cycles";
+static const char TIMER2[] PROGMEM = "Internal Timer";
+static const char TIMER3[] PROGMEM = "External Timer";
+
+static const char *timerStrings[NUM_TIMERS] = {
+  TIMER0,
+  TIMER1,
+  TIMER2,
+  TIMER3
+};
+
 // For convenience, several masks are defined that group similar types of breakpoint/watch

 // Mask for all breakpoint types
@@ -587,6 +616,9 @@ static const char * triggerStrings[NUM_TRIGGERS] = {
 // The current memory address (e.g. used when disassembling)
 addr_t memAddr = 0;

+// The current memory timeout value, in microseconds.
+uint16_t memTimeout = 0x1000;
+
 // The address of the next instruction
 addr_t nextAddr = 0;

@@ -605,6 +637,15 @@ uint8_t cmd_id = 0xff;
 #define MASK_CLOCK_ERROR   1
 #define MASK_TIMEOUT_ERROR 2

+// Current special setting
+uint8_t special = 0x00;
+
+// Current timer mode setting
+uint8_t timer_mode = 0x00;
+uint8_t timer_prescale = 0x01;
+addr_t  timer_resetaddr = 0xffff;
+unsigned long timer_offset = 0;
+
 /********************************************************
 * User Command Processor
 ********************************************************/
@@ -746,9 +787,13 @@ uint8_t checkargs(char *params) {
 ********************************************************/

 // Send a single hardware command
+//
 void hwCmd(cmd_t cmd, cmd_t param) {
  uint8_t status = STATUS_DIN;
-  uint16_t timeout = 10000;
+  // An interation of the inner loop with a 32-bit loop variable
+  // is 9 instructions. So use F_CPU to scale to the timeout
+  // value is approx microseconds.
+  uint32_t timeout =  ((uint32_t) memTimeout) * ((F_CPU / 1000000) / 9);
  cmd |= param;
  CTRL_PORT &= ~CMD_MASK;
  CTRL_PORT ^= cmd | CMD_EDGE;
@@ -957,8 +1002,9 @@ void genericRead(char *params, data_t (*readFunc)()) {
 * Logging Helpers
 ********************************************************/

-void logCycleCount(int offsetLow, int offsetHigh) {
-  unsigned long count = (((unsigned long) hwRead8(offsetHigh)) << 16) | hwRead16(offsetLow);
+void logCycleCount(int offsetLow, int offsetHigh, uint8_t clear) {
+  unsigned long original_count = (((unsigned long) hwRead8(offsetHigh)) << 16) | hwRead16(offsetLow);
+  unsigned long count = ((original_count - timer_offset) & 0xFFFFFF) / timer_prescale;
  char buffer[16];
  uint8_t i;
  // count is 24 bits so a maximum of 16777215
@@ -976,6 +1022,11 @@ void logCycleCount(int offsetLow, int offsetHigh) {
    }
  }
  logs(" : ");
+  // Deal with clearing the counter
+  if (clear) {
+    logs("\n00.000000 : ");
+    timer_offset = original_count;
+  }
 }

 void logMode(modes_t mode) {
@@ -1012,6 +1063,8 @@ uint8_t logDetails() {

  // Process the dropped counter
  uint8_t dropped = mode >> 4;
+  // Whether to clear timer
+  uint8_t clear = i_addr == timer_resetaddr;
  if (dropped) {
    logstr("          : ");
    if (dropped == 15) {
@@ -1030,7 +1083,7 @@ uint8_t logDetails() {

  // Update the serial console
  if (mode & W_MASK) {
-    logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
+    logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH, clear);
  }
  logMode(mode);
  logstr(" hit at ");
@@ -1046,7 +1099,7 @@ uint8_t logDetails() {
  logc('\n');
  if (mode & B_RDWR_MASK) {
    // It's only safe to do this for brkpts, as it makes memory accesses
-    logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
+    logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH, clear);
    disMem(i_addr);
  }
  return watch;
@@ -1058,7 +1111,7 @@ void logAddr() {
  Delay_us(100);
  memAddr = hwRead16(OFFSET_IAL);
  // Update the serial console
-  logCycleCount(OFFSET_CNTL, OFFSET_CNTH);
+  logCycleCount(OFFSET_CNTL, OFFSET_CNTH, memAddr == timer_resetaddr);
  nextAddr = disMem(memAddr);
  return;
 }
@@ -1189,7 +1242,11 @@ void clearBreakpoint(bknum_t n) {
 void genericBreakpoint(char *params, unsigned int mode) {
  bknum_t i;
  addr_t addr;
+#if defined(CPU_Z80)
+  addr_t mask = (mode & MASK_IO) ? 0xFF : 0xFFFF;
+#else
  addr_t mask = 0xFFFF;
+#endif
  trigger_t trigger = TRIGGER_UNDEFINED;
  params = parsehex4required(params, &addr);
  if (checkargs(params)) {
@@ -1366,7 +1423,7 @@ void helpForCommand(uint8_t i) {
  logstr("   ");
  logs(cmdStrings[i]);
  tmp = strlen(cmdStrings[i]);
-  while (tmp++ < 9) {
+  while (tmp++ < 10) {
    logc(' ');
  }
  while ((tmp = pgm_read_byte(ip++))) {
@@ -1985,13 +2042,60 @@ void logSpecial(char *function, uint8_t value) {
 }

 void doCmdSpecial(char *params) {
-  uint8_t special = 0xff;
-  parsehex2(params, &special);
-  if (special <= 3) {
-    CTRL_PORT = (CTRL_PORT & ~SPECIAL_MASK) | (special << SPECIAL_0);
+  uint8_t tmp = 0xff;
+  parsehex2(params, &tmp);
+#if defined(CPU_6809)
+  if (tmp <= 7) {
+#else
+  if (tmp <= 3) {
+#endif
+    special = tmp;
+    hwCmd(CMD_SPECIAL, special);
  }
-  logSpecial("NMI", CTRL_PORT & (1 << SPECIAL_1));
-  logSpecial("IRQ", CTRL_PORT & (1 << SPECIAL_0));
+#if defined(CPU_6809)
+  logSpecial("FIRQ", special & 4);
+#endif
+  logSpecial("NMI", special & 2);
+  logSpecial("IRQ", special & 1);
+}
+
+void doCmdTimerMode(char *params) {
+  uint8_t      mode = 0xff;
+  uint8_t  prescale = 0xff;
+  addr_t       addr = 0xffff;
+
+  params = parsehex2(params, &mode);
+  params = parsehex2(params, &prescale);
+  params = parsehex4(params, &addr);
+  if (mode <= NUM_TIMERS) {
+    timer_mode = mode;
+    hwCmd(CMD_TIMER_MODE, timer_mode);
+  }
+  if (prescale < 0xff) {
+    timer_prescale = prescale;
+  }
+  if (addr < 0xffff) {
+    timer_resetaddr = addr;
+  }
+  logstr("mode: ");
+  logpgmstr(timerStrings[timer_mode]);
+  logstr("; prescale=");
+  loghex4(timer_prescale);
+  logstr("; reset address=");
+  loghex4(timer_resetaddr);
+  logstr("\n");
+}
+
+void doCmdTimeout(char *params) {
+  parsehex4(params, &memTimeout);
+  // Small timeouts values cause bogus timeout errors, so enforce a minimum
+  // of 16us, which is less much than one character time at 115,200 (86us)
+  if (memTimeout < 0x10) {
+     memTimeout = 0x10;
+  }
+  logstr("timeout=");
+  loghex4(memTimeout);
+  logstr(" microseconds (hex)\n");
 }

 void doCmdTrace(char *params) {
@@ -2113,8 +2217,13 @@ void doCmdNext(char *params) {
    logTooManyBreakpoints();
    return;
  }
+  addr_t addr = 0xFFFF;
+  params = parsehex4(params, &addr);
+  if (addr == 0xFFFF) {
+     addr = nextAddr;
+  }
  numbkpts++;
-  setBreakpoint(numbkpts - 1, nextAddr, 0xffff, (1 << BRKPT_EXEC) | (1 << TRANSIENT), TRIGGER_ALWAYS);
+  setBreakpoint(numbkpts - 1, addr, 0xffff, (1 << BRKPT_EXEC) | (1 << TRANSIENT), TRIGGER_ALWAYS);
  doCmdContinue(params);
 }

--- a/firmware/AtomBusMon.h
+++ b/firmware/AtomBusMon.h
@@ -77,6 +77,8 @@ void doCmdTest(char *params);
 void doCmdSave(char *params);
 void doCmdSRec(char *params);
 void doCmdSpecial(char *params);
+void doCmdTimerMode(char *params);
+void doCmdTimeout(char *params);
 void doCmdTrace(char *params);
 void doCmdTrigger(char *params);
 void doCmdWatchI(char *params);
--- a/release.sh
+++ b/release.sh
@@ -16,8 +16,9 @@ pushd target
 make clean
 make

-cp --parents */*/*.bit ../${DIR}
-cp --parents */*/*.mcs ../${DIR}
+cp --parents */*/ice*.bit ../${DIR}
+cp --parents */*/ice*.bin ../${DIR}
+cp --parents */*/ice*.mcs ../${DIR}

 popd

@@ -27,5 +28,3 @@ popd

 echo "Built release in: "${DIR}
 unzip -l releases/${NAME}.zip
-
- 
--- a/src/AVR8/Memory/XPM_T65.vhd
+++ b/src/AVR8/Memory/XPM_T65.vhd
--- a/src/AlanD/R65Cx2.vhd
+++ b/src/AlanD/R65Cx2.vhd
@@ -15,7 +15,6 @@ use ieee.numeric_std.ALL;

 entity R65C02 is
    port (
-		
        reset    : in std_logic;
        clk      : in std_logic;
        enable   : in std_logic;
@@ -41,16 +40,14 @@ end R65C02;
 -- Rts         (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
 -- Rti         (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
 -- Jsr         (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs     (-) => fetch, cycle2, .., cycleJump
-- Jmp (ind)   (-) => fetch, cycle2, .., cycleJump
-- Brk / irq   (6) => fetch, cycle2, stack2, stack3, stack4
+-- Jmp abs     (3) => fetch, cycle2, cycleJump
+-- Jmp (ind)   (6) => fetch, cycle2, cycle3, cycleRead, cycleRead2, cycleJump
+-- Jmp (ind,x) (6) => fetch, cycle2, cycle3, cycleRead, cycleRead2, cycleJump
+-- Brk         (7) => fetch, cycle2, stack2, stack3, stack4, cycleRead2, cycleJump
 -- -----------------------------------------------------------------------

 architecture Behavioral of R65C02 is

--	signal counter : unsigned(27 downto 0);
--	signal mask_irq : std_logic;
--	signal mask_enable : std_logic;
 -- Statemachine

    type cpuCycles is (
@@ -74,6 +71,7 @@ architecture Behavioral of R65C02 is
        cycleJump,        -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
        cycleEnd
        );
+
    signal theCpuCycle     : cpuCycles;
    signal nextCpuCycle    : cpuCycles;
    signal updateRegisters : boolean;
@@ -84,6 +82,7 @@ architecture Behavioral of R65C02 is
    signal soReg           : std_logic; -- SO pin edge detection

 -- Opcode decoding
+
    constant opcUpdateA    : integer := 0;
    constant opcUpdateX    : integer := 1;
    constant opcUpdateY    : integer := 2;
@@ -112,7 +111,6 @@ architecture Behavioral of R65C02 is
    constant opcRti        : integer := 24;
    constant opcIRQ        : integer := 25;

-	
    constant opcInA        : integer := 26;
    constant opcInBrk      : integer := 27;
    constant opcInX        : integer := 28;
@@ -129,7 +127,7 @@ architecture Behavioral of R65C02 is
    constant aluMode2From  : integer := 38;
    --
    constant aluMode2To    : integer := 40;
-	--
+
    constant opcInCmp      : integer := 41;
    constant opcInCpx      : integer := 42;
    constant opcInCpy      : integer := 43;
@@ -200,8 +198,6 @@ architecture Behavioral of R65C02 is
    constant rts       : addrDef := "0000101000100100";
    constant rti       : addrDef := "0000111000100010";
    constant brk       : addrDef := "1000111000000001";
--	constant irq       : addrDef := "0000111000000001";
--	constant        : unsigned(0 to 0) := "0";
    constant xxxxxxxx  : addrDef := "----------0---00";

    -- A = accu
@@ -259,9 +255,7 @@ architecture Behavioral of R65C02 is
    constant aluModeOra : aluMode2 := "101";
    constant aluModeEor : aluMode2 := "110";
    constant aluModeNoF : aluMode2 := "111";
-	--aluModeBRK
-	--constant aluBrk  : aluMode := aluModeBRK & aluModePss & "---";
-	--constant aluFix  : aluMode := aluModeInp & aluModeNoF & "---";
+
    constant aluInp  : aluMode := aluModeInp & aluModePss & "---";
    constant aluP    : aluMode := aluModeP   & aluModePss & "---";
    constant aluInc  : aluMode := aluModeInc & aluModePss & "---";
@@ -285,14 +279,15 @@ architecture Behavioral of R65C02 is

    constant aluXXX  : aluMode := (others => '-');

-
    -- Stack operations. Push/Pop/None
    constant stackInc : unsigned(0 to 0) := "0";
    constant stackDec : unsigned(0 to 0) := "1";
    constant stackXXX : unsigned(0 to 0) := "-";

    subtype decodedBitsDef is unsigned(0 to 43);
+
    type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
+
    constant opcodeInfoTable : opcodeInfoTableDef := (
        -- +------- Update register A
        -- |+------ Update register X
@@ -571,7 +566,6 @@ architecture Behavioral of R65C02 is
        );
    signal opcInfo        : decodedBitsDef;
    signal nextOpcInfo    : decodedBitsDef; -- Next opcode (decoded)
-	signal nextOpcInfoReg : decodedBitsDef;	-- Next opcode (decoded) pipelined
    signal theOpcode      : unsigned(7 downto 0);
    signal nextOpcode     : unsigned(7 downto 0);

@@ -595,6 +589,7 @@ architecture Behavioral of R65C02 is
        nextAddrStack,
        nextAddrRelative
        );
+
    signal nextAddr       : nextAddrDef;
    signal myAddr         : unsigned(15 downto 0);
    signal myAddrIncr     : unsigned(15 downto 0);
@@ -632,11 +627,12 @@ architecture Behavioral of R65C02 is
    signal aluZ           : std_logic;
    signal aluV           : std_logic;
    signal aluN           : std_logic;
+
 -- Indexing
    signal indexOut       : unsigned(8 downto 0);

-	signal realbrk : std_logic;
 begin
+
    processAluInput: process(clk, opcInfo, A, X, Y, T, S)
        variable temp : unsigned(7 downto 0);
    begin
@@ -704,7 +700,7 @@ processCmpInput: process(clk, opcInfo, A, X, Y)
 --hardware interrupts IRQ & NMI will push the B flag as being 0.


-processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C)
+    processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C, R)
        variable lowBits  : unsigned(5 downto 0);
        variable nineBits : unsigned(8 downto 0);
        variable rmwBits  : unsigned(8 downto 0);
@@ -720,7 +716,7 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
        rmwBits  := (others => '-');
        tsxBits  := (others => '-');
        R <= '1';
-	
+        B <= '0';

        -- Shift unit
        case opcInfo(aluMode1From to aluMode1To) is
@@ -754,10 +750,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
            when others     => ninebits := rmwBits;
        end case;

-		
        varV := aluInput(6); -- Default for BIT / PLP / RTI

-				
        if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
            varZ := rmwBits(1);
        elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then
@@ -786,7 +780,6 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
            --    v Set if signed overflow; cleared if valid signed result.
            --    z Set if result is zero; else cleared.
            --    c Set if unsigned overflow; cleared if valid unsigned result
-		
            when aluModeAdc =>
                -- decimal mode low bits correction, is done after setting Z flag.
                if D = '1' then
@@ -797,7 +790,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
                        end if;
                    end if;
                end if;
-		when others =>			null;
+            when others =>
+                null;
        end case;

        case opcInfo(aluMode2From to aluMode2To) is
@@ -823,7 +817,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
                        ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
                    end if;
                end if;
-		when others =>			null;
+            when others =>
+                null;
        end case;

        -- fix n and z flag for 65c02 adc sbc instructions in decimal mode
@@ -846,7 +841,8 @@ processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V,
                    end if;
                    varN := ninebits(7);
                end if;
-		when others =>			null;
+            when others =>
+                null;
        end case;

 -- DMB Remove Pipelining
@@ -911,14 +907,6 @@ calcNextOpcode: process(clk, di, reset, processIrq)

    nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));

-- DMB Remove Pipelining        		
--	process(clk)
--	begin
--		if rising_edge(clk) then
-			nextOpcInfoReg <= nextOpcInfo;
--		end if;
--	end process;
-
    -- Read bits and flags from opcodeInfoTable and store in opcInfo.
    -- This info is used to control the execution of the opcode.
    calcOpcInfo: process(clk)
@@ -979,13 +967,23 @@ calcTheOpcode:	process(clk)

    -- Determine the next cpu cycle. After the last cycle we always
    -- go to opcodeFetch to get the next opcode.
-calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z)
+    calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut, T, N, V, C, Z)
    begin
        nextCpuCycle <= opcodeFetch;

        case theCpuCycle is
-		when opcodeFetch =>		nextCpuCycle <= cycle2;
-		when cycle2 =>							if opcInfo(opcBranch) = '1' then
+
+            when opcodeFetch =>
+                -- DMB: Implement single cycle NOPs (columns 3,7,B,F) by
+                -- looking ahead at opcode (bypassing the normal decoding)
+                if nextOpcode(1 downto 0) = "11" then
+                    nextCpuCycle <= opcodeFetch;
+                else
+                    nextCpuCycle <= cycle2;
+                end   if;
+
+            when cycle2 =>
+                if opcInfo(opcBranch) = '1' then
                    if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
                        or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
                        or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
@@ -1026,7 +1024,9 @@ calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C,
                elsif opcInfo(opcJump) = '1' then
                    nextCpuCycle <= cycleJump;
                end if;
-		when cycle3 =>					nextCpuCycle <= cycleRead;
+
+            when cycle3 =>
+                nextCpuCycle <= cycleRead;
                if opcInfo(opcWrite) = '1' then
                    if (opcInfo(indexX) = '1')  or (opcInfo(indexY) = '1') then
                        nextCpuCycle <= cyclePreWrite;
@@ -1041,18 +1041,24 @@ calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C,
                        nextCpuCycle <= cycleRead2;
                    end if;
                end if;
-		when cyclePreIndirect =>			nextCpuCycle <= cycleIndirect;
-		when cycleIndirect =>			nextCpuCycle <= cycle3;
-		when cycleBranchTaken =>		if indexOut(8) /= T(7) then
+
+            when cyclePreIndirect =>
+                nextCpuCycle <= cycleIndirect;
+
+            when cycleIndirect =>
+                nextCpuCycle <= cycle3;
+
+            when cycleBranchTaken =>
+                if indexOut(8) /= T(7) then
                    nextCpuCycle <= cycleBranchPage;
                end if;
-		when cyclePreRead =>				if opcInfo(opcZeroPage) = '1' then
+            when cyclePreRead =>
+                if opcInfo(opcZeroPage) = '1' then
                    nextCpuCycle <= cycleRead2;
                end if;
+
            when cycleRead =>
-												if opcInfo(opcJump) = '1' then
-													nextCpuCycle <= cycleJump;
-												elsif indexOut(8) = '1' then
+                if opcInfo(opcJump) = '1' or indexOut(8) = '1' then
                    nextCpuCycle <= cycleRead2;
                elsif opcInfo(opcRmw) = '1' then
                    nextCpuCycle <= cycleRmw;
@@ -1060,33 +1066,53 @@ calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C,
                        nextCpuCycle <= cycleRead2;
                    end if;
                end if;
-		when cycleRead2 => 			if opcInfo(opcRmw) = '1' then
+
+            when cycleRead2 =>
+                if opcInfo(opcJump) = '1' then
+                    nextCpuCycle <= cycleJump;
+                elsif opcInfo(opcRmw) = '1' then
                    nextCpuCycle <= cycleRmw;
                end if;
-		when cycleRmw =>				nextCpuCycle <= cycleWrite;
-		when cyclePreWrite =>		nextCpuCycle <= cycleWrite;
-		when cycleStack1 =>			nextCpuCycle <= cycleRead;
+
+            when cycleRmw =>
+                nextCpuCycle <= cycleWrite;
+
+            when cyclePreWrite =>
+                nextCpuCycle <= cycleWrite;
+
+            when cycleStack1 =>
+                nextCpuCycle <= cycleRead;
                if opcInfo(opcStackAddr) = '1' then
                    nextCpuCycle <= cycleStack2;
                end if;
-		when cycleStack2 =>			nextCpuCycle <= cycleStack3;
+
+            when cycleStack2 =>
+                nextCpuCycle <= cycleStack3;
                if opcInfo(opcRti) = '1' then
                    nextCpuCycle <= cycleRead;
                end if;
                if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then
                    nextCpuCycle <= cycleJump;
                end if;
-		when cycleStack3 =>			nextCpuCycle <= cycleRead;
+
+            when cycleStack3 =>
+                nextCpuCycle <= cycleRead;
                if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then
                    nextCpuCycle <= cycleJump;
                elsif opcInfo(opcStackAddr) = '1' then
                    nextCpuCycle <= cycleStack4;
                end if;
-		when cycleStack4 =>			nextCpuCycle <= cycleRead;
-		when cycleJump =>				if opcInfo(opcIncrAfter) = '1' then
+
+            when cycleStack4 =>
+                nextCpuCycle <= cycleRead2;
+
+            when cycleJump =>
+                if opcInfo(opcIncrAfter) = '1' then
                    nextCpuCycle <= cycleEnd;
                end if;
-		when others =>					null;
+
+            when others =>
+                null;
        end case;
    end process;

@@ -1098,7 +1124,8 @@ calcT: process(clk)
        if rising_edge(clk) then
            if enable = '1' then
                case theCpuCycle is
-				when cycle2 =>														T <= di;
+                    when cycle2 =>
+                        T <= di;
                    when cycleStack1 | cycleStack2 =>
                        if opcInfo(opcStackUp) = '1' then
                            if theOpcode = x"28" or theOpcode = x"40" then   -- plp or rti pulling the flags off the stack
@@ -1107,8 +1134,10 @@ calcT: process(clk)
                                T <= di;
                            end if;
                        end if;
-				when cycleIndirect | cycleRead | cycleRead2 =>			T <= di;
-				when others =>														null;					
+                    when cycleIndirect | cycleRead | cycleRead2 =>
+                        T <= di;
+                    when others =>
+                        null;
                end case;
            end if;
        end if;
@@ -1199,6 +1228,7 @@ calcT: process(clk)
            end if;
        end if;
    end process;
+
 -- -----------------------------------------------------------------------
 -- D flag
 -- -----------------------------------------------------------------------
@@ -1266,16 +1296,22 @@ calcT: process(clk)
                            updateFlag := true;
                        end if;

-				when cycleStack2 =>					updateFlag := true;
-				when cycleStack3 =>					updateFlag := true;			
-				when cycleStack4 =>					updateFlag := true;
-				when cycleRead =>			if opcInfo(opcRti) = '1' then							
+                    when cycleStack2 =>
+                        updateFlag := true;
+                    when cycleStack3 =>
+                        updateFlag := true;
+                    when cycleStack4 =>
+                        updateFlag := true;
+                    when cycleRead =>
+                        if opcInfo(opcRti) = '1' then
                            updateFlag := true;
                        end if;
-				when cycleWrite =>		if opcInfo(opcStackData) = '1' then
+                    when cycleWrite =>
+                        if opcInfo(opcStackData) = '1' then
                            updateFlag := true;
                        end if;
-				when others =>				null;					
+                    when others =>
+                        null;
                end case;

                if updateFlag then
@@ -1302,22 +1338,25 @@ calcDo: process(clk)
            if enable = '1' then
                doReg <= aluRmwOut;
                case nextCpuCycle is
-				when cycleStack2 =>					if opcInfo(opcIRQ) = '1' and irqActive = '0' then
+                    when cycleStack2 =>
+                        if opcInfo(opcIRQ) = '1' and irqActive = '0' then
                            doReg <= myAddrIncr(15 downto 8);
                        else
                            doReg <= PC(15 downto 8);
                        end if;
-				when cycleStack3 =>				doReg <= PC(7 downto 0);
-				when cycleRmw =>					doReg <= di; -- Read-modify-write write old value first.
-				when others => null;
+                    when cycleStack3 =>
+                        doReg <= PC(7 downto 0);
+                    when cycleRmw =>
+                        doReg <= di; -- Read-modify-write write old value first.
+                    when others =>
+                        null;
                end case;
            end if;
        end if;
    end process;
+
    do <= doReg;

-
-
 -- -----------------------------------------------------------------------
 -- Write enable
 -- -----------------------------------------------------------------------
@@ -1335,9 +1374,12 @@ calcWe: process(clk)
                        if opcInfo(opcStackUp) = '0' then
                            theWe <= '0';
                        end if;
-				when cycleRmw =>				theWe <= '0';	
-				when cycleWrite =>			theWe <= '0';	
-				when others =>					null;
+                    when cycleRmw =>
+                        theWe <= '0';
+                    when cycleWrite =>
+                        theWe <= '0';
+                    when others =>
+                        null;
                end case;
            end if;
        end if;
@@ -1353,18 +1395,22 @@ calcPC: process(clk)
        if rising_edge(clk) then
            if enable = '1' then
                case theCpuCycle is
-				when opcodeFetch =>					PC <= myAddr;
-				when cycle2 =>					if irqActive = '0' then
+                    when opcodeFetch =>
+                        PC <= myAddr;
+                    when cycle2 =>
+                        if irqActive = '0' then
                            if opcInfo(opcSecondByte) = '1' then
                                PC <= myAddrIncr;
                            else
                                PC <= myAddr;
                            end if;
                        end if;
-				when cycle3 =>					if opcInfo(opcAbsolute) = '1' then
+                    when cycle3 =>
+                        if opcInfo(opcAbsolute) = '1' then
                            PC <= myAddrIncr;
                        end if;
-				when others =>					null;
+                    when others =>
+                        null;
                end case;
            end if;
        end if;
@@ -1378,7 +1424,8 @@ calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
    begin
        nextAddr <= nextAddrIncr;
        case theCpuCycle is
-		when cycle2 =>					if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
+            when cycle2 =>
+                if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
                    nextAddr <= nextAddrStack;
                elsif opcInfo(opcAbsolute) = '1' then
                    nextAddr <= nextAddrIncr;
@@ -1391,67 +1438,72 @@ calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
                else
                    nextAddr <= nextAddrHold;
                end if;
-		when cycle3 =>					if (opcInfo(opcIndirect) = '1')	and (opcInfo(indexX) = '1') then
+            when cycle3 =>
+                if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
                    nextAddr <= nextAddrAbs;
                else
                    nextAddr <= nextAddrAbsIndexed;
                end if;
-		when cyclePreIndirect => 			nextAddr <= nextAddrZPIndexed;
-		when cycleIndirect =>				nextAddr <= nextAddrIncrL;
-		when cycleBranchTaken =>			nextAddr <= nextAddrRelative;
-		when cycleBranchPage => 	if T(7) = '0' then
+            when cyclePreIndirect =>
+                nextAddr <= nextAddrZPIndexed;
+            when cycleIndirect =>
+                nextAddr <= nextAddrIncrL;
+            when cycleBranchTaken =>
+                nextAddr <= nextAddrRelative;
+            when cycleBranchPage =>
+                if T(7) = '0' then
                    nextAddr <= nextAddrIncrH;
                else
                    nextAddr <= nextAddrDecrH;
                end if;
-		when cyclePreRead =>					nextAddr <= nextAddrZPIndexed;
-		when cycleRead =>						nextAddr <= nextAddrPc;
-											if opcInfo(opcJump) = '1' then
-													-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
-													-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
-													nextAddr <= nextAddrIncr;
-													--nextAddr <= nextAddrIncrL;	
-											elsif indexOut(8) = '1' then
+            when cyclePreRead =>
+                nextAddr <= nextAddrZPIndexed;
+            when cycleRead =>
+                nextAddr <= nextAddrPc;
+                if indexOut(8) = '1' then
                    nextAddr <= nextAddrIncrH;
+                elsif opcInfo(opcRmw) = '1' or opcInfo(opcJump) = '1' then
+                    nextAddr <= nextAddrHold;
+                end if;
+            when cycleRead2 =>
+                nextAddr <= nextAddrPc;
+                if opcInfo(opcJump) = '1' then
+                    nextAddr <= nextAddrIncr;
                elsif opcInfo(opcRmw) = '1' then
                    nextAddr <= nextAddrHold;
                end if;
-		when cycleRead2 =>			nextAddr <= nextAddrPc;
-											if opcInfo(opcRmw) = '1' then
+            when cycleRmw =>
+                nextAddr <= nextAddrHold;
+            when cyclePreWrite =>
                nextAddr <= nextAddrHold;
-											end if;
-		when cycleRmw =>				nextAddr <= nextAddrHold;			
-		when cyclePreWrite =>		nextAddr <= nextAddrHold;			
                if opcInfo(opcZeroPage) = '1' then
                    nextAddr <= nextAddrZPIndexed;
                elsif indexOut(8) = '1' then
                    nextAddr <= nextAddrIncrH;
                end if;
-		when cycleWrite =>			nextAddr <= nextAddrPc;			
-		when cycleStack1 =>			nextAddr <= nextAddrStack;
-		when cycleStack2 =>			nextAddr <= nextAddrStack;
-		when cycleStack3 =>			nextAddr <= nextAddrStack;
+            when cycleWrite =>
+                nextAddr <= nextAddrPc;
+            when cycleStack1 =>
+                nextAddr <= nextAddrStack;
+            when cycleStack2 =>
+                nextAddr <= nextAddrStack;
+            when cycleStack3 =>
+                nextAddr <= nextAddrStack;
                if opcInfo(opcStackData) = '0' then
                    nextAddr <= nextAddrPc;
                end if;
-		when cycleStack4 =>			nextAddr <= nextAddrIrq;
-		when cycleJump =>				nextAddr <= nextAddrAbs; 
-										
-		
-		when others =>					null;
+            when cycleStack4 =>
+                nextAddr <= nextAddrIrq;
+            when cycleJump =>
+                nextAddr <= nextAddrAbs;
+            when others =>
+                null;
        end case;
-		
        if reset = '0' then
            nextAddr <= nextAddrReset;
        end if;
-		
    end process;

-	
-	
-	
-	
-	
    indexAlu: process(opcInfo, myAddr, T, X, Y)
    begin
        if opcInfo(indexX) = '1' then
@@ -1470,28 +1522,37 @@ calcAddr: process(clk)
        if rising_edge(clk) then
            if enable = '1' then
                case nextAddr is
-				when nextAddrIncr => myAddr <= myAddrIncr;
-				when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
-				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
-				when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
-				when nextAddrPc => myAddr <= PC;
-				when nextAddrIrq =>myAddr <= X"FFFE";
+                    when nextAddrIncr =>
+                        myAddr <= myAddrIncr;
+                    when nextAddrIncrL =>
+                        myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
+                    when nextAddrIncrH =>
+                        myAddr(15 downto 8) <= myAddrIncrH;
+                    when nextAddrDecrH =>
+                        myAddr(15 downto 8) <= myAddrDecrH;
+                    when nextAddrPc =>
+                        myAddr <= PC;
+                    when nextAddrIrq =>
+                        myAddr <= X"FFFE";
                        if nmiReg = '0' then
                            myAddr <= X"FFFA";
                        end if;
-				when nextAddrReset => myAddr <= X"FFFC";
-				when nextAddrAbs => myAddr <= di & T;
-				when nextAddrAbsIndexed =>--myAddr <= di & indexOut(7 downto 0);
-					if theOpcode = x"7C" then
-						myAddr <= (di & T) + (x"00"& X);
-					else
+                    when nextAddrReset =>
+                        myAddr <= X"FFFC";
+                    when nextAddrAbs =>
+                        myAddr <= di & T;
+                    when nextAddrAbsIndexed =>
                        myAddr <= di & indexOut(7 downto 0);
-					end if;
-				when nextAddrZeroPage => myAddr <= "00000000" & di;
-				when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
-				when nextAddrStack => myAddr <= "00000001" & S;
-				when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
-				when others => null;
+                    when nextAddrZeroPage =>
+                        myAddr <= "00000000" & di;
+                    when nextAddrZPIndexed =>
+                        myAddr <= "00000000" & indexOut(7 downto 0);
+                    when nextAddrStack =>
+                        myAddr <= "00000001" & S;
+                    when nextAddrRelative =>
+                        myAddr(7 downto 0) <= indexOut(7 downto 0);
+                    when others =>
+                        null;
                end case;
            end if;
        end if;
@@ -1506,11 +1567,12 @@ calcAddr: process(clk)
 --
 --  calcsync: process(clk)
 --  begin
--		
 --      if enable = '1' then
 --          case theCpuCycle is
--				when opcodeFetch =>			sync <= '1';
--				when others =>					sync <= '0';			
+--              when opcodeFetch =>
+--                  sync <= '1';
+--              when others =>
+--                  sync <= '0';
 --          end case;
 --      end if;
 --  end process;
@@ -1527,5 +1589,3 @@ calcAddr: process(clk)
            std_logic_vector(A);

 end architecture;
-
-
--- a/src/BusMonCore.vhd
+++ b/src/BusMonCore.vhd
@@ -72,7 +72,7 @@ entity BusMonCore is
        Done             : in std_logic;

        -- Special outputs (function is CPU specific)
-        Special          : out std_logic_vector(1 downto 0);
+        Special          : out std_logic_vector(2 downto 0);

        -- Single Step interface
        SS_Single        : out std_logic;
@@ -124,15 +124,18 @@ architecture behavioral of BusMonCore is
    signal cmd_ack         : std_logic;
    signal cmd_ack1        : std_logic;
    signal cmd_ack2        : std_logic;
-    signal cmd             : std_logic_vector(4 downto 0);
+    signal cmd             : std_logic_vector(5 downto 0);

    signal addr_sync       : std_logic_vector(15 downto 0);
    signal addr_inst       : std_logic_vector(15 downto 0);
    signal Addr1           : std_logic_vector(15 downto 0);
    signal Data1           : std_logic_vector(7 downto 0);

+    signal ext_clk         : std_logic;
+    signal timer0Count     : std_logic_vector(23 downto 0);
+    signal timer1Count     : std_logic_vector(23 downto 0);
    signal cycleCount      : std_logic_vector(23 downto 0);
-    signal cycleCount_inst : std_logic_vector(23 downto 0);
+    signal instrCount      : std_logic_vector(23 downto 0);

    signal single          : std_logic;
    signal reset           : std_logic;
@@ -181,6 +184,8 @@ architecture behavioral of BusMonCore is

    signal dropped_counter : std_logic_vector(3 downto 0);

+    signal timer_mode      : std_logic_vector(1 downto 0);
+
 begin

    inst_oho_dy1 : entity work.Oho_Dy1 port map (
@@ -224,9 +229,9 @@ begin
        portbout(2)          => cmd(2),
        portbout(3)          => cmd(3),
        portbout(4)          => cmd(4),
-        portbout(5)          => cmd_edge,
-        portbout(6)          => Special(0),
-        portbout(7)          => Special(1),
+        portbout(5)          => cmd(5),
+        portbout(6)          => cmd_edge,
+        portbout(7)          => open,

        -- Status Port
        portdin(0)           => '0',
@@ -289,7 +294,7 @@ begin
    -- DataWr1 is the data being written delayed by 1 cycle
    -- DataRd is the data being read, that is already one cycle late
    -- bw_state1(1) is 1 for writes, and 0 for reads
-    fifo_din <= cycleCount_inst & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
+    fifo_din <= instrCount & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;

    -- Implement a 4-bit saturating counter of the number of dropped events
    process (busmon_clk)
@@ -325,9 +330,9 @@ begin
    mux <= addr_inst(7 downto 0)            when muxsel = 0 else
           addr_inst(15 downto 8)           when muxsel = 1 else
           din_reg                          when muxsel = 2 else
-           cycleCount(23 downto 16)         when muxsel = 3 else
-           cycleCount(7 downto 0)           when muxsel = 4 else
-           cycleCount(15 downto 8)          when muxsel = 5 else
+           instrCount(23 downto 16)         when muxsel = 3 else
+           instrCount(7 downto 0)           when muxsel = 4 else
+           instrCount(15 downto 8)          when muxsel = 5 else

           fifo_dout(7 downto 0)            when muxsel = 6 else
           fifo_dout(15 downto 8)           when muxsel = 7 else
@@ -432,40 +437,55 @@ begin
    end process;

    -- CPU Control Commands
-    -- 0000x Enable/Disable single stepping
-    -- 0001x Enable/Disable breakpoints / watches
-    -- 0010x Load breakpoint / watch register
-    -- 0011x Reset CPU
-    -- 01000 Singe Step CPU
-    -- 01001 Read FIFO
-    -- 01010 Reset FIFO
-    -- 01011 Unused
-    -- 0110x Load address/data register
-    -- 0111x Unused
-    -- 10000 Read Memory
-    -- 10001 Read Memory and Auto Inc Address
-    -- 10010 Write Memory
-    -- 10011 Write Memory and Auto Inc Address
-    -- 10100 Read IO
-    -- 10101 Read IO and Auto Inc Address
-    -- 10110 Write IO
-    -- 10111 Write IO and Auto Inc Address
-    -- 11000 Execute 6502 instruction
-    -- 111xx Unused
-    -- 11x1x Unused
-    -- 11xx1 Unused
+    -- 00000x Enable/Disable single stepping
+    -- 00001x Enable/Disable breakpoints / watches
+    -- 00010x Load breakpoint / watch register
+    -- 00011x Reset CPU
+    -- 001000 Singe Step CPU
+    -- 001001 Read FIFO
+    -- 001010 Reset FIFO
+    -- 001011 Unused
+    -- 00110x Load address/data register
+    -- 00111x Unused
+    -- 010000 Read Memory
+    -- 010001 Read Memory and Auto Inc Address
+    -- 010010 Write Memory
+    -- 010011 Write Memory and Auto Inc Address
+    -- 010100 Read IO
+    -- 010101 Read IO and Auto Inc Address
+    -- 010110 Write IO
+    -- 010111 Write IO and Auto Inc Address
+    -- 011000 Execute 6502 instruction
+    -- 0111xx Unused
+    -- 011x1x Unused
+    -- 011xx1 Unused
+    -- 100xxx Special
+    -- 1010xx Timer Mode
+    --     00 - count cpu cycles where clken = 1 and CountCycle = 1
+    --     01 - count cpu cycles where clken = 1 (ignoring CountCycle)
+    --     10 - free running timer, using busmon_clk as the source
+    --     11 - free running timer, using trig0 as the source
+
+    -- Use trig0 to drive a free running counter for absolute timings
+    ext_clk <= trig(0);
+    timer1Process: process (ext_clk)
+    begin
+        if rising_edge(ext_clk) then
+            timer1Count <= timer1Count + 1;
+        end if;
+    end process;

    cpuProcess: process (busmon_clk)
    begin
        if rising_edge(busmon_clk) then
+            timer0Count <= timer0Count + 1;
            if busmon_clken = '1' then
-                -- Cycle counter, wraps every 16s at 1MHz
+                -- Cycle counter
                if (cpu_reset_n = '0') then
                    cycleCount <= (others => '0');
-                elsif (CountCycle = '1') then
+                elsif (CountCycle = '1' or timer_mode(0) = '1') then
                    cycleCount <= cycleCount + 1;
                end if;
-
                -- Command processing
                cmd_edge1 <= cmd_edge;
                cmd_edge2 <= cmd_edge1;
@@ -479,60 +499,68 @@ begin
                exec      <= '0';
                SS_Step   <= '0';
                if (cmd_edge2 /= cmd_edge1) then
-                    if (cmd(4 downto 1) = "0000") then
+                    if (cmd(5 downto 1) = "00000") then
                        single <= cmd(0);
                    end if;

-                    if (cmd(4 downto 1) = "0001") then
+                    if (cmd(5 downto 1) = "00001") then
                        brkpt_enable <= cmd(0);
                    end if;

-                    if (cmd(4 downto 1) = "0010") then
+                    if (cmd(5 downto 1) = "00010") then
                        brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
                    end if;

-                    if (cmd(4 downto 1) = "0110") then
+                    if (cmd(5 downto 1) = "00110") then
                        addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
                    end if;

-                    if (cmd(4 downto 1) = "0011") then
+                    if (cmd(5 downto 1) = "00011") then
                        reset <= cmd(0);
                    end if;

-                    if (cmd(4 downto 0) = "01001") then
+                    if (cmd(5 downto 0) = "01001") then
                        fifo_rd <= '1';
                    end if;

-                    if (cmd(4 downto 0) = "01010") then
+                    if (cmd(5 downto 0) = "01010") then
                        fifo_rst <= '1';
                    end if;

-                    if (cmd(4 downto 1) = "1000") then
+                    if (cmd(5 downto 1) = "01000") then
                        memory_rd <= '1';
                        auto_inc  <= cmd(0);
                    end if;

-                    if (cmd(4 downto 1) = "1001") then
+                    if (cmd(5 downto 1) = "01001") then
                        memory_wr <= '1';
                        auto_inc  <= cmd(0);
                    end if;

-                    if (cmd(4 downto 1) = "1010") then
+                    if (cmd(5 downto 1) = "01010") then
                        io_rd <= '1';
                        auto_inc  <= cmd(0);
                    end if;

-                    if (cmd(4 downto 1) = "1011") then
+                    if (cmd(5 downto 1) = "01011") then
                        io_wr <= '1';
                        auto_inc  <= cmd(0);
                    end if;

-                    if (cmd(4 downto 0) = "11000") then
+                    if (cmd(5 downto 0) = "011000") then
                        exec <= '1';
                    end if;

+                    if (cmd(5 downto 3) = "100") then
+                        Special <= cmd(2 downto 0);
+                    end if;
+
+                    if (cmd(5 downto 2) = "1010") then
+                        timer_mode <= cmd(1 downto 0);
+                    end if;
+
                    -- Acknowlege certain commands immediately
-                    if cmd(4) = '0' then
+                    if cmd(5 downto 4) /= "01" then
                        cmd_ack <= not cmd_ack;
                    end if;

@@ -552,7 +580,7 @@ begin
                    single <= '1';
                end if;

-                if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "01000")) then
+                if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "001000")) then
                    Rdy_int <= (not brkpt_active);
                    SS_Step <= (not brkpt_active);
                else
@@ -562,7 +590,13 @@ begin
                -- Latch instruction address for the whole cycle
                if (Sync = '1') then
                    addr_inst <= Addr;
-                    cycleCount_inst <= cycleCount;
+                    if timer_mode = "10" then
+                        instrCount <= timer0Count;
+                    elsif timer_mode = "11" then
+                        instrCount <= timer1Count;
+                    else
+                        instrCount <= cycleCount;
+                    end if;
                end if;

                -- Breakpoints and Watches written to the FIFO
--- a/src/MC6809CpuMon.vhd
+++ b/src/MC6809CpuMon.vhd
@@ -101,6 +101,7 @@ architecture behavioral of MC6809CpuMon is
    signal Addr_int       : std_logic_vector(15 downto 0);
    signal Din            : std_logic_vector(7 downto 0);
    signal Dout           : std_logic_vector(7 downto 0);
+    signal Dbusmon        : std_logic_vector(7 downto 0);
    signal Sync_int       : std_logic;
    signal hold           : std_logic;

@@ -123,7 +124,7 @@ architecture behavioral of MC6809CpuMon is
    signal SS_Single      : std_logic;
    signal SS_Step        : std_logic;
    signal CountCycle     : std_logic;
-    signal special        : std_logic_vector(1 downto 0);
+    signal special        : std_logic_vector(2 downto 0);

    signal LIC_int        : std_logic;

@@ -176,7 +177,7 @@ begin
        cpu_clk      => cpu_clk,
        cpu_clken    => '1',
        Addr         => Addr_int,
-        Data         => Data,
+        Data         => Dbusmon,
        Rd_n         => not R_W_n_int,
        Wr_n         => R_W_n_int,
        RdIO_n       => '1',
@@ -211,8 +212,8 @@ begin
        SS_Single    => SS_Single
    );

+    FIRQ_n_masked <= FIRQ_n or special(2);
    NMI_n_masked  <= NMI_n  or special(1);
-    FIRQ_n_masked <= FIRQ_n or special(1);
    IRQ_n_masked  <= IRQ_n  or special(0);

    -- The CPU is slightly pipelined and the register update of the last
@@ -339,6 +340,13 @@ begin
                         Dout when TSC = '0' and data_wr = '1' and R_W_n_int = '0' and memory_rd1 = '0' else
                  (others => 'Z');

+    -- Version of data seen by the Bus Mon need to use Din rather than the
+    -- external bus value as by the rising edge of cpu_clk we will have stopped driving
+    -- the external bus. On the ALS version we get away way this, but on the GODIL
+    -- version, due to the pullups, we don't. So all write watch breakpoints see
+    -- the data bus as 0xFF.
+    Dbusmon   <= Din when R_W_n_int = '1' else Dout;
+
    memory_done <= memory_rd1 or memory_wr1;

    -- Delayed/Deglitched version of the E clock
--- a/src/MOS6502CpuMonCore.vhd
+++ b/src/MOS6502CpuMonCore.vhd
@@ -82,8 +82,10 @@ architecture behavioral of MOS6502CpuMonCore is
    signal Din_int       : std_logic_vector(7 downto 0);
    signal Dout_int      : std_logic_vector(7 downto 0);
    signal R_W_n_int     : std_logic;
-    signal Rd_n_int      : std_logic;
-    signal Wr_n_int      : std_logic;
+    signal Rd_n_mon      : std_logic;
+    signal Wr_n_mon      : std_logic;
+    signal Sync_mon      : std_logic;
+    signal Done_mon      : std_logic;
    signal Sync_int      : std_logic;
    signal Addr_int      : std_logic_vector(23 downto 0);

@@ -98,7 +100,7 @@ architecture behavioral of MOS6502CpuMonCore is
    signal SS_Step       : std_logic;
    signal SS_Step_held  : std_logic;
    signal CountCycle    : std_logic;
-    signal special       : std_logic_vector(1 downto 0);
+    signal special       : std_logic_vector(2 downto 0);

    signal memory_rd     : std_logic;
    signal memory_rd1    : std_logic;
@@ -131,11 +133,11 @@ begin
        cpu_clken    => cpu_clken,
        Addr         => Addr_int(15 downto 0),
        Data         => Data,
-        Rd_n         => Rd_n_int,
-        Wr_n         => Wr_n_int,
+        Rd_n         => Rd_n_mon,
+        Wr_n         => Wr_n_mon,
        RdIO_n       => '1',
        WrIO_n       => '1',
-        Sync         => Sync_int,
+        Sync         => Sync_mon,
        Rdy          => open,
        nRSTin       => Res_n,
        nRSTout      => cpu_reset_n,
@@ -160,13 +162,16 @@ begin
        AddrOut      => memory_addr,
        DataOut      => memory_dout,
        DataIn       => memory_din,
-        Done         => memory_done,
+        Done         => Done_mon,
        Special      => special,
        SS_Step      => SS_Step,
        SS_Single    => SS_Single
    );
-    Wr_n_int <= R_W_n_int;
-    Rd_n_int <= not R_W_n_int;
+    Wr_n_mon <= Rdy and R_W_n_int;
+    Rd_n_mon <= Rdy and not R_W_n_int;
+    Sync_mon <= Rdy and Sync_int;
+    Done_mon <= Rdy and memory_done;
+
    Data <= Din when R_W_n_int = '1' else Dout_int;
    NMI_n_masked <= NMI_n or special(1);
    IRQ_n_masked <= IRQ_n or special(0);
--- a/src/T80/T80.vhd
+++ b/src/T80/T80.vhd
@@ -380,6 +380,7 @@ architecture rtl of T80 is
 	signal Halt                 : std_logic;
 	signal XYbit_undoc          : std_logic;
 	signal DOR                  : std_logic_vector(127 downto 0);
+	signal IVector              : std_logic_vector(7 downto 0);

 begin

@@ -578,6 +579,12 @@ begin
 							IR <= "11111111";
 						elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
 							IR <= "00000000";
+							-- DMB: It's important to catch the interrupt vector at
+							-- the start of T3, not the middle as the old code
+							-- (using WZ) did. This caused a issue with the Z80
+							-- Second Processor on the GODIL due to the pullups
+							-- (esp on D0)
+							IVector <= DInst;
 						else
 							IR <= DInst;
 						end if;
@@ -631,9 +638,9 @@ begin
 							PC <= "0000000001100110";
 						elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
 							A(15 downto 8) <= I;
-							A(7 downto 0) <= WZ(7 downto 0);
+							A(7 downto 0) <= IVector;
 							PC(15 downto 8) <= unsigned(I);
-							PC(7 downto 0) <= unsigned(WZ(7 downto 0));
+							PC(7 downto 0) <= unsigned(IVector);
 						else
 							case Set_Addr_To is
 							when aXY =>
--- a/src/Z80CpuMon.vhd
+++ b/src/Z80CpuMon.vhd
@@ -110,15 +110,13 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
    signal RFSH_n_int     : std_logic;
    signal M1_n_int       : std_logic;
    signal BUSAK_n_int    : std_logic;
-    signal BUSAK_n_comb   : std_logic;
    signal WAIT_n_latched : std_logic;
    signal TState         : std_logic_vector(2 downto 0);
-    signal TState1        : std_logic_vector(2 downto 0);
    signal SS_Single      : std_logic;
    signal SS_Step        : std_logic;
    signal SS_Step_held   : std_logic;
    signal CountCycle     : std_logic;
-    signal special        : std_logic_vector(1 downto 0);
+    signal special        : std_logic_vector(2 downto 0);
    signal skipNextOpcode : std_logic;

    signal Regs           : std_logic_vector(255 downto 0);
@@ -153,23 +151,17 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
    signal INT_n_sync     : std_logic;
    signal NMI_n_sync     : std_logic;

-    signal Rdy            : std_logic;
    signal Read_n         : std_logic;
    signal Read_n0        : std_logic;
-    signal Read_n1        : std_logic;
    signal Write_n        : std_logic;
    signal Write_n0       : std_logic;
    signal ReadIO_n       : std_logic;
    signal ReadIO_n0      : std_logic;
-    signal ReadIO_n1      : std_logic;
    signal WriteIO_n      : std_logic;
    signal WriteIO_n0     : std_logic;
    signal Sync           : std_logic;
    signal Sync0          : std_logic;
    signal Sync1          : std_logic;
-    signal Mem_IO_n       : std_logic;
-
-    signal MemState       : std_logic_vector(2 downto 0);

    signal Din            : std_logic_vector(7 downto 0);
    signal Dout           : std_logic_vector(7 downto 0);
@@ -327,40 +319,32 @@ begin
    -- really care about the data (it's re-read from memory by the disassembler).
    Sync0    <= '1' when WAIT_n = '1' and M1_n_int = '0' and TState = "010" and skipNextOpcode = '0' else '0';

-    -- For memory reads/write breakpoints we make the monitoring decision in the middle of T2
-    -- but only if WAIT_n is '1' so we catch the right data.
-    Read_n0    <= not (WAIT_n and (not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
-    Write_n0   <= not (WAIT_n and (    RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
-
-    -- For IO reads/writes we make the monitoring decision in the middle of the second T2 cycle
-    -- but only if WAIT_n is '1' so we catch the right data.
-    -- This one cycle delay accounts for the forced wait state
-    ReadIO_n0  <= not (WAIT_n and (not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState1 = "010" else '1';
-    WriteIO_n0 <= not (WAIT_n and (    RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState1 = "010" else '1';
+    -- For reads/write breakpoints we make the monitoring decision in the middle of T3
+    Read_n0    <= not ((not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "011" else '1';
+    Write_n0   <= not ((    RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "011" else '1';
+    ReadIO_n0  <= not ((not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "011" else '1';
+    WriteIO_n0 <= not ((    RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "011" else '1';

    -- Hold the monitoring decision so it is valid on the rising edge of the clock
-    -- For instruction fetches and writes, the monitor sees these at the start of T3
-    -- For reads, the data can arrive in the middle of T3 so delay until end of T3
+    -- For instruction fetches the monitor sees these at the end of T2
+    -- For reads and writes, the data is sampled in the middle of T3 so delay until end of T3
    watch_gen : process(CLK_n)
    begin
        if falling_edge(CLK_n) then
            Sync        <= Sync0;
-            Read_n1     <= Read_n0;
-            Read_n      <= Read_n1;
+            Read_n      <= Read_n0;
            Write_n     <= Write_n0;
-            ReadIO_n1   <= ReadIO_n0;
-            ReadIO_n    <= ReadIO_n1;
+            ReadIO_n    <= ReadIO_n0;
            WriteIO_n   <= WriteIO_n0;
            -- Latch wait seen by T80 on the falling edge, for use on the next rising edge
            WAIT_n_latched <= WAIT_n;
        end if;
    end process;

-    -- Register the exec data on the rising at the end of T2
+    -- Register the exec data on the rising edge of the clock at the end of T2
    ex_data_latch : process(CLK_n)
    begin
        if rising_edge(CLK_n) then
-            TState1 <= TState;
            if Sync = '1' then
                ex_data <= Data;
            end if;
@@ -371,14 +355,14 @@ begin
    rd_data_latch : process(CLK_n)
    begin
        if falling_edge(CLK_n) then
-            if Read_n1 = '0' or ReadIO_n1 = '0' then
+            if Read_n0 = '0' or ReadIO_n0 = '0' then
                rd_data <= Data;
            end if;
            memory_din <= Data;
        end if;
    end process;

-    -- Register the write data on the falling edge in the middle of T2
+    -- Register the read data on the falling edge of clock in the middle of T3
    wr_data_latch : process(CLK_n)
    begin
        if falling_edge(CLK_n) then
--- a/target/common/Makefile.inc
+++ b/target/common/Makefile.inc
@@ -22,7 +22,7 @@ OBJCOPY=avr-objcopy

 PROG = avr_progmem

-CFLAGS=$(CPU_CFLAGS) -DF_CPU=${F_CPU}UL -DBAUD=${BAUD} -mmcu=$(MCU) -Wall -Os -mcall-prologues
+CFLAGS=$(CPU_CFLAGS) -DF_CPU=${F_CPU}UL -DBAUD=${BAUD} -std=c99 -mmcu=$(MCU) -Wall -Os -mcall-prologues

 OBJECTS=AtomBusMon.o status.o $(CPU_OBJECTS)

@@ -30,6 +30,7 @@ build: $(TARGET).mcs

 $(TARGET).mcs: $(TARGET).bit
 	promgen -u 0 $(TARGET).bit -o $(TARGET).mcs -p mcs -w -spi -s 8192
+	promgen -u 0 $(TARGET).bit -o $(TARGET).bin -p bin -w -spi -s 8192
 	rm -f $(TARGET).cfi $(TARGET).prm

 working/$(PROJECT).bit:
--- a/target/godil_250/_icez80/board.ucf
+++ b/target/godil_250/_icez80/board.ucf
@@ -3,6 +3,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;

 NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock49"  LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator

 NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1
--- a/target/godil_250/ice6502/board.ucf
+++ b/target/godil_250/ice6502/board.ucf
@@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
 NET "Phi0" TNM_NET = clk_period_grp_phi0;
 TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33                           ; # 49.152 MHz Oscillator
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 1
 NET "Rdy"        LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 2
--- a/target/godil_250/ice65c02/board.ucf
+++ b/target/godil_250/ice65c02/board.ucf
@@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
 NET "Phi0" TNM_NET = clk_period_grp_phi0;
 TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33                           ; # 49.152 MHz Oscillator
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 1
 NET "Rdy"        LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 2
--- a/target/godil_250/ice6809/board.ucf
+++ b/target/godil_250/ice6809/board.ucf
@@ -3,6 +3,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;

 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 1
 NET "NMI_n"      LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 2
 NET "IRQ_n"      LOC="P18" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 3
--- a/target/godil_500/ice6502/board.ucf
+++ b/target/godil_500/ice6502/board.ucf
@@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
 NET "Phi0" TNM_NET = clk_period_grp_phi0;
 TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33                           ; # 49.152 MHz Oscillator
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 1
 NET "Rdy"        LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 2
--- a/target/godil_500/ice65c02/board.ucf
+++ b/target/godil_500/ice65c02/board.ucf
@@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
 NET "Phi0" TNM_NET = clk_period_grp_phi0;
 TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33                           ; # 49.152 MHz Oscillator
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 1
 NET "Rdy"        LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6502 pin 2
--- a/target/godil_500/ice6809/board.ucf
+++ b/target/godil_500/ice6809/board.ucf
@@ -3,6 +3,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;

 NET "clock49"    LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 #NET "VSS"       LOC="P16" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 1
 NET "NMI_n"      LOC="P95" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 2
 NET "IRQ_n"      LOC="P18" | IOSTANDARD = LVCMOS33                           ; # 6809 pin 3
--- a/target/godil_500/icez80/board.ucf
+++ b/target/godil_500/icez80/board.ucf
@@ -5,6 +5,8 @@ NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;

 NET "clock49"  LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns  ; # 49.152 MHz Oscillator

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1
 NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 2
 NET "Addr<13>" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 3
--- a/target/lx9_dave/gen_mcs.sh
+++ b/target/lx9_dave/gen_mcs.sh
@@ -16,6 +16,9 @@ NAME=${DIR}/icemulti

 mkdir -p ${DIR}

+for FORMAT in mcs bin
+do
+
 promgen                                          \
 -u      0 loader/MultiBootLoader.bit            \
 -u  54000 unknown/UnknownAdapter.bit            \
@@ -23,6 +26,8 @@ promgen                                          \
 -u  FC000 icez80/icez80.bit                     \
 -u 150000 ice65c02/ice65c02.bit                 \
 -u 1A4000 ice6809/ice6809.bit                   \
- -o $NAME.mcs  -p mcs -w -spi -s 8192
+ -o $NAME.$FORMAT  -p $FORMAT -w -spi -s 8192
+
+done

 rm -f $NAME.cfi $NAME.prm
--- a/target/lx9_dave/ice6502/board.ucf
+++ b/target/lx9_dave/ice6502/board.ucf
@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi = PERIOD "clk_period_grp_phi" 250ns LOW;

 NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

 NET "VP_n"     LOC="P35"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
--- a/target/lx9_dave/ice65c02/board.ucf
+++ b/target/lx9_dave/ice65c02/board.ucf
@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi = PERIOD "clk_period_grp_phi" 250ns LOW;

 NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

 NET "VP_n"     LOC="P35"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
--- a/target/lx9_dave/ice6809/board.ucf
+++ b/target/lx9_dave/ice6809/board.ucf
@@ -3,6 +3,8 @@ TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;

 NET "E" CLOCK_DEDICATED_ROUTE = FALSE;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"          LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

 #NET "VSS"           LOC="P"    | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
--- a/target/lx9_dave/icez80/board.ucf
+++ b/target/lx9_dave/icez80/board.ucf
@@ -4,6 +4,8 @@ TIMESPEC TS_clk_period_clk_n = PERIOD "clk_period_grp_clk_n" 125ns LOW;

 NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

 NET "Addr<11>" LOC="P43"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8          ; # dip pin 1
--- a/target/lx9_dave/ipcore/WatchEvents.ngc
+++ b/target/lx9_dave/ipcore/WatchEvents.ngc
--- a/target/lx9_dave/ipcore/WatchEvents.vhd
+++ b/target/lx9_dave/ipcore/WatchEvents.vhd
@@ -22,7 +22,7 @@
 --    devices, or systems.  Use in such applications are expressly            --
 --    prohibited.                                                             --
 --                                                                            --
--    (c) Copyright 1995-2017 Xilinx, Inc.                                    --
+--    (c) Copyright 1995-2020 Xilinx, Inc.                                    --
 --    All rights reserved.                                                    --
 --------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
@@ -96,7 +96,7 @@ END COMPONENT;
      c_axis_type => 0,
      c_common_clock => 1,
      c_count_type => 0,
-      c_data_count_width => 10,
+      c_data_count_width => 13,
      c_default_value => "BlankString",
      c_din_width => 72,
      c_din_width_axis => 1,
@@ -179,7 +179,7 @@ END COMPONENT;
      c_overflow_low => 0,
      c_preload_latency => 0,
      c_preload_regs => 1,
-      c_prim_fifo_type => "512x72",
+      c_prim_fifo_type => "4kx9",
      c_prog_empty_thresh_assert_val => 4,
      c_prog_empty_thresh_assert_val_axis => 1022,
      c_prog_empty_thresh_assert_val_rach => 1022,
@@ -195,14 +195,14 @@ END COMPONENT;
      c_prog_empty_type_wach => 0,
      c_prog_empty_type_wdch => 0,
      c_prog_empty_type_wrch => 0,
-      c_prog_full_thresh_assert_val => 511,
+      c_prog_full_thresh_assert_val => 4095,
      c_prog_full_thresh_assert_val_axis => 1023,
      c_prog_full_thresh_assert_val_rach => 1023,
      c_prog_full_thresh_assert_val_rdch => 1023,
      c_prog_full_thresh_assert_val_wach => 1023,
      c_prog_full_thresh_assert_val_wdch => 1023,
      c_prog_full_thresh_assert_val_wrch => 1023,
-      c_prog_full_thresh_negate_val => 510,
+      c_prog_full_thresh_negate_val => 4094,
      c_prog_full_type => 0,
      c_prog_full_type_axis => 0,
      c_prog_full_type_rach => 0,
@@ -211,10 +211,10 @@ END COMPONENT;
      c_prog_full_type_wdch => 0,
      c_prog_full_type_wrch => 0,
      c_rach_type => 0,
-      c_rd_data_count_width => 10,
-      c_rd_depth => 512,
+      c_rd_data_count_width => 13,
+      c_rd_depth => 4096,
      c_rd_freq => 1,
-      c_rd_pntr_width => 9,
+      c_rd_pntr_width => 12,
      c_rdch_type => 0,
      c_reg_slice_mode_axis => 0,
      c_reg_slice_mode_rach => 0,
@@ -242,8 +242,8 @@ END COMPONENT;
      c_wach_type => 0,
      c_wdch_type => 0,
      c_wr_ack_low => 0,
-      c_wr_data_count_width => 10,
-      c_wr_depth => 512,
+      c_wr_data_count_width => 13,
+      c_wr_depth => 4096,
      c_wr_depth_axis => 1024,
      c_wr_depth_rach => 16,
      c_wr_depth_rdch => 1024,
@@ -251,7 +251,7 @@ END COMPONENT;
      c_wr_depth_wdch => 1024,
      c_wr_depth_wrch => 16,
      c_wr_freq => 1,
-      c_wr_pntr_width => 9,
+      c_wr_pntr_width => 12,
      c_wr_pntr_width_axis => 10,
      c_wr_pntr_width_rach => 4,
      c_wr_pntr_width_rdch => 10,
--- a/target/lx9_dave/ipcore/WatchEvents.xco
+++ b/target/lx9_dave/ipcore/WatchEvents.xco
@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.7
-# Date: Tue Jul 25 16:17:25 2017
+# Date: Mon Jun 22 18:58:13 2020
 #
 ##############################################################
 #
@@ -53,7 +53,7 @@ CSET clock_enable_type=Slave_Interface_Clock_Enable
 CSET clock_type_axi=Common_Clock
 CSET component_name=WatchEvents
 CSET data_count=false
-CSET data_count_width=10
+CSET data_count_width=13
 CSET disable_timing_violations=false
 CSET disable_timing_violations_axi=false
 CSET dout_reset_value=0
@@ -111,14 +111,14 @@ CSET fifo_implementation_wach=Common_Clock_Block_RAM
 CSET fifo_implementation_wdch=Common_Clock_Block_RAM
 CSET fifo_implementation_wrch=Common_Clock_Block_RAM
 CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=511
+CSET full_threshold_assert_value=4095
 CSET full_threshold_assert_value_axis=1023
 CSET full_threshold_assert_value_rach=1023
 CSET full_threshold_assert_value_rdch=1023
 CSET full_threshold_assert_value_wach=1023
 CSET full_threshold_assert_value_wdch=1023
 CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=510
+CSET full_threshold_negate_value=4094
 CSET id_width=4
 CSET inject_dbit_error=false
 CSET inject_dbit_error_axis=false
@@ -135,7 +135,7 @@ CSET inject_sbit_error_wach=false
 CSET inject_sbit_error_wdch=false
 CSET inject_sbit_error_wrch=false
 CSET input_data_width=72
-CSET input_depth=512
+CSET input_depth=4096
 CSET input_depth_axis=1024
 CSET input_depth_rach=16
 CSET input_depth_rdch=1024
@@ -144,7 +144,7 @@ CSET input_depth_wdch=1024
 CSET input_depth_wrch=16
 CSET interface_type=Native
 CSET output_data_width=72
-CSET output_depth=512
+CSET output_depth=4096
 CSET overflow_flag=false
 CSET overflow_flag_axi=false
 CSET overflow_sense=Active_High
@@ -168,7 +168,7 @@ CSET rach_type=FIFO
 CSET rdch_type=FIFO
 CSET read_clock_frequency=1
 CSET read_data_count=false
-CSET read_data_count_width=10
+CSET read_data_count_width=13
 CSET register_slice_mode_axis=Fully_Registered
 CSET register_slice_mode_rach=Fully_Registered
 CSET register_slice_mode_rdch=Fully_Registered
@@ -203,11 +203,11 @@ CSET write_acknowledge_flag=false
 CSET write_acknowledge_sense=Active_High
 CSET write_clock_frequency=1
 CSET write_data_count=false
-CSET write_data_count_width=10
+CSET write_data_count_width=13
 CSET wuser_width=1
 # END Parameters
 # BEGIN Extra information
 MISC pkg_timestamp=2012-11-19T12:39:56Z
 # END Extra information
 GENERATE
-# CRC: 3745e82a
+# CRC: ae9d5adb
--- a/target/lx9_dave/ipcore/WatchEvents.xise
+++ b/target/lx9_dave/ipcore/WatchEvents.xise
@@ -30,6 +30,7 @@

  <properties>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
@@ -51,8 +52,8 @@
    <!--                                                                                  -->
    <property xil_pn:name="PROP_DesignName" xil_pn:value="WatchEvents" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-07-25T17:19:37" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="374CFF28879B2146EB9160793669CDAF" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-06-22T19:59:58" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8443B0C0597663D41E40C7503B5D1699" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
  </properties>
--- a/target/lx9_jason/ice6502/board.ucf
+++ b/target/lx9_jason/ice6502/board.ucf
@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;

 NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

 #NET "VSS"     LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
--- a/target/lx9_jason/ice65c02/board.ucf
+++ b/target/lx9_jason/ice65c02/board.ucf
@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;

 NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

 #NET "VSS"     LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
--- a/target/lx9_jason/ice6809/board.ucf
+++ b/target/lx9_jason/ice6809/board.ucf
@@ -6,6 +6,8 @@ PIN "inst_dcm1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE;

 NET "clock"      LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 #NET "VSS"       LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "NMI_n"      LOC="P95"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
 NET "IRQ_n"      LOC="P98"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
--- a/target/lx9_jason/icez80/board.ucf
+++ b/target/lx9_jason/icez80/board.ucf
@@ -6,6 +6,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;

 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "Addr<11>" LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "Addr<12>" LOC="P95"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
 NET "Addr<13>" LOC="P98"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
--- a/target/lx9_jason_flipped/ice6502/board.ucf
+++ b/target/lx9_jason_flipped/ice6502/board.ucf
@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;

 NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

 #NET "VSS"     LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
--- a/target/lx9_jason_flipped/ice65c02/board.ucf
+++ b/target/lx9_jason_flipped/ice65c02/board.ucf
@@ -6,6 +6,8 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;

 NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

 #NET "VSS"     LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
--- a/target/lx9_jason_flipped/ice6809/board.ucf
+++ b/target/lx9_jason_flipped/ice6809/board.ucf
@@ -6,6 +6,8 @@ PIN "inst_dcm1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE;

 NET "clock"      LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 #NET "VSS"       LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "NMI_n"      LOC="P15"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
 NET "IRQ_n"      LOC="P17"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
--- a/target/lx9_jason_flipped/icez80/board.ucf
+++ b/target/lx9_jason_flipped/icez80/board.ucf
@@ -6,6 +6,8 @@ NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;

 NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator

+NET "trig<0>" CLOCK_DEDICATED_ROUTE = FALSE;
+
 NET "Addr<11>" LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "Addr<12>" LOC="P15"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
 NET "Addr<13>" LOC="P17"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
Author	SHA1	Message	Date
David Banks	1b0c0624ff	Updated release script to include .bin files Change-Id: Ic09c51f721a3c517a43282b053dbdf9a55fba902	2021-09-21 13:20:32 +01:00
David Banks	58978d3e05	Update build scripts to generate .bin files for programming using OpenOCD on a Pi Change-Id: I39909acc3a1fe4504d5e4c2d20d11b23e3878058	2021-09-21 10:57:25 +01:00
David Banks	246cb88e72	Update firmware version to 0.994 Change-Id: I9ef936cb741d78fd57cd51a06ea7882a24185429	2021-06-30 19:45:39 +01:00
David Banks	db014b0e56	Eliminate a divide from hwCmd Change-Id: I85284e3709679d66a11e7f1c00cbd8db4a25da51	2021-06-30 19:45:39 +01:00
David Banks	2773dd97b1	Update firmware version to 0.993 Change-Id: I5e261ecca2bf7c15a6fc4b05f5b90e5b5625a295	2021-04-10 16:15:39 +01:00
David Banks	944f951b18	Added timeout command to change the memory timeout Change-Id: I1e5401356200f20be814ad58f9e7ae7b34fc0a68	2021-04-10 16:15:20 +01:00
David Banks	8f0536c2e9	Update firmware version to 0.992 Change-Id: If0a587272bd6576fc92f23178b33992ba36978bf	2021-03-21 17:44:04 +00:00
David Banks	dc2db74cc3	Z80: Sample IM2 vector at start of T3, not middle Change-Id: I902d5993e35da092b8b702fc21b3fbcbef4cc8c3	2021-03-21 17:43:51 +00:00
David Banks	6abb27cfbe	Update firmware version to 0.991 Change-Id: Id10c3abf34a83666be72d2432bfb1ac4b812b5ca	2021-03-20 17:23:30 +00:00
David Banks	a7cb67c469	Z80: Rd/Wr Mem/IO breakpoint/watchpoint sampled in middle of T3 Change-Id: I9dcca58f121da9e443bd18da8f13a099cfbc2056	2021-03-20 17:22:53 +00:00
David Banks	0e6a31360f	Z80: IO Breakpoint/watchpoint mask defaults to 0xFF Change-Id: Ifbe37871ad9cee29fedc81f967149dc058ab3648	2021-03-20 17:21:03 +00:00
David Banks	97a1e9ad74	Add std=c99 to Makefile.inc Change-Id: I0b0f74c25117ecf18fd479d55fdf818e205d6be8	2021-03-20 17:20:23 +00:00
David Banks	d218caa40b	Updated XPM_T65 to 0.990 Change-Id: Iab134b0375322c226c4d8f3f6f9a4360e933891f	2021-03-13 14:33:45 +00:00
David Banks	530f9118f8	Update firmware version to 0.990 Change-Id: Idc210b311081fa1dffaf0023e6efb0dd2cdc211f	2021-03-13 14:21:13 +00:00
David Banks	6b67360bf3	R65C02: correct cycle counts of JMP (ind) and JMP (ind,x) to 6 Change-Id: I3f7659b0db8d9c6a62577cb5b17052267a0b4154	2021-03-13 14:19:45 +00:00
David Banks	c184b6466a	R65C02: fix warnings Change-Id: I0578e4afcdc0817046bafe2b78fecbfe82102f05	2021-03-13 12:30:59 +00:00
David Banks	839d510af9	R65C02: Whitespace only Change-Id: I19aa6962d48206dc0eb75cabfa9f230e8872822d	2021-03-13 11:23:31 +00:00
David Banks	709c73999b	Updated XPM_T65 to 0.989 Change-Id: I99176656af754985e986c8b2a8bff2a509839c4a	2021-03-11 20:00:41 +00:00
David Banks	ed4d0662ba	Update firmware version to 0.989 Change-Id: I2f05fbf43e9b1094f082c70aafd8f4acf30511cb	2021-03-11 19:21:42 +00:00
David Banks	340f7e33f9	65C02: Implement single cycle NOPs Change-Id: I9e37b42dcce4ee57359e5d3298f38f2eb70663af	2021-03-11 19:02:10 +00:00
David Banks	0aa58bb25c	Whitespace only Change-Id: Ie59536f97544885673000f2a383efd1a1338792b	2021-03-11 19:01:46 +00:00
David Banks	b23bb1d9ce	Update firmware version to 0.988 Change-Id: I58b3200646d0272d9f76f70ff2e9d888d6c327a9	2020-06-22 20:40:02 +01:00
David Banks	b708ec59a8	lx9_dave: update WatchEvents from 512x72 to 4096x72 Change-Id: I6b1fac95150592244cd5662c502ff34fbb885d10	2020-06-22 20:39:08 +01:00
David Banks	a2e2f7c1d1	Updated XPM_T65 to 0.987 Change-Id: I4689fa344f47b976b10e249ac0b7f908e2ff291c	2020-06-21 15:22:51 +01:00
David Banks	68b34da5ba	Update firmware version to 0.987 Change-Id: I755c8cfac46978f3a2c7f061ba332f36874d0072	2020-06-21 15:08:18 +01:00
David Banks	ca40fe81b3	Extend TimerMode command with prescale and reset address Change-Id: Ia958ea97175469b642b4a70579f080dd0ff148cc	2020-06-21 15:07:45 +01:00
David Banks	c0275ff059	Make commands 6-bits, add Special and TimerMode commands Change-Id: I8862fba0cf4c1e54ee831a547bf3337bbe7cf973	2020-06-21 14:12:33 +01:00
David Banks	ddc2ff358c	Updated XPM_T65 to 0.986 Change-Id: I8d18dae89123a84ddbbbf7fe34a5fafbddfc0142	2020-06-20 13:14:49 +01:00
David Banks	41afa8edeb	Update firmware version to 0.986 Change-Id: I475d10f1481279acbdc55a69bb33ebb39a69d25b	2020-06-17 17:18:11 +01:00
David Banks	e931e93dff	6502: fix duplicate break/watchpoints when Rdy in use Change-Id: Idc566462c4496290d4d0a8e14fe568c05907a508	2020-06-17 17:14:00 +01:00
David Banks	d38ae01d6f	Update firmware version to 0.985 Change-Id: Id50f4f2b2e23cd8ab5e23862cf51e2428c56c40c	2020-06-09 19:10:28 +01:00
David Banks	b07b86195c	Firmware: add optional address to next command Change-Id: I5378e5bb8ec767f6504823d190b774c8f523c879	2020-06-09 19:10:28 +01:00
David Banks	2de5c382a7	6809: fix a bug with write watchpoints seeing data as 0xFF Change-Id: Id5ca15ad95a5f5bbee242368ca8bb9b2c0cf7364	2020-06-09 18:55:06 +01:00