65C02: Reset exec_held in MOS6502CpuMonCore (fixes issue with BeebFpga/Gowin)

Change-Id: I9b2a58d7dc911c81bf93090fd8711d4e1d6ae873

.gitignore

@@ -8,6 +8,7 @@ nohup.out
 target/**/*.o
 target/**/*.bit
 target/**/*.mcs
+target/**/*.bin
 target/**/avr_progmem.*
 target/*/ipcore/WatchEvents.asy
 target/*/ipcore/WatchEvents.gise

firmware/AtomBusMon.c

@@ -14,16 +14,35 @@
  * VERSION and NAME are used in the start-up message
  ********************************************************/
 
-#define VERSION "0.994"
+#define VERSION "0.998"
+
+// The X commands allows the various interrupt inputs to be overridded
+// They are named after the data sheet pin name
 
 #if defined(CPU_Z80)
   #define NAME "ICE-Z80"
+  #define XCMD0 "xbusrq"
+  #define XCMD1 "xint"
+  #define XCMD2 "xnmi"
+  #define XCMD3 "xres"
 #elif defined(CPU_6502)
   #define NAME "ICE-6502"
+  #define XCMD0 "xirq"
+  #define XCMD1 "xnmi"
+  #define XCMD2 "xres"
+  #define XCMD3 "xso "
 #elif defined(CPU_65C02)
   #define NAME "ICE-65C02"
+  #define XCMD0 "xirq"
+  #define XCMD1 "xnmi"
+  #define XCMD2 "xres"
+  #define XCMD3 "xso "
 #elif defined(CPU_6809)
   #define NAME "ICE-6809"
+  #define XCMD0 "xfiq"
+  #define XCMD1 "xirq"
+  #define XCMD2 "xnmi"
+  #define XCMD3 "xres"
 #else
   #error "Unsupported CPU type"
 #endif
@@ -70,7 +89,6 @@ char *cmdStrings[] = {
   "load",
   "save",
   "srec",
-  "special",
   "reset",
   "trace",
   "blist",
@@ -89,7 +107,11 @@ char *cmdStrings[] = {
   "clear",
   "trigger",
   "timermode",
-  "timeout"
+  "timeout",
+  XCMD0,
+  XCMD1,
+  XCMD2,
+  XCMD3
 };
 
 // Must be kept in step with cmdStrings (just above)
@@ -125,7 +147,6 @@ void (*cmdFuncs[])(char *params) = {
   doCmdLoad,
   doCmdSave,
   doCmdSRec,
-  doCmdSpecial,
   doCmdReset,
   doCmdTrace,
   doCmdList,
@@ -144,7 +165,11 @@ void (*cmdFuncs[])(char *params) = {
   doCmdClear,
   doCmdTrigger,
   doCmdTimerMode,
-  doCmdTimeout
+  doCmdTimeout,
+  doCmdXCmd0,
+  doCmdXCmd1,
+  doCmdXCmd2,
+  doCmdXCmd3
 };
 
 #if defined(EXTENDED_HELP)
@@ -167,6 +192,7 @@ static const char ARGS14[] PROGMEM = "[ <value> ]";
 static const char ARGS15[] PROGMEM = "[ <command> ]";
 static const char ARGS16[] PROGMEM = "<op1> [ <op2> [ <op3> ] ]";
 static const char ARGS17[] PROGMEM = "[ <source> [ <prescale> [ <reset address> ] ] ]";
+static const char ARGS18[] PROGMEM = "e|c|d|f";
 
 static const char * const argsStrings[] PROGMEM = {
   ARGS00,
@@ -187,6 +213,7 @@ static const char * const argsStrings[] PROGMEM = {
   ARGS15,
   ARGS16,
   ARGS17,
+  ARGS18
 };
 
 // Must be kept in step with cmdStrings (just above)
@@ -197,7 +224,7 @@ static const uint8_t helpMeta[] PROGMEM = {
   17, 15, // help
    9,  8, // continue
   24,  1, // next
-  32,  6, // step
+  31,  6, // step
   27,  7, // regs
   12, 10, // dis
   16,  7, // flush
@@ -207,7 +234,7 @@ static const uint8_t helpMeta[] PROGMEM = {
    8, 13, // compare
   22,  1, // mem
   26,  2, // rd
-  43,  3, // wr
+  42,  3, // wr
 #if defined(CPU_Z80)
   20,  1, // io
   19,  2, // in
@@ -218,30 +245,33 @@ static const uint8_t helpMeta[] PROGMEM = {
   15, 16, // exec
   23, 14, // mode
 #endif
-  33, 12, // test
+  32, 12, // test
   21,  0, // load
   29,  9, // save
-  31,  7, // srec
-  30, 14, // special
+  30,  7, // srec
   28,  7, // reset
-  36,  6, // trace
+  35,  6, // trace
    1,  7, // blist
    6,  4, // breakx
-  42,  4, // watchx
+  41,  4, // watchx
    4,  4, // breakr
-  40,  4, // watchr
+  39,  4, // watchr
    5,  4, // breakw
-  41,  4, // watchw
+  40,  4, // watchw
 #if defined(CPU_Z80)
    2,  4, // breaki
-  38,  4, // watchi
+  37,  4, // watchi
    3,  4, // breako
-  39,  4, // watcho
+  38,  4, // watcho
 #endif
    7,  0, // clear
-  37,  5, // trigger
-  35, 17, // timermode
-  34, 14, // timeout
+  36,  5, // trigger
+  34, 17, // timermode
+  33, 14, // timeout
+  43, 18, // xcmd0
+  44, 18, // xcmd1
+  45, 18, // xcmd2
+  46, 18, // xcmd3
    0,  0
 };
 
@@ -286,8 +316,8 @@ static const uint8_t helpMeta[] PROGMEM = {
 // 011xx1 Unused
 // 011x1x Unused
 // 0111xx Unused
-// 100xxx Special
-// 1010xx Timer Mode
+// 10xxxx Int Ctrl
+// 1100xx Timer Mode
 //     00 - count cpu cycles where clken = 1 and CountCycle = 1
 //     01 - count cpu cycles where clken = 1 (ignoring CountCycle)
 //     10 - free running timer, using busmon_clk as the source
@@ -310,8 +340,8 @@ static const uint8_t helpMeta[] PROGMEM = {
 #define CMD_WR_IO         0x16
 #define CMD_WR_IO_INC     0x17
 #define CMD_EXEC_GO       0x18
-#define CMD_SPECIAL       0x20
-#define CMD_TIMER_MODE    0x28
+#define CMD_INT_CTRL      0x20
+#define CMD_TIMER_MODE    0x30
 
 /********************************************************
  * AVR Status Register Definitions
@@ -609,6 +639,24 @@ static const char * triggerStrings[NUM_TRIGGERS] = {
 
 #define TRIGGER_UNDEFINED 31
 
+/********************************************************
+ * Interrupt controls
+ ********************************************************/
+
+static const uint8_t cmd_map[] = { 1, 3, 0, 2 };
+
+static const char INTCTRL0[] PROGMEM = "Enabled";
+static const char INTCTRL1[] PROGMEM = "Conditional";
+static const char INTCTRL2[] PROGMEM = "Forced";
+static const char INTCTRL3[] PROGMEM = "Disabled";
+
+static const char *int_ctrl_strings[] = {
+   INTCTRL0,
+   INTCTRL1,
+   INTCTRL2,
+   INTCTRL3
+};
+
 /********************************************************
  * Other global variables
  ********************************************************/
@@ -637,15 +685,16 @@ uint8_t cmd_id = 0xff;
 #define MASK_CLOCK_ERROR   1
 #define MASK_TIMEOUT_ERROR 2
 
-// Current special setting
-uint8_t special = 0x00;
-
 // Current timer mode setting
 uint8_t timer_mode = 0x00;
 uint8_t timer_prescale = 0x01;
 addr_t  timer_resetaddr = 0xffff;
 unsigned long timer_offset = 0;
 
+// Current interrupts controls
+uint8_t int_ctrl = 0;
+
+
 /********************************************************
  * User Command Processor
  ********************************************************/
@@ -922,7 +971,7 @@ void writeIOByteInc() {
 
 addr_t disMem(addr_t addr) {
   loadAddr(addr);
-  return disassemble(addr);
+  return disassemble(addr, MODE_NORMAL);
 }
 
 void genericDump(char *params, data_t (*readFunc)()) {
@@ -1526,7 +1575,7 @@ void doCmdDis(char *params) {
   memAddr = startAddr;
   loadAddr(memAddr);
   do {
-    memAddr = disassemble(memAddr);
+     memAddr = disassemble(memAddr, MODE_DIS_CMD);
     i++;
   } while ((!endAddr && i < 10) || (endAddr && memAddr > startAddr && memAddr <= endAddr));
 }
@@ -2032,31 +2081,50 @@ void doCmdSRec(char *params) {
   }
 }
 
-void logSpecial(char *function, uint8_t value) {
-  logs(function);
-  if (value) {
-    logstr(" inhibited\n");
-  } else {
-    logstr(" enabled\n");
-  }
+void set_int_ctrl(uint8_t offset, char *params) {
+   // (C) 01 Conditional
+   // (D) 11 Disabled
+   // (E) 00 Enabled
+   // (F) 10 Forced
+   while (*params == ' ') {
+      params++;
+   }
+   if (!*params) {
+      uint8_t tmp = int_ctrl;
+      for (int i = 0; i < 4; i++) {
+         logs(cmdStrings[NUM_CMDS - 4 + i]);
+         logstr(" = ");
+         logpgmstr(int_ctrl_strings[tmp & 3]);
+         logc('\n');
+         tmp >>= 2;
+      }
+   } else {
+      *params &= 0xdf;
+      if (*params >= 'C' && *params <= 'F') {
+         uint8_t val = cmd_map[*params - 'C'];
+         hwCmd(CMD_INT_CTRL, (offset << 1) | val);
+         int_ctrl &= (0x03 << offset) ^ 0xFF;
+         int_ctrl |= (val  << offset);
+      } else {
+         logstr("Illegal option\n");
+      }
+   }
 }
 
-void doCmdSpecial(char *params) {
-  uint8_t tmp = 0xff;
-  parsehex2(params, &tmp);
-#if defined(CPU_6809)
-  if (tmp <= 7) {
-#else
-  if (tmp <= 3) {
-#endif
-    special = tmp;
-    hwCmd(CMD_SPECIAL, special);
-  }
-#if defined(CPU_6809)
-  logSpecial("FIRQ", special & 4);
-#endif
-  logSpecial("NMI", special & 2);
-  logSpecial("IRQ", special & 1);
+void doCmdXCmd0(char *params) {
+   set_int_ctrl(0, params);
+}
+
+void doCmdXCmd1(char *params) {
+   set_int_ctrl(2, params);
+}
+
+void doCmdXCmd2(char *params) {
+   set_int_ctrl(4, params);
+}
+
+void doCmdXCmd3(char *params) {
+   set_int_ctrl(6, params);
 }
 
 void doCmdTimerMode(char *params) {

firmware/AtomBusMon.h

@@ -76,7 +76,6 @@ void doCmdStep(char *params);
 void doCmdTest(char *params);
 void doCmdSave(char *params);
 void doCmdSRec(char *params);
-void doCmdSpecial(char *params);
 void doCmdTimerMode(char *params);
 void doCmdTimeout(char *params);
 void doCmdTrace(char *params);
@@ -88,5 +87,9 @@ void doCmdWatchWrIO(char *params);
 void doCmdWatchWrMem(char *params);
 void doCmdWriteIO(char *params);
 void doCmdWriteMem(char *params);
+void doCmdXCmd0(char *params);
+void doCmdXCmd1(char *params);
+void doCmdXCmd2(char *params);
+void doCmdXCmd3(char *params);
 
 #endif

firmware/dis.h

@@ -6,6 +6,10 @@
 #define PDC_DDR          DDRA
 #define PDC_DIN          PINA
 
-addr_t disassemble(addr_t addr);
+#define MODE_NORMAL      0
+#define MODE_DIS_CMD     1
+
+addr_t disassemble(addr_t addr, uint8_t m);
+
 
 #endif

firmware/dis6502.c

@@ -149,7 +149,7 @@ static const unsigned char dopname[256] PROGMEM =
 
 static const unsigned char dopaddr[256] PROGMEM =
 {
-/*00*/ IMP, INDX,  IMP, IMP,  IMP,  ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  IMP,    ABS,   ABS,  IMP,
+/*00*/ IMM, INDX,  IMP, IMP,  IMP,  ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  IMP,    ABS,   ABS,  IMP,
 /*10*/ BRA, INDY,  IMP, IMP,  IMP,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  IMP,    ABSX,  ABSX, IMP,
 /*20*/ ABS, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
 /*30*/ BRA, INDY,  IMP, IMP,  IMP,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  IMP,    ABSX,  ABSX, IMP,
@@ -167,7 +167,7 @@ static const unsigned char dopaddr[256] PROGMEM =
 /*F0*/ BRA, INDY,  IMP, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP
 };
 
-addr_t disassemble(addr_t addr)
+addr_t disassemble(addr_t addr, uint8_t m)
 {
 
   char buffer[40];

firmware/dis65c02.c

@@ -169,7 +169,7 @@ static const unsigned char dopname[256] PROGMEM =
 
 static const unsigned char dopaddr[256] PROGMEM =
 {
-/*00*/ IMP, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
+/*00*/ IMM, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
 /*10*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMPA,  IMP,  ABS,    ABSX,  ABSX, IMP,
 /*20*/ ABS, INDX,  IMP, IMP,  ZP,   ZP,    ZP,   IMP,   IMP,  IMM,   IMPA,  IMP,  ABS,    ABS,   ABS,  IMP,
 /*30*/ BRA, INDY,  IND, IMP,  ZPX,  ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMPA,  IMP,  ABSX,   ABSX,  ABSX, IMP,
@@ -187,7 +187,7 @@ static const unsigned char dopaddr[256] PROGMEM =
 /*F0*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,  IMP,   IMP,  ABSY,  IMP,   IMP,  ABS,    ABSX,  ABSX, IMP
 };
 
-addr_t disassemble(addr_t addr)
+addr_t disassemble(addr_t addr, uint8_t m)
 {
 
   char buffer[40];

firmware/dis6809.c

@@ -647,7 +647,7 @@ static char *strcc(char *ptr, uint8_t val) {
 
 /* disassemble one instruction at address addr and return the address of the next instruction */
 
-addr_t disassemble(addr_t addr) {
+addr_t disassemble(addr_t addr, uint8_t m) {
   uint8_t d = get_memb(addr);
   uint8_t s;
   int8_t i;

firmware/disz80.c

@@ -530,9 +530,9 @@ static const unsigned char cmd_ED40[192] PROGMEM = {
     NOP,0,0
   };
 
-static const char word_EX_HALT[] PROGMEM = "**HALT**";
-static const char word_EX_INT[] PROGMEM = "**INT**";
-static const char word_EX_NMI[] PROGMEM = "**NMI**";
+static const char msg_HALT[] PROGMEM = "**HALT**\n";
+static const char msg_INT[] PROGMEM = "**INT**\n";
+static const char msg_NMI[] PROGMEM = "**NMI**\n";
 
 unsigned char cmd_halt[] = { HALT,0,0 };
 unsigned char cmd_nop[]  = { NOP,0,0 };
@@ -887,12 +887,15 @@ char * disassem (char *ptr, unsigned int *ip) {
   return ptr;
 }
 
-addr_t disassemble(addr_t addr) {
+addr_t disassemble(addr_t addr, uint8_t m) {
   static char buffer[64];
 
   char *ptr;
   addr_t addr2 = addr;
 
+  // Ignore the current CPU state in the disassemble connamd
+  uint8_t pdc = (m == MODE_DIS_CMD) ? 0 : PDC_DIN;
+
   // 0123456789012345678901234567890123456789
   // AAAA : HH HH HH HH : LD   RR,($XXXX)
 
@@ -905,17 +908,18 @@ addr_t disassemble(addr_t addr) {
 
   // Opcode
   ptr = buffer + 21;
-  if (PDC_DIN & 0x80) {
-    strcpy_P(ptr, PSTR("**HALT**"));
-  } else if (PDC_DIN & 0x40) {
-    strcpy(ptr, PSTR("**NMI**"));
-  } else if (PDC_DIN & 0x20) {
-    strcpy(ptr, PSTR("**INT**"));
+
+  if (pdc & 0x80) {
+    strcpy_P(ptr, msg_HALT);
+  } else if (pdc & 0x40) {
+    strcpy(ptr, msg_NMI);
+  } else if (pdc & 0x20) {
+    strcpy(ptr, msg_INT);
   } else {
     ptr = disassem(ptr, &addr2);
+    *ptr++ = '\n';
+    *ptr++ = '\0';
   }
-  *ptr++ = '\n';
-  *ptr++ = '\0';
 
   // Hex
   loadAddr(addr);

src/AlanD/R65Cx2.vhd

@@ -369,7 +369,7 @@ architecture Behavioral of R65C02 is
         "1000" & "100010" & readIndX  & aluInT   & aluEor, -- 41 EOR (zp,x)
         "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 42 NOP ------- 65C02
         "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 43 NOP ------- 65C02
-        "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 44 NOP ------- 65C02
+        "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 44 NOP ------- 65C02
         "1000" & "100010" & readZp    & aluInT   & aluEor, -- 45 EOR zp
         "0000" & "100011" & rmwZp     & aluInT   & aluLsr, -- 46 LSR zp
         "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 47 NOP ------- 65C02
@@ -385,7 +385,7 @@ architecture Behavioral of R65C02 is
         "1000" & "100010" & readIndY  & aluInT   & aluEor, -- 51 EOR (zp),y
         "1000" & "100010" & readInd   & aluInT   & aluEor, -- 52 EOR (zp) -------- 65C02
         "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 53 NOP ------- 65C02
-        "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 54 NOP ------- 65C02
+        "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 54 NOP ------- 65C02
         "1000" & "100010" & readZpX   & aluInT   & aluEor, -- 55 EOR zp,x
         "0000" & "100011" & rmwZpX    & aluInT   & aluLsr, -- 56 LSR zp,x
         "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 57 NOP ------- 65C02
@@ -518,7 +518,7 @@ architecture Behavioral of R65C02 is
         "0000" & "100011" & readIndY  & aluInT   & aluCmp, -- D1 CMP (zp),y
         "0000" & "100011" & readInd   & aluInT   & aluCmp, -- D2 CMP (zp) ------ 65C02
         "0000" & "000000" & implied   & aluInXXX & aluXXX, -- D3 NOP ----- 65C02
-        "0000" & "000000" & immediate & aluInXXX & aluXXX, -- D4 NOP ----- 65C02
+        "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- D4 NOP ----- 65C02
         "0000" & "100011" & readZpX   & aluInT   & aluCmp, -- D5 CMP zp,x
         "0000" & "100010" & rmwZpX    & aluInT   & aluDec, -- D6 DEC zp,x
         "0000" & "000000" & implied   & aluInXXX & aluXXX, -- D7 NOP ----- 65C02
@@ -551,7 +551,7 @@ architecture Behavioral of R65C02 is
         "1000" & "110011" & readIndY  & aluInT   & aluSbc, -- F1 SBC (zp),y
         "1000" & "110011" & readInd   & aluInT   & aluSbc, -- F2 SBC (zp) ------ 65C02
         "0000" & "000000" & implied   & aluInXXX & aluXXX, -- F3 NOP ----- 65C02
-        "0000" & "000000" & immediate & aluInXXX & aluXXX, -- F4 NOP ----- 65C02
+        "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- F4 NOP ----- 65C02
         "1000" & "110011" & readZpX   & aluInT   & aluSbc, -- F5 SBC zp,x
         "0000" & "100010" & rmwZpX    & aluInT   & aluInc, -- F6 INC zp,x
         "0000" & "000000" & implied   & aluInXXX & aluXXX, -- F7 NOP  ---- 65C02
@@ -775,7 +775,7 @@ begin
         varC := ninebits(8);
 
         case opcInfo(aluMode2From to aluMode2To) is
-            --    Flags Affected: n v — — — — z c
+            --    Flags Affected: n v - - - - z c
             --    n Set if most significant bit of result is set; else cleared.
             --    v Set if signed overflow; cleared if valid signed result.
             --    z Set if result is zero; else cleared.

src/BusMonCore.vhd

@@ -71,8 +71,8 @@ entity BusMonCore is
         DataIn           : in std_logic_vector(7 downto 0);
         Done             : in std_logic;
 
-        -- Special outputs (function is CPU specific)
-        Special          : out std_logic_vector(2 downto 0);
+        -- External Interrupt Control
+        int_ctrl         : out std_logic_vector(7 downto 0) := x"00";
 
         -- Single Step interface
         SS_Single        : out std_logic;
@@ -459,8 +459,8 @@ begin
     -- 0111xx Unused
     -- 011x1x Unused
     -- 011xx1 Unused
-    -- 100xxx Special
-    -- 1010xx Timer Mode
+    -- 10xxxx Int Ctrl
+    -- 1100xx Timer Mode
     --     00 - count cpu cycles where clken = 1 and CountCycle = 1
     --     01 - count cpu cycles where clken = 1 (ignoring CountCycle)
     --     10 - free running timer, using busmon_clk as the source
@@ -551,11 +551,11 @@ begin
                         exec <= '1';
                     end if;
 
-                    if (cmd(5 downto 3) = "100") then
-                        Special <= cmd(2 downto 0);
+                    if (cmd(5 downto 4) = "10") then
+                        int_ctrl(to_integer(unsigned(cmd(3 downto 2))) * 2 + 1 downto to_integer(unsigned(cmd(3 downto 2))) * 2) <= cmd(1 downto 0);
                     end if;
 
-                    if (cmd(5 downto 2) = "1010") then
+                    if (cmd(5 downto 2) = "1100") then
                         timer_mode <= cmd(1 downto 0);
                     end if;
 

src/MC6809CpuMon.vhd

@@ -124,7 +124,7 @@ architecture behavioral of MC6809CpuMon is
     signal SS_Single      : std_logic;
     signal SS_Step        : std_logic;
     signal CountCycle     : std_logic;
-    signal special        : std_logic_vector(2 downto 0);
+    signal int_ctrl       : std_logic_vector(7 downto 0);
 
     signal LIC_int        : std_logic;
 
@@ -140,9 +140,10 @@ architecture behavioral of MC6809CpuMon is
     signal data_wr        : std_logic;
     signal nRSTout        : std_logic;
 
-    signal NMI_n_masked   : std_logic;
-    signal IRQ_n_masked   : std_logic;
     signal FIRQ_n_masked  : std_logic;
+    signal IRQ_n_masked   : std_logic;
+    signal NMI_n_masked   : std_logic;
+    signal RES_n_masked   : std_logic;
 
 begin
 
@@ -184,7 +185,7 @@ begin
         WrIO_n       => '1',
         Sync         => Sync_int,
         Rdy          => open,
-        nRSTin       => RES_n,
+        nRSTin       => RES_n_masked,
         nRSTout      => cpu_reset_n,
         CountCycle   => CountCycle,
         trig         => trig,
@@ -207,14 +208,28 @@ begin
         DataOut      => memory_dout,
         DataIn       => memory_din,
         Done         => memory_done,
-        Special      => special,
+        int_ctrl     => int_ctrl,
         SS_Step      => SS_Step,
         SS_Single    => SS_Single
     );
 
-    FIRQ_n_masked <= FIRQ_n or special(2);
-    NMI_n_masked  <= NMI_n  or special(1);
-    IRQ_n_masked  <= IRQ_n  or special(0);
+    -- The two int control bits work as follows
+    -- 00 -> IRQ_n                (enabled)
+    -- 01 -> IRQ_n or SS_Single   (enabled when free-running)
+    -- 10 -> 0                    (forced)
+    -- 11 -> 1                    (disabled)
+
+    FIRQ_n_masked <= int_ctrl(0) when int_ctrl(1) = '1' else
+                     FIRQ_n or (int_ctrl(0) and SS_single);
+
+    IRQ_n_masked  <= int_ctrl(2) when int_ctrl(3) = '1' else
+                     IRQ_n or (int_ctrl(2) and SS_single);
+
+    NMI_n_masked  <= int_ctrl(4) when int_ctrl(5) = '1' else
+                     NMI_n or (int_ctrl(4) and SS_single);
+
+    RES_n_masked  <= int_ctrl(6) when int_ctrl(7) = '1' else
+                     RES_n or (int_ctrl(6) and SS_single);
 
     -- The CPU is slightly pipelined and the register update of the last
     -- instruction overlaps with the opcode fetch of the next instruction.

src/MOS6502CpuMon.vhd

@@ -48,14 +48,14 @@ entity MOS6502CpuMon is
         Rdy             : in    std_logic;
 
         -- External trigger inputs
-        trig             : in    std_logic_vector(1 downto 0);
+        trig            : in    std_logic_vector(1 downto 0);
 
         -- Jumpers
-        fakeTube_n      : in     std_logic;
+        fakeTube_n      : in    std_logic;
 
         -- Serial Console
-        avr_RxD         : in     std_logic;
-        avr_TxD         : out    std_logic;
+        avr_RxD         : in    std_logic;
+        avr_TxD         : out   std_logic;
 
         -- Switches
         sw_reset_cpu    : in    std_logic;
@@ -67,9 +67,12 @@ entity MOS6502CpuMon is
         led_trig1       : out   std_logic;
 
         -- OHO_DY1 connected to test connector
-        tmosi            : out   std_logic;
-        tdin             : out   std_logic;
-        tcclk            : out   std_logic
+        tmosi           : out   std_logic;
+        tdin            : out   std_logic;
+        tcclk           : out   std_logic;
+
+        -- Test connector signals
+        test            : inout std_logic_vector(3 downto 0)
     );
 end MOS6502CpuMon;
 
@@ -141,7 +144,8 @@ begin
         led_trig1    => led_trig1,
         tmosi        => tmosi,
         tdin         => tdin,
-        tcclk        => tcclk
+        tcclk        => tcclk,
+        test         => test
     );
 
     sync_gen : process(cpu_clk)

src/MOS6502CpuMonALS.vhd

@@ -79,18 +79,21 @@ entity MOS6502CpuMonALS is
         avr_TxD          : out   std_logic;
 
         -- Switches
-        sw1               : in   std_logic;
-        sw2               : in   std_logic;
+        sw1              : in   std_logic;
+        sw2              : in   std_logic;
 
         -- LEDs
-        led1              : out  std_logic;
-        led2              : out  std_logic;
-        led3              : out  std_logic;
+        led1             : out  std_logic;
+        led2             : out  std_logic;
+        led3             : out  std_logic;
 
         -- OHO_DY1 LED display
-        tmosi             : out  std_logic;
-        tdin              : out  std_logic;
-        tcclk             : out  std_logic
+        tmosi            : out  std_logic;
+        tdin             : out  std_logic;
+        tcclk            : out  std_logic;
+
+        -- Test connector signals
+        test             : inout std_logic_vector(3 downto 0)
     );
 end MOS6502CpuMonALS;
 
@@ -166,7 +169,10 @@ begin
             -- OHO_DY1 LED display
             tmosi            => tmosi,
             tdin             => tdin,
-            tcclk            => tcclk
+            tcclk            => tcclk,
+
+            -- Test signals
+            test             => test
             );
 
     -- 6502 Outputs

src/MOS6502CpuMonCore.vhd

@@ -67,7 +67,10 @@ entity MOS6502CpuMonCore is
         -- OHO_DY1 connected to test connector
         tmosi           : out   std_logic;
         tdin            : out   std_logic;
-        tcclk           : out   std_logic
+        tcclk           : out   std_logic;
+
+        -- Test connector signals
+        test            : inout std_logic_vector(3 downto 0)
     );
 end MOS6502CpuMonCore;
 
@@ -100,7 +103,7 @@ architecture behavioral of MOS6502CpuMonCore is
     signal SS_Step       : std_logic;
     signal SS_Step_held  : std_logic;
     signal CountCycle    : std_logic;
-    signal special       : std_logic_vector(2 downto 0);
+    signal int_ctrl      : std_logic_vector(7 downto 0);
 
     signal memory_rd     : std_logic;
     signal memory_rd1    : std_logic;
@@ -111,8 +114,11 @@ architecture behavioral of MOS6502CpuMonCore is
     signal memory_din    : std_logic_vector(7 downto 0);
     signal memory_done   : std_logic;
 
-    signal NMI_n_masked  : std_logic;
+
     signal IRQ_n_masked  : std_logic;
+    signal NMI_n_masked  : std_logic;
+    signal Res_n_masked  : std_logic;
+    signal SO_n_masked   : std_logic;
 
     signal exec          : std_logic;
     signal exec_held     : std_logic;
@@ -139,7 +145,7 @@ begin
         WrIO_n       => '1',
         Sync         => Sync_mon,
         Rdy          => open,
-        nRSTin       => Res_n,
+        nRSTin       => Res_n_masked,
         nRSTout      => cpu_reset_n,
         CountCycle   => CountCycle,
         trig         => trig,
@@ -163,7 +169,7 @@ begin
         DataOut      => memory_dout,
         DataIn       => memory_din,
         Done         => Done_mon,
-        Special      => special,
+        int_ctrl     => int_ctrl,
         SS_Step      => SS_Step,
         SS_Single    => SS_Single
     );
@@ -173,8 +179,24 @@ begin
     Done_mon <= Rdy and memory_done;
 
     Data <= Din when R_W_n_int = '1' else Dout_int;
-    NMI_n_masked <= NMI_n or special(1);
-    IRQ_n_masked <= IRQ_n or special(0);
+
+    -- The two int control bits work as follows
+    -- 00 -> IRQ_n                (enabled)
+    -- 01 -> IRQ_n or SS_Single   (enabled when free-running)
+    -- 10 -> 0                    (forced)
+    -- 11 -> 1                    (disabled)
+
+    IRQ_n_masked <= int_ctrl(0) when int_ctrl(1) = '1' else
+                    IRQ_n or (int_ctrl(0) and SS_single);
+
+    NMI_n_masked <= int_ctrl(2) when int_ctrl(3) = '1' else
+                    NMI_n or (int_ctrl(2) and SS_single);
+
+    Res_n_masked <= int_ctrl(4) when int_ctrl(5) = '1' else
+                     Res_n or (int_ctrl(4) and SS_single);
+
+    SO_n_masked  <= int_ctrl(6) when int_ctrl(7) = '1' else
+                    SO_n or (int_ctrl(6) and SS_single);
 
     -- The CPU is slightly pipelined and the register update of the last
     -- instruction overlaps with the opcode fetch of the next instruction.
@@ -209,7 +231,7 @@ begin
         inst_t65: entity work.T65 port map (
             mode            => "00",
             Abort_n         => '1',
-            SO_n            => SO_n,
+            SO_n            => SO_n_masked,
             Res_n           => cpu_reset_n,
             Enable          => cpu_clken_ss,
             Clk             => cpu_clk,
@@ -278,6 +300,7 @@ begin
     begin
         if cpu_reset_n = '0' then
             state <= idle;
+            exec_held <= '0';
         elsif rising_edge(cpu_clk) then
             -- Extend the control signals from BusMonitorCore which
             -- only last one cycle.
@@ -372,4 +395,10 @@ begin
 
     memory_din <= Din;
 
+    -- Test outputs
+    test(0) <= SS_Single;     -- GODIL J5 pin 1 (46)
+    test(1) <= 'Z';           -- GODIL J5 pin 2 (47)
+    test(2) <= 'Z';           -- GODIL J5 pin 3 (48)
+    test(3) <= 'Z';           -- GODIL J5 pin 4 (56)
+
 end behavioral;

src/T80/T80.vhd

@@ -21,7 +21,7 @@
 -- ****
 -- Z80 compatible microprocessor core
 --
--- Version : 0247
+-- Version : 0250
 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
 -- All rights reserved
 --
@@ -73,14 +73,14 @@
 --      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
 --      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
 --      0247 : Fixed bus req/ack cycle
+--      0250 : Added R800 Multiplier by TobiFlex 2017.10.15
 --
 
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use IEEE.STD_LOGIC_UNSIGNED.all;
-
-use work.all;
+use work.T80_Pack.all;
 
 entity T80 is
 	generic(
@@ -120,6 +120,7 @@ entity T80 is
 		NMICycle_n : out std_logic;
 		IntE       : out std_logic;
 		Stop       : out std_logic;
+		R800_mode  : in  std_logic := '0';
 		out0       : in  std_logic := '0';  -- 0 => OUT(C),0, 1 => OUT(C),255
 		REG        : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
 
@@ -129,136 +130,6 @@ entity T80 is
 end T80;
 
 architecture rtl of T80 is
-    component T80_MCode
-        generic(
-            Mode   : integer := 0;
-            Flag_C : integer := 0;
-            Flag_N : integer := 1;
-            Flag_P : integer := 2;
-            Flag_X : integer := 3;
-            Flag_H : integer := 4;
-            Flag_Y : integer := 5;
-            Flag_Z : integer := 6;
-            Flag_S : integer := 7
-        );
-        port(
-          IR          : in std_logic_vector(7 downto 0);
-          ISet        : in std_logic_vector(1 downto 0);
-          MCycle      : in std_logic_vector(2 downto 0);
-          F           : in std_logic_vector(7 downto 0);
-          NMICycle    : in std_logic;
-          IntCycle    : in std_logic;
-          XY_State    : in std_logic_vector(1 downto 0);
-          MCycles     : out std_logic_vector(2 downto 0);
-          TStates     : out std_logic_vector(2 downto 0);
-          Prefix      : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-          Inc_PC      : out std_logic;
-          Inc_WZ      : out std_logic;
-          IncDec_16   : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-          Read_To_Reg : out std_logic;
-          Read_To_Acc : out std_logic;
-          Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-          Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-          ALU_Op      : out std_logic_vector(3 downto 0);
-             -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-          Save_ALU    : out std_logic;
-          PreserveC   : out std_logic;
-          Arith16     : out std_logic;
-          Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-          IORQ        : out std_logic;
-          Jump        : out std_logic;
-          JumpE       : out std_logic;
-          JumpXY      : out std_logic;
-          Call        : out std_logic;
-          RstP        : out std_logic;
-          LDZ         : out std_logic;
-          LDW         : out std_logic;
-          LDSPHL      : out std_logic;
-          Special_LD  : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-          ExchangeDH  : out std_logic;
-          ExchangeRp  : out std_logic;
-          ExchangeAF  : out std_logic;
-          ExchangeRS  : out std_logic;
-          I_DJNZ      : out std_logic;
-          I_CPL       : out std_logic;
-          I_CCF       : out std_logic;
-          I_SCF       : out std_logic;
-          I_RETN      : out std_logic;
-          I_BT        : out std_logic;
-          I_BC        : out std_logic;
-          I_BTR       : out std_logic;
-          I_RLD       : out std_logic;
-          I_RRD       : out std_logic;
-          I_INRC      : out std_logic;
-          SetWZ       : out std_logic_vector(1 downto 0);
-          SetDI       : out std_logic;
-          SetEI       : out std_logic;
-          IMode       : out std_logic_vector(1 downto 0);
-          Halt        : out std_logic;
-          NoRead      : out std_logic;
-          Write       : out std_logic;
-          XYbit_undoc : out std_logic
-       );
-    end component;
-
-    component T80_ALU
-        generic(
-            Mode : integer := 0;
-            Flag_C : integer := 0;
-            Flag_N : integer := 1;
-            Flag_P : integer := 2;
-            Flag_X : integer := 3;
-            Flag_H : integer := 4;
-            Flag_Y : integer := 5;
-            Flag_Z : integer := 6;
-            Flag_S : integer := 7
-        );
-        port(
-            Arith16         : in  std_logic;
-            Z16             : in  std_logic;
-            WZ              : in  std_logic_vector(15 downto 0);
-            XY_State            : in  std_logic_vector(1 downto 0);
-            ALU_Op          : in  std_logic_vector(3 downto 0);
-            IR              : in  std_logic_vector(5 downto 0);
-            ISet            : in  std_logic_vector(1 downto 0);
-            BusA            : in  std_logic_vector(7 downto 0);
-            BusB            : in  std_logic_vector(7 downto 0);
-            F_In            : in  std_logic_vector(7 downto 0);
-            Q               : out std_logic_vector(7 downto 0);
-            F_Out           : out std_logic_vector(7 downto 0)
-        );
-    end component;
-
-    component T80_Reg
-        port(
-            Clk     : in  std_logic;
-            CEN     : in  std_logic;
-            WEH     : in  std_logic;
-            WEL     : in  std_logic;
-            AddrA   : in  std_logic_vector(2 downto 0);
-            AddrB   : in  std_logic_vector(2 downto 0);
-            AddrC   : in  std_logic_vector(2 downto 0);
-            DIH     : in  std_logic_vector(7 downto 0);
-            DIL     : in  std_logic_vector(7 downto 0);
-            DOAH    : out std_logic_vector(7 downto 0);
-            DOAL    : out std_logic_vector(7 downto 0);
-            DOBH    : out std_logic_vector(7 downto 0);
-            DOBL    : out std_logic_vector(7 downto 0);
-            DOCH    : out std_logic_vector(7 downto 0);
-            DOCL    : out std_logic_vector(7 downto 0);
-            DOR     : out std_logic_vector(127 downto 0);
-            DIRSet  : in  std_logic;
-            DIR     : in  std_logic_vector(127 downto 0)
-        );
-    end component;
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
 
 	-- Registers
 	signal ACC, F               : std_logic_vector(7 downto 0);
@@ -283,9 +154,13 @@ architecture rtl of T80 is
 
 	-- Help Registers
 	signal WZ                   : std_logic_vector(15 downto 0);        -- MEMPTR register
+	signal TmpAddr2             : std_logic_vector(15 downto 0);        -- Temporary address register
 	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
 	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
 	signal RegBusA_r            : std_logic_vector(15 downto 0);
+	signal MULU_Prod32          : std_logic_vector(31 downto 0);
+	signal MULU_tmp             : std_logic_vector(31 downto 0);
+	signal MULU_Fakt1           : std_logic_vector(15 downto 0);
 
 	signal ID16                 : signed(15 downto 0);
 	signal Save_Mux             : std_logic_vector(7 downto 0);
@@ -295,8 +170,8 @@ architecture rtl of T80 is
 	signal IntE_FF1             : std_logic;
 	signal IntE_FF2             : std_logic;
 	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
+	signal BusReq_s             : std_logic := '0';
+	signal BusAck               : std_logic := '0';
 	signal ClkEn                : std_logic;
 	signal NMI_s                : std_logic;
 	signal IStatus              : std_logic_vector(1 downto 0);
@@ -344,6 +219,7 @@ architecture rtl of T80 is
 	signal Set_BusA_To          : std_logic_vector(3 downto 0);
 	signal ALU_Op               : std_logic_vector(3 downto 0);
 	signal Save_ALU             : std_logic;
+	signal Rot_Akku             : std_logic;
 	signal PreserveC            : std_logic;
 	signal Arith16              : std_logic;
 	signal Set_Addr_To          : std_logic_vector(2 downto 0);
@@ -355,6 +231,8 @@ architecture rtl of T80 is
 	signal LDZ                  : std_logic;
 	signal LDW                  : std_logic;
 	signal LDSPHL               : std_logic;
+	signal LDHLSP               : std_logic;
+	signal ADDSPdd              : std_logic;
 	signal IORQ_i               : std_logic;
 	signal Special_LD           : std_logic_vector(2 downto 0);
 	signal ExchangeDH           : std_logic;
@@ -373,14 +251,16 @@ architecture rtl of T80 is
 	signal I_RRD                : std_logic;
 	signal I_RXDD               : std_logic;
 	signal I_INRC               : std_logic;
+	signal I_MULUB              : std_logic;
+	signal I_MULU               : std_logic;
 	signal SetWZ                : std_logic_vector(1 downto 0);
 	signal SetDI                : std_logic;
 	signal SetEI                : std_logic;
 	signal IMode                : std_logic_vector(1 downto 0);
 	signal Halt                 : std_logic;
 	signal XYbit_undoc          : std_logic;
+	signal No_PC                : std_logic;
 	signal DOR                  : std_logic_vector(127 downto 0);
-	signal IVector              : std_logic_vector(7 downto 0);
 
 begin
 
@@ -419,6 +299,7 @@ begin
 			Set_BusA_To => Set_BusA_To,
 			ALU_Op      => ALU_Op,
 			Save_ALU    => Save_ALU,
+			Rot_Akku    => Rot_Akku,
 			PreserveC   => PreserveC,
 			Arith16     => Arith16,
 			Set_Addr_To => Set_Addr_To,
@@ -431,6 +312,8 @@ begin
 			LDZ         => LDZ,
 			LDW         => LDW,
 			LDSPHL      => LDSPHL,
+			LDHLSP      => LDHLSP,
+			ADDSPdd     => ADDSPdd,
 			Special_LD  => Special_LD,
 			ExchangeDH  => ExchangeDH,
 			ExchangeRp  => ExchangeRp,
@@ -447,6 +330,8 @@ begin
 			I_RLD       => I_RLD,
 			I_RRD       => I_RRD,
 			I_INRC      => I_INRC,
+			I_MULUB     => I_MULUB,
+			I_MULU      => I_MULU,
 			SetWZ       => SetWZ,
 			SetDI       => SetDI,
 			SetEI       => SetEI,
@@ -454,6 +339,8 @@ begin
 			Halt        => Halt,
 			NoRead      => NoRead,
 			Write       => Write,
+			R800_mode   => R800_mode,
+			No_PC       => No_PC,
 			XYbit_undoc => XYbit_undoc);
 
 	alu : T80_ALU
@@ -473,6 +360,7 @@ begin
 			WZ      => WZ,
 			XY_State=> XY_State,
 			ALU_Op  => ALU_Op_r,
+			Rot_Akku    => Rot_Akku,
 			IR      => IR(5 downto 0),
 			ISet    => ISet,
 			BusA    => BusA,
@@ -497,6 +385,8 @@ begin
 	process (RESET_n, CLK_n)
 		variable n : std_logic_vector(7 downto 0);
 		variable ioq : std_logic_vector(8 downto 0);
+		variable temp_c : unsigned(8 downto 0);
+		variable temp_h : unsigned(4 downto 0);
 	begin
 		if RESET_n = '0' then
 			PC <= (others => '0');  -- Program Counter
@@ -511,6 +401,11 @@ begin
 
 			ACC <= (others => '1');
 			F <= (others => '1');
+			if Mode = 3 then
+				ACC <= (others => '0');
+				F <= "11110000";
+			end if;
+
 			Ap <= (others => '1');
 			Fp <= (others => '1');
 			I <= (others => '0');
@@ -539,7 +434,7 @@ begin
 				R   <= unsigned(DIR(47 downto 40));
 				SP  <= unsigned(DIR(63 downto 48));
 				PC  <= unsigned(DIR(79 downto 64));
-				A   <= DIR(79 downto 64);
+				A <= DIR(79 downto 64);
 				IStatus <= DIR(209 downto 208);
 
 			elsif ClkEn = '1' then
@@ -549,7 +444,27 @@ begin
 
 				MCycles <= MCycles_d;
 
-				if IMode /= "11" then
+				if LDHLSP = '1' and MCycle = "011" and TState = 1 then
+					temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
+					temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
+					F(Flag_Z) <= '0';
+					F(Flag_N) <= '0';
+					F(Flag_H) <= temp_h(4);
+					F(Flag_C) <= temp_c(8);
+				end if;
+
+				if ADDSPdd = '1' and TState = 1 then
+					temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
+					temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
+					F(Flag_Z) <= '0';
+					F(Flag_N) <= '0';
+					F(Flag_H) <= temp_h(4);
+					F(Flag_C) <= temp_c(8);
+				end if;
+
+				if Mode = 3 then
+					IStatus <= "10";
+				elsif IMode /= "11" then
 					IStatus <= IMode;
 				end if;
 
@@ -579,16 +494,15 @@ begin
 							IR <= "11111111";
 						elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
 							IR <= "00000000";
-							-- DMB: It's important to catch the interrupt vector at
-							-- the start of T3, not the middle as the old code
-							-- (using WZ) did. This caused a issue with the Z80
-							-- Second Processor on the GODIL due to the pullups
-							-- (esp on D0)
-							IVector <= DInst;
 						else
 							IR <= DInst;
 						end if;
 
+						if Mode <= 1 and IntCycle = '1' and IStatus = "10" then
+							-- IM2 vector address low byte from bus
+							WZ(7 downto 0) <= DInst;
+						end if;
+
 						ISet <= "00";
 						if Prefix /= "00" then
 							if Prefix = "11" then
@@ -636,11 +550,12 @@ begin
 						elsif MCycle = MCycles and NMICycle = '1' then
 							A <= "0000000001100110";
 							PC <= "0000000001100110";
-						elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						elsif ((Mode /= 3 and MCycle = "011") or (Mode = 3 and MCycle = "100"))
+							and IntCycle = '1' and IStatus = "10" then
 							A(15 downto 8) <= I;
-							A(7 downto 0) <= IVector;
+							A(7 downto 0) <= WZ(7 downto 0);
 							PC(15 downto 8) <= unsigned(I);
-							PC(7 downto 0) <= unsigned(IVector);
+							PC(7 downto 0) <= unsigned(WZ(7 downto 0));
 						else
 							case Set_Addr_To is
 							when aXY =>
@@ -700,7 +615,12 @@ begin
 									end if;
 								end if;
 							when others =>
-								A <= std_logic_vector(PC);
+								if ISet = "10" and IR(7 downto 4) = x"B" and IR(2 downto 1) = "01" and MCycle = 3 and No_BTR = '0' then
+									-- INIR, INDR, OTIR, OTDR
+									A <= RegBusA_r;
+								elsif No_PC = '0' or No_BTR = '1' or (I_DJNZ = '1' and IncDecZ = '1') or Mode > 1 then
+									A <= std_logic_vector(PC);
+								end if;
 							end case;
 						end if;
 
@@ -711,29 +631,50 @@ begin
 						Save_ALU_r <= Save_ALU;
 						ALU_Op_r <= ALU_Op;
 
-						if I_CPL = '1' then
-							-- CPL
-							ACC <= not ACC;
-							F(Flag_Y) <= not ACC(5);
-							F(Flag_H) <= '1';
-							F(Flag_X) <= not ACC(3);
-							F(Flag_N) <= '1';
-						end if;
-						if I_CCF = '1' then
-							-- CCF
-							F(Flag_C) <= not F(Flag_C);
-							F(Flag_Y) <= ACC(5);
-							F(Flag_H) <= F(Flag_C);
-							F(Flag_X) <= ACC(3);
-							F(Flag_N) <= '0';
-						end if;
-						if I_SCF = '1' then
-							-- SCF
-							F(Flag_C) <= '1';
-							F(Flag_Y) <= ACC(5);
-							F(Flag_H) <= '0';
-							F(Flag_X) <= ACC(3);
-							F(Flag_N) <= '0';
+						if Mode = 3 then
+							if I_CPL = '1' then
+								-- CPL
+								ACC <= not ACC;
+								F(Flag_H) <= '1';
+								F(Flag_N) <= '1';
+							end if;
+							if I_CCF = '1' then
+								-- CCF
+								F(Flag_C) <= not F(Flag_C);
+								F(Flag_H) <= '0';
+								F(Flag_N) <= '0';
+							end if;
+							if I_SCF = '1' then
+								-- SCF
+								F(Flag_C) <= '1';
+								F(Flag_H) <= '0';
+								F(Flag_N) <= '0';
+							end if;
+						else
+							if I_CPL = '1' then
+								-- CPL
+								ACC <= not ACC;
+								F(Flag_Y) <= not ACC(5);
+								F(Flag_H) <= '1';
+								F(Flag_X) <= not ACC(3);
+								F(Flag_N) <= '1';
+							end if;
+							if I_CCF = '1' then
+								-- CCF
+								F(Flag_C) <= not F(Flag_C);
+								F(Flag_Y) <= ACC(5);
+								F(Flag_H) <= F(Flag_C);
+								F(Flag_X) <= ACC(3);
+								F(Flag_N) <= '0';
+							end if;
+							if I_SCF = '1' then
+								-- SCF
+								F(Flag_C) <= '1';
+								F(Flag_Y) <= ACC(5);
+								F(Flag_H) <= '0';
+								F(Flag_X) <= ACC(3);
+								F(Flag_N) <= '0';
+							end if;
 						end if;
 					end if;
 
@@ -784,6 +725,11 @@ begin
 						end if;
 					end if;
 
+					if ADDSPdd = '1' and TState = 2 then
+						WZ <= std_logic_vector(SP);
+						SP <= unsigned(signed(SP)+signed(Save_Mux));
+					end if;
+
 					if LDSPHL = '1' then
 						SP <= unsigned(RegBusC);
 					end if;
@@ -931,7 +877,12 @@ begin
 					when "11001" =>
 						SP(15 downto 8) <= unsigned(Save_Mux);
 					when "11011" =>
-						F <= Save_Mux;
+						if Mode = 3 then
+							F(7 downto 4) <= Save_Mux(7 downto 4);
+							F(3 downto 0) <= "0000"; -- bit 3 to 0 always return 0
+						else
+							F <= Save_Mux;
+						end if;
 					when others =>
 					end case;
 					if XYbit_undoc='1' then
@@ -942,6 +893,42 @@ begin
 		end if;
 	end process;
 
+---------------------------------------------------------------------------
+--
+-- Multiply
+--
+---------------------------------------------------------------------------
+	process (CLK_n, ACC, RegBusB, MULU_tmp, MULU_Fakt1, MULU_Prod32)
+	begin
+
+		MULU_tmp(31 downto 12) <= std_logic_vector((unsigned(MULU_Fakt1)*unsigned(MULU_Prod32(3 downto 0)))+unsigned("0000"&MULU_Prod32(31 downto 16)));
+		MULU_tmp(11 downto 0) <= MULU_Prod32(15 downto 4);
+
+		if rising_edge(CLK_n) then
+			if ClkEn = '1' then
+				if T_Res='1' then
+					if I_MULUB='1' then
+						MULU_Prod32(7 downto 0) <= ACC;
+						MULU_Prod32(15 downto 8) <= "--------";
+						MULU_Prod32(31 downto 16) <= X"0000";
+						MULU_Fakt1(7 downto 0) <= "00000000";
+						if Set_BusB_To(0) = '1' then
+							MULU_Fakt1(15 downto 8) <= RegBusB(7 downto 0);
+						else
+							MULU_Fakt1(15 downto 8) <= RegBusB(15 downto 8);
+						end if;
+					else
+						MULU_Prod32(15 downto 0) <= RegBusA;
+						MULU_Prod32(31 downto 16) <= X"0000";
+						MULU_Fakt1 <= RegBusB;
+					end if;
+				else
+					MULU_Prod32 <= MULU_tmp;
+				end if;
+			end if;
+		end if;
+	end process;
+
 ---------------------------------------------------------------------------
 --
 -- BC('), DE('), HL('), IX and IY
@@ -997,7 +984,9 @@ begin
 				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
 			-- EX HL,DL
 			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			Alternate & "01" when (ExchangeDH = '1' or I_MULU = '1') and TState = 4 else
+			-- LDHLSP
+			"010" when LDHLSP = '1' and TState = 4 else
 			-- Bus A / Write
 			RegAddrA_r;
 
@@ -1010,8 +999,8 @@ begin
 	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
 			signed(RegBusA) + 1;
 
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, I_MULU, T_Res,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP)
 	begin
 		RegWEH <= '0';
 		RegWEL <= '0';
@@ -1025,11 +1014,21 @@ begin
 			end case;
 		end if;
 
+		if I_MULU = '1' and (T_Res = '1' or TState = 4) then    -- TState = 4 DE write
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
 		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
 			RegWEH <= '1';
 			RegWEL <= '1';
 		end if;
 
+		if LDHLSP = '1' and MCycle = "010" and TState = 4 then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
 		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
 			case IncDec_16(1 downto 0) is
 			when "00" | "01" | "10" =>
@@ -1040,12 +1039,29 @@ begin
 		end if;
 	end process;
 
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	TmpAddr2 <= std_logic_vector(unsigned(signed(SP) + signed(Save_Mux)));
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16, I_MULU, MULU_Prod32, MULU_tmp, T_Res,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP, TmpAddr2)
 	begin
 		RegDIH <= Save_Mux;
 		RegDIL <= Save_Mux;
 
+		if I_MULU = '1' then
+			if T_Res = '1' then
+				RegDIH <= MULU_Prod32(31 downto 24);
+				RegDIL <= MULU_Prod32(23 downto 16);
+			else
+				RegDIH <= MULU_tmp(15 downto 8);    -- TState = 4 DE write
+				RegDIL <= MULU_tmp(7 downto 0);
+			end if;
+		end if;
+
+		if LDHLSP = '1' and MCycle = "010" and TState = 4 then
+			RegDIH <= TmpAddr2(15 downto 8);
+			RegDIL <= TmpAddr2(7 downto 0);
+		end if;
+
 		if ExchangeDH = '1' and TState = 3 then
 			RegDIH <= RegBusB(15 downto 8);
 			RegDIL <= RegBusB(7 downto 0);
@@ -1176,13 +1192,12 @@ begin
 	TS <= std_logic_vector(TState);
 	DI_Reg <= DI;
 	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
+	BUSAK_n <= not (BusAck and RESET_n);
 	IntCycle_n <= not IntCycle;
 	NMICycle_n <= not NMICycle;
 	IntE <= IntE_FF1;
 	IORQ <= IORQ_i;
 	Stop <= I_DJNZ;
-
 -------------------------------------------------------------------------
 --
 -- Main state machine
@@ -1196,7 +1211,7 @@ begin
 			TState <= "000";
 			Pre_XY_F_M <= "000";
 			Halt_FF <= '0';
-			BusAck <= '0';
+			--BusAck <= '0';
 			NMICycle <= '0';
 			IntCycle <= '0';
 			IntE_FF1 <= '0';
@@ -1205,10 +1220,9 @@ begin
 			Auto_Wait_t1 <= '0';
 			Auto_Wait_t2 <= '0';
 			M1_n <= '1';
-			BusReq_s <= '0';
+			--BusReq_s <= '0';
 			NMI_s <= '0';
 		elsif rising_edge(CLK_n) then
-
 			if DIRSet = '1' then
 				IntE_FF2 <= DIR(211);
 				IntE_FF1 <= DIR(210);
@@ -1256,13 +1270,20 @@ begin
 						BusAck <= '0';
 						if TState = 2 and Wait_n = '0' then
 						elsif T_Res = '1' then
-							if Halt = '1' then
+							if Halt = '1' and  ( not(Mode = 3 and INT_n = '0' and IntE_FF1 = '0')) then  -- halt bug when Mode = 3 , INT_n = '0' and IME=0
 								Halt_FF <= '1';
 							end if;
 							if BusReq_s = '1' then
 								BusAck <= '1';
 							else
 								TState <= "001";
+								if (IntCycle = '1' and Mode = 3) then -- GB: read interrupt at MCycle 3
+									if (MCycle = "010") then
+										M1_n <= '0';
+									else
+										M1_n <= '1';
+									end if;
+								end if;
 								if NextIs_XY_Fetch = '1' then
 									MCycle <= "110";
 									Pre_XY_F_M <= MCycle;
@@ -1284,6 +1305,8 @@ begin
 										IntCycle <= '1';
 										IntE_FF1 <= '0';
 										IntE_FF2 <= '0';
+									elsif (Halt_FF = '1' and INT_n = '0' and Mode = 3) then
+										Halt_FF <= '0';
 									end if;
 								else
 									MCycle <= std_logic_vector(unsigned(MCycle) + 1);

src/T80/T80_ALU.vhd

@@ -89,6 +89,7 @@ entity T80_ALU is
 		WZ              : in  std_logic_vector(15 downto 0);
 		XY_State		    : in  std_logic_vector(1 downto 0);
 		ALU_Op          : in  std_logic_vector(3 downto 0);
+		Rot_Akku        : in  std_logic;
 		IR              : in  std_logic_vector(5 downto 0);
 		ISet            : in  std_logic_vector(1 downto 0);
 		BusA            : in  std_logic_vector(7 downto 0);
@@ -158,7 +159,7 @@ begin
 		end if;
 	end process;
 
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, WZ, XY_State)
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, Rot_Akku, WZ, XY_State)
 		variable Q_t : std_logic_vector(7 downto 0);
 		variable DAA_Q : unsigned(8 downto 0);
 	begin
@@ -220,35 +221,64 @@ begin
 			end if;
 		when "1100" =>
 			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
+			if Mode = 3 then
+				F_Out(Flag_H) <= '0';
+				F_Out(Flag_C) <= F_In(Flag_C);
+				DAA_Q(7 downto 0) := unsigned(BusA);
+				DAA_Q(8) := '0';
+				if F_In(Flag_N) = '0' then
+					-- After addition
+					-- Alow > 9 or H = 1
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+							DAA_Q := DAA_Q + 6;
+					end if;
+					-- new Ahigh > 9 or C = 1
+					if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q + 96; -- 0x60
+					end if;
+				else
+					-- After subtraction
+					if F_In(Flag_H) = '1' then
+						DAA_Q := DAA_Q - 6;
+						if F_In(Flag_C) = '0' then
+							DAA_Q(8) := '0';
+						end if;
+					end if;
+					if F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q - 96; -- 0x60
 					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
 				end if;
 			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
+				F_Out(Flag_H) <= F_In(Flag_H);
+				F_Out(Flag_C) <= F_In(Flag_C);
+				DAA_Q(7 downto 0) := unsigned(BusA);
+				DAA_Q(8) := '0';
+				if F_In(Flag_N) = '0' then
+					-- After addition
+					-- Alow > 9 or H = 1
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+						if (DAA_Q(3 downto 0) > 9) then
+							F_Out(Flag_H) <= '1';
+						else
+							F_Out(Flag_H) <= '0';
+						end if;
+						DAA_Q := DAA_Q + 6;
+					end if;
+					-- new Ahigh > 9 or C = 1
+					if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q + 96; -- 0x60
+					end if;
+				else
+					-- After subtraction
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+						if DAA_Q(3 downto 0) > 5 then
+							F_Out(Flag_H) <= '0';
+						end if;
+						DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+					end if;
+					if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q - 352; -- 0x160
 					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
 				end if;
 			end if;
 			F_Out(Flag_X) <= DAA_Q(3);
@@ -368,6 +398,9 @@ begin
 				F_Out(Flag_S) <= F_In(Flag_S);
 				F_Out(Flag_Z) <= F_In(Flag_Z);
 			end if;
+			if Mode = 3 and Rot_Akku = '1'  then
+					F_Out(Flag_Z) <= '0';
+			end if; 
 		when others =>
 			null;
 		end case;

src/T80/T80_Pack.vhd

@@ -11,7 +11,7 @@
 --
 -- Z80 compatible microprocessor core
 --
--- Version : 0242
+-- Version : 0250
 --
 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
 --
@@ -84,7 +84,7 @@ package T80_Pack is
 	port(
 		RESET_n         : in std_logic;
 		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
+		CEN             : in std_logic;
 		WAIT_n          : in std_logic;
 		INT_n           : in std_logic;
 		NMI_n           : in std_logic;
@@ -96,16 +96,18 @@ package T80_Pack is
 		RFSH_n          : out std_logic;
 		HALT_n          : out std_logic;
 		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
+		A               : out std_logic_vector(15 downto 0);
 		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
+		DI              : in std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
 		IntCycle_n      : out std_logic;
 		NMICycle_n      : out std_logic;
 		IntE            : out std_logic;
 		Stop            : out std_logic;
+		R800_mode       : in  std_logic := '0';
+		out0            : in  std_logic := '0';  -- 0 => OUT(C),0, 1 => OUT(C),255
 		REG             : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
 		DIRSet          : in  std_logic := '0';
 		DIR             : in  std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
@@ -114,24 +116,24 @@ package T80_Pack is
 
 	component T80_Reg
 	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA                   : in std_logic_vector(2 downto 0);
-		AddrB                   : in std_logic_vector(2 downto 0);
-		AddrC                   : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH                    : out std_logic_vector(7 downto 0);
-		DOAL                    : out std_logic_vector(7 downto 0);
-		DOBH                    : out std_logic_vector(7 downto 0);
-		DOBL                    : out std_logic_vector(7 downto 0);
-		DOCH                    : out std_logic_vector(7 downto 0);
-		DOCL                    : out std_logic_vector(7 downto 0);
-		DOR                     : out std_logic_vector(127 downto 0);
-		DIRSet                  : in  std_logic;
-		DIR                     : in  std_logic_vector(127 downto 0)
+		Clk             : in std_logic;
+		CEN             : in std_logic;
+		WEH             : in std_logic;
+		WEL             : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH             : in std_logic_vector(7 downto 0);
+		DIL             : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0);
+		DOR             : out std_logic_vector(127 downto 0);
+		DIRSet          : in  std_logic;
+		DIR             : in  std_logic_vector(127 downto 0)
 	);
 	end component;
 
@@ -168,6 +170,7 @@ package T80_Pack is
 		ALU_Op                  : out std_logic_vector(3 downto 0);
 			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
 		Save_ALU                : out std_logic;
+		Rot_Akku                : out std_logic;
 		PreserveC               : out std_logic;
 		Arith16                 : out std_logic;
 		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
@@ -181,7 +184,7 @@ package T80_Pack is
 		LDW                     : out std_logic;
 		LDSPHL                  : out std_logic;
 		LDHLSP                  : out std_logic;
-		ADDSPdd						: out std_logic;
+		ADDSPdd                 : out std_logic;
 		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
 		ExchangeDH              : out std_logic;
 		ExchangeRp              : out std_logic;
@@ -198,12 +201,17 @@ package T80_Pack is
 		I_RLD                   : out std_logic;
 		I_RRD                   : out std_logic;
 		I_INRC                  : out std_logic;
+		I_MULUB                 : out std_logic;
+		I_MULU                  : out std_logic;
+		SetWZ                   : out std_logic_vector(1 downto 0);
 		SetDI                   : out std_logic;
 		SetEI                   : out std_logic;
 		IMode                   : out std_logic_vector(1 downto 0);
 		Halt                    : out std_logic;
 		NoRead                  : out std_logic;
 		Write                   : out std_logic;
+		R800_mode               : in  std_logic;
+		No_PC                   : out std_logic;
 		XYbit_undoc             : out std_logic
 	);
 	end component;
@@ -223,7 +231,10 @@ package T80_Pack is
 	port(
 		Arith16         : in  std_logic;
 		Z16             : in  std_logic;
+		WZ              : in  std_logic_vector(15 downto 0);
+		XY_State        : in  std_logic_vector(1 downto 0);
 		ALU_Op          : in  std_logic_vector(3 downto 0);
+		Rot_Akku        : in  std_logic;
 		IR              : in  std_logic_vector(5 downto 0);
 		ISet            : in  std_logic_vector(1 downto 0);
 		BusA            : in  std_logic_vector(7 downto 0);

src/T80/T80a.vhd

@@ -203,7 +203,7 @@ begin
     begin
         if CLK_n'event and CLK_n = '0' then
             if CEN = '1' then
-                Wait_s <= WAIT_n;
+                Wait_s <= WAIT_n or (IORQ_n_i and MREQ_n_i);
                 if TState = "011" and BUSAK_n_i = '1' then
                     DI_Reg <= to_x01(Din);
                 end if;

src/Z80CpuMon.vhd

@@ -116,7 +116,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
     signal SS_Step        : std_logic;
     signal SS_Step_held   : std_logic;
     signal CountCycle     : std_logic;
-    signal special        : std_logic_vector(2 downto 0);
+    signal int_ctrl       : std_logic_vector(7 downto 0);
     signal skipNextOpcode : std_logic;
 
     signal Regs           : std_logic_vector(255 downto 0);
@@ -150,6 +150,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
     signal BUSRQ_n_sync   : std_logic;
     signal INT_n_sync     : std_logic;
     signal NMI_n_sync     : std_logic;
+    signal RESET_n_sync   : std_logic;
 
     signal Read_n         : std_logic;
     signal Read_n0        : std_logic;
@@ -218,7 +219,7 @@ begin
         WrIO_n       => WriteIO_n,
         Sync         => Sync,
         Rdy          => open,
-        nRSTin       => RESET_n,
+        nRSTin       => RESET_n_sync,
         nRSTout      => cpu_reset_n,
         CountCycle   => CountCycle,
         trig         => trig,
@@ -242,7 +243,7 @@ begin
         DataOut      => memory_dout,
         DataIn       => memory_din,
         Done         => memory_done,
-        Special      => special,
+        int_ctrl     => int_ctrl,
         SS_Single    => SS_Single,
         SS_Step      => SS_Step
     );
@@ -283,9 +284,31 @@ begin
     int_gen : process(CLK_n)
     begin
         if rising_edge(CLK_n) then
-            BUSRQ_n_sync <= BUSRQ_n;
-            NMI_n_sync   <= NMI_n or special(1);
-            INT_n_sync   <= INT_n or special(0);
+
+            if int_ctrl(1) = '1' then
+                BUSRQ_n_sync <= int_ctrl(0);
+            else
+                BUSRQ_n_sync <= BUSRQ_n or (int_ctrl(0) and SS_single);
+            end if;
+
+            if int_ctrl(3) = '1' then
+                INT_n_sync <= int_ctrl(2);
+            else
+                INT_n_sync <= INT_n or (int_ctrl(2) and SS_single);
+            end if;
+
+            if int_ctrl(5) = '1' then
+                NMI_n_sync <= int_ctrl(4);
+            else
+                NMI_n_sync <= NMI_n or (int_ctrl(4) and SS_single);
+            end if;
+
+            if int_ctrl(7) = '1' then
+                RESET_n_sync <= int_ctrl(6);
+            else
+                RESET_n_sync <= RESET_n or (int_ctrl(6) and SS_single);
+            end if;
+
         end if;
     end process;
 
@@ -401,7 +424,7 @@ begin
     BUSAK_n    <= BUSAK_n_int when state = idle else mon_busak_n;
 
     -- Force the address and databus to tristate when reset is asserted
-    tristate_ad_n <= '0'         when RESET_n = '0' else
+    tristate_ad_n <= '0'         when RESET_n_sync = '0' else
                      BUSAK_n_int when state = idle  else
                      mon_busak_n1;
 

target/lx9_dave/ice6502/board.ucf

@@ -88,7 +88,7 @@ NET "tdin"     LOC="P61"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 NET "tcclk"    LOC="P62"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 
 # Test outputs (connect to J5 on FPGA board)
-#NET "test1"    LOC="P46"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test2"    LOC="P48"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test3"    LOC="P57"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test4"    LOC="P59"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<0>"  LOC="P46"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<1>"  LOC="P47"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<2>"  LOC="P48"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<3>"  LOC="P56"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

target/lx9_dave/ice65c02/board.ucf

@@ -88,7 +88,7 @@ NET "tdin"     LOC="P61"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 NET "tcclk"    LOC="P62"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 
 # Test outputs (connect to J5 on FPGA board)
-#NET "test1"    LOC="P46"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test2"    LOC="P48"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test3"    LOC="P57"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
-#NET "test4"    LOC="P59"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<0>"  LOC="P46"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<1>"  LOC="P47"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<2>"  LOC="P48"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "test<3>"  LOC="P56"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;