44 lines
780 B
VHDL
44 lines
780 B
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13:08:23 06/14/2015
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-- Design Name:
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-- Module Name: Blank - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Blank is
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port(
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-- GODIL Switches
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sw1 : in std_logic;
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-- GODIL LEDs
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led8 : out std_logic
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);
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end Blank;
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architecture Behavioral of Blank is
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begin
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led8 <= sw1;
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end Behavioral;
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