407 lines
13 KiB
VHDL
407 lines
13 KiB
VHDL
-------------------------------------------------------------------------------
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-- Copyright (c) 2019 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : MC6808CpuMon.vhd
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-- /___/ /\ Timestamp : 24/10/2019
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: MC6808CpuMon
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--Device: multiple
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity MC6809CpuMon is
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generic (
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ClkMult : integer;
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ClkDiv : integer;
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ClkPer : real;
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num_comparators : integer;
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avr_prog_mem_size : integer
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);
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port (
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-- Fast clock
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clock : in std_logic;
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-- Quadrature clocks
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E : in std_logic;
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Q : in std_logic;
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--6809 Signals
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DMA_n_BREQ_n : in std_logic;
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-- 6809E Sig
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TSC : in std_logic;
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LIC : out std_logic;
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AVMA : out std_logic;
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BUSY : out std_logic;
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-- Signals common to both 6809 and 6809E
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RES_n : in std_logic;
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NMI_n : in std_logic;
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IRQ_n : in std_logic;
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FIRQ_n : in std_logic;
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HALT_n : in std_logic;
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BS : out std_logic;
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BA : out std_logic;
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R_W_n : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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Data : inout std_logic_vector(7 downto 0);
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- Switches
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sw_reset_cpu : in std_logic;
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sw_reset_avr : in std_logic;
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-- LEDs
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led_bkpt : out std_logic;
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led_trig0 : out std_logic;
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led_trig1 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic;
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-- Debugging signals
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test1 : out std_logic;
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test2 : out std_logic
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);
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end MC6809CpuMon;
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architecture behavioral of MC6809CpuMon is
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signal clock_avr : std_logic;
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signal cpu_clk : std_logic;
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signal cpu_reset_n : std_logic;
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signal busmon_clk : std_logic;
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signal R_W_n_int : std_logic;
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signal NMI_sync : std_logic;
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signal IRQ_sync : std_logic;
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signal FIRQ_sync : std_logic;
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signal HALT_sync : std_logic;
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signal Addr_int : std_logic_vector(15 downto 0);
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signal Din : std_logic_vector(7 downto 0);
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signal Dout : std_logic_vector(7 downto 0);
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signal Dbusmon : std_logic_vector(7 downto 0);
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signal Sync_int : std_logic;
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signal hold : std_logic;
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signal memory_rd : std_logic;
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signal memory_wr : std_logic;
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signal memory_rd1 : std_logic;
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signal memory_wr1 : std_logic;
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signal memory_addr : std_logic_vector(15 downto 0);
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signal memory_addr1 : std_logic_vector(15 downto 0);
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signal memory_dout : std_logic_vector(7 downto 0);
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signal memory_din : std_logic_vector(7 downto 0);
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signal memory_done : std_logic;
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signal Regs : std_logic_vector(111 downto 0);
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signal Regs1 : std_logic_vector(255 downto 0);
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signal last_PC : std_logic_vector(15 downto 0);
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signal ifetch : std_logic;
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signal ifetch1 : std_logic;
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signal SS_Single : std_logic;
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signal SS_Step : std_logic;
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signal CountCycle : std_logic;
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signal int_ctrl : std_logic_vector(7 downto 0);
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signal LIC_int : std_logic;
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signal E_a : std_logic; -- E delayed by 0..20ns
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signal E_b : std_logic; -- E delayed by 20..40ns
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signal E_c : std_logic; -- E delayed by 40..60ns
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signal E_d : std_logic; -- E delayed by 60..80ns
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signal E_e : std_logic; -- E delayed by 80..100ns
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signal E_f : std_logic; -- E delayed by 100..120ns
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signal E_g : std_logic; -- E delayed by 120..140ns
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signal E_h : std_logic; -- E delayed by 120..140ns
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signal E_i : std_logic; -- E delayed by 120..140ns
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signal data_wr : std_logic;
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signal nRSTout : std_logic;
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signal FIRQ_n_masked : std_logic;
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signal IRQ_n_masked : std_logic;
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signal NMI_n_masked : std_logic;
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signal RES_n_masked : std_logic;
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begin
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LIC <= LIC_int;
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-- The following outputs are not implemented
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-- BUSY (6809E mode)
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BUSY <= '0';
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-- The following inputs are not implemented
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-- DMA_n_BREQ_n (6809 mode)
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inst_dcm0 : entity work.DCM0
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generic map (
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ClkMult => ClkMult,
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ClkDiv => ClkDiv,
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ClkPer => ClkPer
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)
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port map(
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CLKIN_IN => clock,
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CLKFX_OUT => clock_avr
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);
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mon : entity work.BusMonCore
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generic map (
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num_comparators => num_comparators,
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avr_prog_mem_size => avr_prog_mem_size
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)
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port map (
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clock_avr => clock_avr,
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busmon_clk => busmon_clk,
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busmon_clken => '1',
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cpu_clk => cpu_clk,
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cpu_clken => '1',
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Addr => Addr_int,
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Data => Dbusmon,
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Rd_n => not R_W_n_int,
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Wr_n => R_W_n_int,
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RdIO_n => '1',
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WrIO_n => '1',
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Sync => Sync_int,
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Rdy => open,
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nRSTin => RES_n_masked,
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nRSTout => cpu_reset_n,
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CountCycle => CountCycle,
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trig => trig,
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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sw_reset_cpu => sw_reset_cpu,
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sw_reset_avr => sw_reset_avr,
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led_bkpt => led_bkpt,
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led_trig0 => led_trig0,
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led_trig1 => led_trig1,
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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Regs => Regs1,
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RdMemOut => memory_rd,
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WrMemOut => memory_wr,
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RdIOOut => open,
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WrIOOut => open,
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AddrOut => memory_addr,
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DataOut => memory_dout,
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DataIn => memory_din,
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Done => memory_done,
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int_ctrl => int_ctrl,
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SS_Step => SS_Step,
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SS_Single => SS_Single
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);
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-- The two int control bits work as follows
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-- 00 -> IRQ_n (enabled)
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-- 01 -> IRQ_n or SS_Single (enabled when free-running)
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-- 10 -> 0 (forced)
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-- 11 -> 1 (disabled)
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FIRQ_n_masked <= int_ctrl(0) when int_ctrl(1) = '1' else
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FIRQ_n or (int_ctrl(0) and SS_single);
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IRQ_n_masked <= int_ctrl(2) when int_ctrl(3) = '1' else
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IRQ_n or (int_ctrl(2) and SS_single);
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NMI_n_masked <= int_ctrl(4) when int_ctrl(5) = '1' else
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NMI_n or (int_ctrl(4) and SS_single);
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RES_n_masked <= int_ctrl(6) when int_ctrl(7) = '1' else
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RES_n or (int_ctrl(6) and SS_single);
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-- The CPU is slightly pipelined and the register update of the last
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-- instruction overlaps with the opcode fetch of the next instruction.
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--
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-- If the single stepping stopped on the opcode fetch cycle, then the registers
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-- valued would not accurately reflect the previous instruction.
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--
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-- To work around this, when single stepping, we stop on the cycle after
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-- the opcode fetch, which means the program counter has advanced.
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--
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-- To hide this from the user single stepping, all we need to do is to
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-- also pipeline the value of the program counter by one stage to compensate.
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last_pc_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if (hold = '0') then
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last_PC <= Regs(95 downto 80);
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end if;
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end if;
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end process;
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Regs1( 79 downto 0) <= Regs( 79 downto 0);
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Regs1( 95 downto 80) <= last_PC;
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Regs1(111 downto 96) <= Regs(111 downto 96);
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Regs1(255 downto 112) <= (others => '0');
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inst_cpu09: entity work.cpu09 port map (
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clk => cpu_clk,
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rst => not cpu_reset_n,
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vma => AVMA,
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lic_out => LIC_int,
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ifetch => ifetch,
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opfetch => open,
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ba => BA,
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bs => BS,
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addr => Addr_int,
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rw => R_W_n_int,
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data_out => Dout,
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data_in => Din,
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irq => IRQ_sync,
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firq => FIRQ_sync,
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nmi => NMI_sync,
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halt => HALT_sync,
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hold => hold,
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Regs => Regs
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);
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-- Synchronize all external inputs, to avoid subtle bugs like missed interrupts
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irq_gen : process(cpu_clk)
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begin
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if falling_edge(cpu_clk) then
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NMI_sync <= not NMI_n_masked;
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IRQ_sync <= not IRQ_n_masked;
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FIRQ_sync <= not FIRQ_n_masked;
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HALT_sync <= not HALT_n;
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end if;
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end process;
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-- This block generates a sync signal that has the same characteristic as
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-- a 6502 sync, i.e. asserted during the fetching the first byte of each instruction.
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-- The below logic copes ifetch being active for all bytes of the instruction.
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sync_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if (hold = '0') then
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ifetch1 <= ifetch and not LIC_int;
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end if;
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end if;
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end process;
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Sync_int <= ifetch and not ifetch1;
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-- This block generates a hold signal that acts as the inverse of a clock enable
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-- for the 6809. See comments above for why this is a cycle later than the way
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-- we would do if for the 6502.
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hold_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if (Sync_int = '1') then
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-- stop after the opcode has been fetched
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hold <= SS_Single;
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elsif (SS_Step = '1') then
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-- start again when the single step command is issues
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hold <= '0';
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end if;
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end if;
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end process;
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-- Only count cycles when the 6809 is actually running
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CountCycle <= not hold;
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-- this block delays memory_rd, memory_wr, memory_addr until the start of the next cpu clk cycle
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-- necessary because the cpu mon block is clocked of the opposite edge of the clock
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-- this allows a full cpu clk cycle for cpu mon reads and writes
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mem_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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memory_rd1 <= memory_rd;
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memory_wr1 <= memory_wr;
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memory_addr1 <= memory_addr;
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end if;
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end process;
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R_W_n <= 'Z' when TSC = '1' else
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'1' when memory_rd1 = '1' else
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'0' when memory_wr1 = '1' else
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R_W_n_int;
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Addr <= (others => 'Z') when TSC = '1' else
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memory_addr1 when (memory_rd1 = '1' or memory_wr1 = '1') else
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Addr_int;
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data_latch : process(E)
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begin
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if falling_edge(E) then
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Din <= Data;
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memory_din <= Data;
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end if;
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end process;
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Data <= memory_dout when TSC = '0' and data_wr = '1' and memory_wr1 = '1' else
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Dout when TSC = '0' and data_wr = '1' and R_W_n_int = '0' and memory_rd1 = '0' else
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(others => 'Z');
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-- Version of data seen by the Bus Mon need to use Din rather than the
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-- external bus value as by the rising edge of cpu_clk we will have stopped driving
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-- the external bus. On the ALS version we get away way this, but on the GODIL
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-- version, due to the pullups, we don't. So all write watch breakpoints see
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-- the data bus as 0xFF.
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Dbusmon <= Din when R_W_n_int = '1' else Dout;
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memory_done <= memory_rd1 or memory_wr1;
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-- Delayed/Deglitched version of the E clock
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e_gen : process(clock)
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begin
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if rising_edge(clock) then
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E_a <= E;
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E_b <= E_a;
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if E_b /= E_i then
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E_c <= E_b;
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end if;
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E_d <= E_c;
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E_e <= E_d;
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E_f <= E_e;
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E_g <= E_f;
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E_h <= E_g;
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E_i <= E_h;
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end if;
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end process;
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-- Main clock timing control
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-- E_c is delayed by 40-60ns
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-- On a real 6809 the output delay (to ADDR, RNW, BA, BS) is 65ns (measured)
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cpu_clk <= not E_c;
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busmon_clk <= E_c;
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-- Data bus write timing control
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--
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-- When data_wr is 0 the bus is high impedence
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--
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-- This avoids bus conflicts when the direction of the data bus
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-- changes from read to write (or visa versa).
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--
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-- Note: on the dragon this is not critical; setting to '1' seemed to work
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data_wr <= Q or E;
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-- Spare pins used for testing
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test1 <= E_a;
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test2 <= E_c;
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end behavioral;
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