176 lines
4.8 KiB
VHDL
176 lines
4.8 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2019 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : MC6809CpuMonALS.vhd
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-- /___/ /\ Timestamp : 24/10/2019
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: MC6809CpuMonALS
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--Device: XC6SLX9
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity MC6809CpuMonALS is
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generic (
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num_comparators : integer := 8; -- default value correct for ALS
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avr_prog_mem_size : integer := 1024 * 9 -- default value correct for ALS
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);
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port (
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clock : in std_logic;
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--6809 Signals
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BUSY : out std_logic;
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E : in std_logic;
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Q : in std_logic;
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AVMA : out std_logic;
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LIC : out std_logic;
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TSC : in std_logic;
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-- Signals common to both 6809 and 6809E
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RES_n : in std_logic;
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NMI_n : in std_logic;
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IRQ_n : in std_logic;
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FIRQ_n : in std_logic;
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HALT_n : in std_logic;
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BS : out std_logic;
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BA : out std_logic;
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R_W_n : out std_logic_vector(1 downto 0);
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Addr : out std_logic_vector(15 downto 0);
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Data : inout std_logic_vector(7 downto 0);
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-- Level Shifers Controls
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OERW_n : out std_logic;
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OEAL_n : out std_logic;
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OEAH_n : out std_logic;
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OED_n : out std_logic;
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DIRD : out std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- ID/mode inputs
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mode : in std_logic;
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id : in std_logic_vector(3 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- Switches
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sw1 : in std_logic;
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sw2 : in std_logic;
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-- LEDs
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led1 : out std_logic;
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led2 : out std_logic;
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led3 : out std_logic
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);
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end MC6809CpuMonALS;
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architecture behavioral of MC6809CpuMonALS is
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signal R_W_n_int : std_logic;
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signal sw_reset_cpu : std_logic;
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signal sw_reset_avr : std_logic;
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signal led_bkpt : std_logic;
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signal led_trig0 : std_logic;
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signal led_trig1 : std_logic;
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begin
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sw_reset_cpu <= not sw1;
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sw_reset_avr <= not sw2;
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led1 <= led_bkpt;
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led2 <= led_trig0;
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led3 <= led_trig1;
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wrapper : entity work.MC6809CpuMon
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generic map (
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ClkMult => 12,
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ClkDiv => 25,
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ClkPer => 20.000,
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num_comparators => num_comparators,
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avr_prog_mem_size => avr_prog_mem_size
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)
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port map (
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-- Fast clock
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clock => clock,
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-- Quadrature clocks
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E => E,
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Q => Q,
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--6809 Signals
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DMA_n_BREQ_n => '1',
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-- 6809E Signals
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TSC => TSC,
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LIC => LIC,
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AVMA => AVMA,
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BUSY => BUSY,
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-- Signals common to both 6809 and 6809E
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RES_n => RES_n,
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NMI_n => NMI_n,
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IRQ_n => IRQ_n,
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FIRQ_n => FIRQ_n,
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HALT_n => HALT_n,
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BS => BS,
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BA => BA,
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R_W_n => R_W_n_int,
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Addr => Addr,
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Data => Data,
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-- External trigger inputs
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trig => trig,
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-- Serial Console
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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-- Switches
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sw_reset_cpu => sw_reset_cpu,
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sw_reset_avr => sw_reset_avr,
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-- LEDs
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led_bkpt => led_bkpt,
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led_trig0 => led_trig0,
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led_trig1 => led_trig1,
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-- OHO_DY1 connected to test connector
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tmosi => open,
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tdin => open,
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tcclk => open,
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-- Debugging signals
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test1 => open,
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test2 => open
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);
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-- 6809 Outputs
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R_W_n <= R_W_n_int & R_W_n_int;
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-- Level Shifter Controls
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OERW_n <= TSC;
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OEAH_n <= TSC;
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OEAL_n <= TSC;
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OED_n <= TSC or not (Q or E);
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DIRD <= R_W_n_int;
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end behavioral;
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