336 lines
9.3 KiB
Verilog
336 lines
9.3 KiB
Verilog
module MultiBootLoader
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(
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input clock,
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input mode,
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input [3:0] id,
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output led1, // red
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output led2, // trig 1
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output led3, // trig 2
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output ld1,
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output ld2,
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output ld3,
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output ld4,
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output ld5,
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output ld6,
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output ld7,
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output ld8
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);
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reg [1:0] clk;
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reg [15:0] icap_din;
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reg icap_ce;
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reg icap_wr;
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reg [15:0] ff_icap_din_reversed;
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reg ff_icap_ce;
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reg ff_icap_wr;
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reg [15:0] MBT_REBOOT = 16'h0000;
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reg [24:0] counter;
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ICAP_SPARTAN6 ICAP_SPARTAN6_inst
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(
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.BUSY (), // Busy output
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.O (), // 16-bit data output
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.CE (ff_icap_ce), // Clock enable input
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.CLK (clk[0]), // Clock input
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.I (ff_icap_din_reversed), // 16-bit data input
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.WRITE (ff_icap_wr) // Write input
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);
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// -------------------------------------------------
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// -- State Machine for ICAP_SPARTAN6 MultiBoot --
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// -- sequence. --
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// -------------------------------------------------
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parameter
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IDLE = 0,
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SYNC_H = 1,
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SYNC_L = 2,
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CWD_H = 3,
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CWD_L = 4,
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GEN1_H = 5,
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GEN1_L = 6,
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GEN2_H = 7,
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GEN2_L = 8,
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GEN3_H = 9,
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GEN3_L = 10,
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GEN4_H = 11,
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GEN4_L = 12,
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GEN5_H = 13,
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GEN5_L = 14,
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NUL_H = 15,
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NUL_L = 16,
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MOD_H = 17,
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MOD_L = 18,
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HCO_H = 19,
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HCO_L = 20,
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RBT_H = 21,
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RBT_L = 22,
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NOOP_0 = 23,
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NOOP_1 = 24,
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NOOP_2 = 25,
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NOOP_3 = 26;
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reg [4:0] state = IDLE;
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reg [4:0] next_state;
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always @(MBT_REBOOT or state or id or mode)
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begin: COMB
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case (state)
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IDLE:
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begin
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if (MBT_REBOOT==16'hffff)
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begin
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next_state = SYNC_H;
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icap_ce = 0;
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icap_wr = 0;
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icap_din = 16'hAA99; // Sync word part 1
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end
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else
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begin
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next_state = IDLE;
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icap_ce = 1;
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icap_wr = 1;
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icap_din = 16'hFFFF; // Null data
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end
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end
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SYNC_H:
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begin
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next_state = SYNC_L;
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icap_ce = 0;
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icap_wr = 0;
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icap_din = 16'h5566; // Sync word part 2
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end
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SYNC_L:
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begin
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next_state = GEN1_H;
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icap_ce = 0;
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icap_wr = 0;
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icap_din = 16'h3261; // Write to GENERAL_1 Register....
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end
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GEN1_H:
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begin
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next_state = GEN1_L;
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icap_ce = 0;
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icap_wr = 0;
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// Loader - 0300-0000
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// Unknown Adapter - 0305-4000
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// 6502 - 030A-8000 - mode 1 id 1110
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// Z80 - 030F-C000 - mode x id 1101
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// 65C02 - 0315-0000 - mode 0 id 1110 (future)
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// 6809 - 031A-4000 - mode x id 1100 (future)
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case ({mode, id})
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5'b11110: icap_din = 16'h8000; // 6502
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5'b11101: icap_din = 16'hC000; // Z80 (mode = 1)
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5'b01101: icap_din = 16'hC000; // Z80 (mode = 0)
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5'b01110: icap_din = 16'h0000; // 65C02
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5'b11100: icap_din = 16'h4000; // 6809 (mode = 1)
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5'b01100: icap_din = 16'h4000; // 6809 (mode = 0)
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default: icap_din = 16'h4000; // Unknown Adapter
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endcase
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end
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GEN1_L:
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begin
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next_state = GEN2_H;
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icap_ce = 0;
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icap_wr = 0;
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icap_din = 16'h3281; // Write to GENERAL_2 Register....
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end
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GEN2_H:
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begin
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next_state = GEN2_L;
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icap_ce = 0;
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icap_wr = 0;
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case ({mode, id})
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5'b11110: icap_din = 16'h030A; // 6502
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5'b11101: icap_din = 16'h030F; // Z80 (mode = 1)
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5'b01101: icap_din = 16'h030F; // Z80 (mode = 0)
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5'b01110: icap_din = 16'h0315; // 65C02
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5'b11100: icap_din = 16'h031A; // 6809 (mode = 1)
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5'b01100: icap_din = 16'h031A; // 6809 (mode = 0)
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default: icap_din = 16'h0305; // Unknown Adapter
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endcase
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end
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GEN2_L:
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begin
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next_state = RBT_H;
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icap_ce = 0;
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icap_wr = 0;
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icap_din = 16'h30A1; // Write to Command Register....
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end
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RBT_H:
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begin
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next_state = RBT_L;
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icap_ce = 0;
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icap_wr = 0;
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icap_din = 16'h000E; // REBOOT Command issued.... value = 0x000E
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end
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RBT_L:
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begin
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next_state = NOOP_0;
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icap_ce = 0;
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icap_wr = 0;
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icap_din = 16'h2000; // NOOP
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end
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NOOP_0:
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begin
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next_state = NOOP_1;
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icap_ce = 0;
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icap_wr = 0;
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icap_din = 16'h2000; // NOOP
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end
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NOOP_1:
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begin
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next_state = NOOP_2;
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icap_ce = 0;
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icap_wr = 0;
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icap_din = 16'h2000; // NOOP
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end
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NOOP_2:
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begin
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next_state = NOOP_3;
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icap_ce = 0;
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icap_wr = 0;
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icap_din = 16'h2000; // NOOP
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end
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NOOP_3:
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begin
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next_state = IDLE;
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icap_ce = 1;
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icap_wr = 1;
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icap_din = 16'h1111; // NULL value
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end
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default:
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begin
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next_state = IDLE;
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icap_ce = 1;
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icap_wr = 1;
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icap_din = 16'h1111; // 16'h1111"
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end
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endcase
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end
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// Clock ICAP_SPARTAN6 and the state machine with clocks that are 90deg phase apart.
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//
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// This is an attempt to cure some reconfiguration unreliability.
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//
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// The problem is that ICAP_SPARTAN2 isn't treated by the Xilinx tools as a synchronous
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// component, so when clocked off the same clock there can be timing issues.
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//
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// The below clocking patten runs the clock at 8MHz (half what it was before).
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//
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// It ensures there is plenty of setup and hold time margin for signals passing
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// between ICAP_SPARTAN6 and the state machine, regardless of which clk edge is used
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// ICAP_SPARTAN6.
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//
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// See this link for some related discussion:
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// https://forums.xilinx.com/t5/Spartan-Family-FPGAs/20Mhz-limitation-for-ICAP-SPARTAN6/td-p/238060
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//
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// NOTE: I'm hedging here, as this bug is quite difficult to reproduce, and changing almost anything
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// (e.g. connecting state to the test pins) causes the problem to go away.
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//
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// At worst this change should be harmless!
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//
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// Dave Banks - 18/07/2017
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always@(posedge clock) begin
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if (clk == 2'b00)
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clk <= 2'b10;
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else if (clk == 2'b10)
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clk <= 2'b11;
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else if (clk == 2'b11)
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clk <= 2'b01;
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else
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clk <= 2'b00;
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end
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// Give a bit of delay before starting the state machine
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always @(posedge clk[1]) begin
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if (MBT_REBOOT == 16'hffff) begin
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state <= next_state;
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end else begin
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MBT_REBOOT <= MBT_REBOOT + 1'b1;
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state <= IDLE;
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end
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end
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always @(posedge clk[1]) begin: ICAP_FF
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// need to reverse bits to ICAP module since D0 bit is read first
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ff_icap_din_reversed[0] <= icap_din[7];
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ff_icap_din_reversed[1] <= icap_din[6];
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ff_icap_din_reversed[2] <= icap_din[5];
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ff_icap_din_reversed[3] <= icap_din[4];
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ff_icap_din_reversed[4] <= icap_din[3];
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ff_icap_din_reversed[5] <= icap_din[2];
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ff_icap_din_reversed[6] <= icap_din[1];
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ff_icap_din_reversed[7] <= icap_din[0];
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ff_icap_din_reversed[8] <= icap_din[15];
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ff_icap_din_reversed[9] <= icap_din[14];
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ff_icap_din_reversed[10] <= icap_din[13];
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ff_icap_din_reversed[11] <= icap_din[12];
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ff_icap_din_reversed[12] <= icap_din[11];
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ff_icap_din_reversed[13] <= icap_din[10];
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ff_icap_din_reversed[14] <= icap_din[9];
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ff_icap_din_reversed[15] <= icap_din[8];
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ff_icap_ce <= icap_ce;
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ff_icap_wr <= icap_wr;
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end
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always@(posedge clock) begin
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counter <= counter + 1'b1;
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end
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assign led1 = 1'b1;
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assign led2 = 1'b0;
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assign led3 = 1'b0;
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assign ld1 = counter[24];
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assign ld2 = ~counter[24];
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assign ld3 = 1'b0;
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assign ld4 = state[4];
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assign ld5 = state[3];
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assign ld6 = state[2];
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assign ld7 = state[1];
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assign ld8 = state[0];
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endmodule
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