mirror of
https://github.com/hoglet67/AtomBusMon.git
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193 lines
11 KiB
VHDL
193 lines
11 KiB
VHDL
-- *****************************************************************************************
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-- AVR constants and type declarations
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-- Version 1.0A(Special version for the JTAG OCD)
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-- Modified 05.05.2004
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-- Designed by Ruslan Lepetenok
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-- *****************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use WORK.SynthCtrlPack.all;
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package AVRuCPackage is
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-- Old package
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type ext_mux_din_type is array(0 to CExtMuxInSize-1) of std_logic_vector(7 downto 0);
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subtype ext_mux_en_type is std_logic_vector(0 to CExtMuxInSize-1);
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-- End of old package
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constant IOAdrWidth : positive := 16;
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type AVRIOAdr_Type is array(0 to 63) of std_logic_vector(IOAdrWidth-1 downto 0);
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constant CAVRIOAdr : AVRIOAdr_Type :=("0000000000000000","0000000000000001","0000000000000010","0000000000000011",
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"0000000000000100","0000000000000101","0000000000000110","0000000000000111",
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"0000000000001000","0000000000001001","0000000000001010","0000000000001011",
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"0000000000001100","0000000000001101","0000000000001110","0000000000001111",
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"0000000000010000","0000000000010001","0000000000010010","0000000000010011",
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"0000000000010100","0000000000010101","0000000000010110","0000000000010111",
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"0000000000011000","0000000000011001","0000000000011010","0000000000011011",
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"0000000000011100","0000000000011101","0000000000011110","0000000000011111",
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"0000000000100000","0000000000100001","0000000000100010","0000000000100011",
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"0000000000100100","0000000000100101","0000000000100110","0000000000100111",
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"0000000000101000","0000000000101001","0000000000101010","0000000000101011",
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"0000000000101100","0000000000101101","0000000000101110","0000000000101111",
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"0000000000110000","0000000000110001","0000000000110010","0000000000110011",
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"0000000000110100","0000000000110101","0000000000110110","0000000000110111",
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"0000000000111000","0000000000111001","0000000000111010","0000000000111011",
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"0000000000111100","0000000000111101","0000000000111110","0000000000111111"); -- I/O port addresses
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-- I/O register file
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constant RAMPZ_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3B#);
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constant SPL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3D#);
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constant SPH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3E#);
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constant SREG_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3F#);
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-- End of I/O register file
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-- UART
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constant UDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0C#);
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constant UBRR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#09#);
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constant USR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0B#);
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constant UCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0A#);
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-- End of UART
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-- Timer/Counter
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constant TCCR0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#33#);
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constant TCCR1A_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2F#);
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constant TCCR1B_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2E#);
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constant TCCR2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#25#);
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constant ASSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#30#);
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constant TIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#37#);
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constant TIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#36#);
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constant TCNT0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#32#);
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constant TCNT2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#24#);
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constant OCR0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#31#);
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constant OCR2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#23#);
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constant TCNT1H_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2D#);
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constant TCNT1L_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2C#);
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constant OCR1AH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2B#);
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constant OCR1AL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2A#);
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constant OCR1BH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#29#);
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constant OCR1BL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#28#);
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constant ICR1AH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#27#);
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constant ICR1AL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#26#);
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-- End of Timer/Counter
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-- Service module
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constant MCUCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#35#);
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constant EIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#39#);
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constant EIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#38#);
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constant EICR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3A#);
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constant MCUSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#34#);
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constant XDIV_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3C#);
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-- End of service module
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-- EEPROM
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constant EEARH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1F#);
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constant EEARL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1E#);
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constant EEDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1D#);
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constant EECR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1C#);
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-- End of EEPROM
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-- SPI
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constant SPDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0F#);
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constant SPSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0E#);
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constant SPCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0D#);
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-- End of SPI
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-- PORTA addresses
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constant PORTA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1B#);
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constant DDRA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1A#);
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constant PINA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#19#);
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-- PORTB addresses
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constant PORTB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#18#);
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constant DDRB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#17#);
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constant PINB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#16#);
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-- PORTC addresses
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constant PORTC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#15#);
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constant DDRC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#14#);
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constant PINC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#13#);
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-- PORTD addresses
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constant PORTD_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#12#);
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constant DDRD_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#11#);
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constant PIND_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#10#);
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-- PORTE addresses
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constant PORTE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#03#);
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constant DDRE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#02#);
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constant PINE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#01#);
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-- PORTF addresses
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constant PORTF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#07#);
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constant DDRF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#08#);
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constant PINF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#00#);
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-- ******************** Parallel port address table **************************************
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constant CMaxNumOfPPort : positive := 6;
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type PPortAdrTbl_Type is record Port_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
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DDR_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
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Pin_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
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end record;
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type PPortAdrTblArray_Type is array (0 to CMaxNumOfPPort-1) of PPortAdrTbl_Type;
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constant PPortAdrArray : PPortAdrTblArray_Type := ((PORTA_Address,DDRA_Address,PINA_Address), -- PORTA
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(PORTB_Address,DDRB_Address,PINB_Address), -- PORTB
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(PORTC_Address,DDRC_Address,PINC_Address), -- PORTC
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(PORTD_Address,DDRD_Address,PIND_Address), -- PORTD
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(PORTE_Address,DDRE_Address,PINE_Address), -- PORTE
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(PORTF_Address,DDRF_Address,PINF_Address)); -- PORTF
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-- ***************************************************************************************
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-- Analog to digital converter
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constant ADCL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#04#);
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constant ADCH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#05#);
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constant ADCSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#06#);
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constant ADMUX_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#07#);
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-- Analog comparator
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constant ACSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#08#);
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-- Watchdog
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constant WDTCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#21#);
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-- JTAG OCDR (ATmega128)
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constant OCDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#22#);
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-- JTAG OCDR (ATmega16)
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--constant OCDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#31#);
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-- ***************************************************************************************
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-- Function declaration
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function LOG2(Number : positive) return natural;
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end AVRuCPackage;
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package body AVRuCPackage is
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-- Functions
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function LOG2(Number : positive) return natural is
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variable Temp : positive;
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begin
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Temp := 1;
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if Number=1 then
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return 0;
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else
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for i in 1 to integer'high loop
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Temp := 2*Temp;
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if Temp>=Number then
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return i;
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end if;
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end loop;
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end if;
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end LOG2;
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-- End of functions
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end AVRuCPackage;
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