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35 lines
1.3 KiB
VHDL
35 lines
1.3 KiB
VHDL
-- *****************************************************************************************
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-- AVR synthesis control package
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-- Version 1.32 (Special version for the JTAG OCD)
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-- Modified 14.07.2005
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-- Designed by Ruslan Lepetenok
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-- *****************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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package SynthCtrlPack is
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-- Please note: Do not change these settings, this is not quite ready yet. Jack Gassett
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-- Control the size of Program and Data memory.
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constant CDATAMEMSIZE : integer := 11; --2^(x+1)=Data SRAM Memory Size (10=2048) (Default 11=4096) (12=8192)
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constant CPROGMEMSIZE : integer := 12; --(2^(x+1))*2)=Program Memory Size (10=4096) (11=8192) (Default 12=16384)
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-- Calculate at Wolfram Alpha (http://www.wolframalpha.com/input/?i=%282^%28x%2B1%29%29*2%29%2Cx%3D12)
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-- Reset generator
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constant CSecondClockUsed : boolean := FALSE;
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constant CImplClockSw : boolean := FALSE;
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-- Only for ASICs
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constant CSynchLatchUsed : boolean := FALSE;
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-- Register file
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constant CResetRegFile : boolean := TRUE;
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-- External multiplexer size
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constant CExtMuxInSize : positive := 16;
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end SynthCtrlPack;
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