mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-06-02 18:41:35 +00:00
43df61cd06
Change-Id: Ic21b05ae8ecb828d32e55fe36be501800cfb3407
445 lines
19 KiB
VHDL
445 lines
19 KiB
VHDL
--************************************************************************************************
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-- Top entity for AVR core
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-- Version 1.82? (Special version for the JTAG OCD)
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-- Designed by Ruslan Lepetenok
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-- Modified 31.08.2006
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-- SLEEP and CLRWDT instructions support was added
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-- BREAK instructions support was added
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-- PM clock enable was added
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use Work.AVR_Core_CompPack.all;
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entity AVR_Core is port(
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--Clock and reset
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cp2 : in std_logic;
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cp2en : in std_logic;
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ireset : in std_logic;
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-- JTAG OCD support
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valid_instr : out std_logic;
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insert_nop : in std_logic;
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block_irq : in std_logic;
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change_flow : out std_logic;
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-- Program Memory
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pc : out std_logic_vector(15 downto 0);
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inst : in std_logic_vector(15 downto 0);
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-- I/O control
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adr : out std_logic_vector(15 downto 0);
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iore : out std_logic;
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iowe : out std_logic;
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-- Data memory control
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ramadr : out std_logic_vector(15 downto 0);
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ramre : out std_logic;
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ramwe : out std_logic;
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cpuwait : in std_logic;
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-- Data paths
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dbusin : in std_logic_vector(7 downto 0);
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dbusout : out std_logic_vector(7 downto 0);
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-- Interrupt
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irqlines : in std_logic_vector(22 downto 0);
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irqack : out std_logic;
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irqackad : out std_logic_vector(4 downto 0);
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--Sleep Control
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sleepi : out std_logic;
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irqok : out std_logic;
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globint : out std_logic;
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--Watchdog
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wdri : out std_logic
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);
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end AVR_Core;
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architecture Struct of avr_core is
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signal dbusin_int : std_logic_vector(7 downto 0);
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signal dbusout_int : std_logic_vector(7 downto 0);
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signal adr_int : std_logic_vector(15 downto 0);
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signal iowe_int : std_logic;
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signal iore_int : std_logic;
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-- SIGNALS FOR INSTRUCTION AND STATES
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signal idc_add : std_logic;
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signal idc_adc : std_logic;
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signal idc_adiw : std_logic;
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signal idc_sub : std_logic;
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signal idc_subi : std_logic;
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signal idc_sbc : std_logic;
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signal idc_sbci : std_logic;
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signal idc_sbiw : std_logic;
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signal adiw_st : std_logic;
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signal sbiw_st : std_logic;
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signal idc_and : std_logic;
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signal idc_andi : std_logic;
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signal idc_or : std_logic;
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signal idc_ori : std_logic;
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signal idc_eor : std_logic;
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signal idc_com : std_logic;
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signal idc_neg : std_logic;
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signal idc_inc : std_logic;
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signal idc_dec : std_logic;
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signal idc_cp : std_logic;
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signal idc_cpc : std_logic;
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signal idc_cpi : std_logic;
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signal idc_cpse : std_logic;
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signal idc_lsr : std_logic;
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signal idc_ror : std_logic;
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signal idc_asr : std_logic;
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signal idc_swap : std_logic;
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signal sbi_st : std_logic;
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signal cbi_st : std_logic;
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signal idc_bst : std_logic;
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signal idc_bset : std_logic;
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signal idc_bclr : std_logic;
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signal idc_sbic : std_logic;
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signal idc_sbis : std_logic;
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signal idc_sbrs : std_logic;
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signal idc_sbrc : std_logic;
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signal idc_brbs : std_logic;
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signal idc_brbc : std_logic;
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signal idc_reti : std_logic;
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signal alu_data_r_in : std_logic_vector(7 downto 0);
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signal alu_data_out : std_logic_vector(7 downto 0);
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signal reg_rd_in : std_logic_vector(7 downto 0);
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signal reg_rd_out : std_logic_vector(7 downto 0);
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signal reg_rr_out : std_logic_vector(7 downto 0);
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signal reg_rd_adr : std_logic_vector(4 downto 0);
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signal reg_rr_adr : std_logic_vector(4 downto 0);
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signal reg_h_out : std_logic_vector(15 downto 0);
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signal reg_z_out : std_logic_vector(15 downto 0);
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signal reg_h_adr : std_logic_vector(2 downto 0);
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signal reg_rd_wr : std_logic;
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signal post_inc : std_logic;
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signal pre_dec : std_logic;
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signal reg_h_wr : std_logic;
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signal sreg_fl_in : std_logic_vector(7 downto 0);
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signal sreg_out : std_logic_vector(7 downto 0);
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signal sreg_fl_wr_en : std_logic_vector(7 downto 0);
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signal spl_out : std_logic_vector(7 downto 0);
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signal sph_out : std_logic_vector(7 downto 0);
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signal rampz_out : std_logic_vector(7 downto 0);
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signal sp_ndown_up : std_logic;
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signal sp_en : std_logic;
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signal bit_num_r_io : std_logic_vector(2 downto 0);
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signal branch : std_logic_vector(2 downto 0);
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signal bitpr_io_out : std_logic_vector(7 downto 0);
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signal bit_pr_sreg_out : std_logic_vector(7 downto 0);
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signal sreg_flags : std_logic_vector(7 downto 0);
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signal bld_op_out : std_logic_vector(7 downto 0);
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signal reg_file_rd_in : std_logic_vector(7 downto 0);
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signal bit_test_op_out : std_logic;
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signal alu_c_flag_out : std_logic;
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signal alu_z_flag_out : std_logic;
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signal alu_n_flag_out : std_logic;
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signal alu_v_flag_out : std_logic;
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signal alu_s_flag_out : std_logic;
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signal alu_h_flag_out : std_logic;
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begin
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pm_fetch_dec_Inst:component pm_fetch_dec port map(
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-- Clock and reset
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cp2 => cp2,
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cp2en => cp2en,
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ireset => ireset,
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-- JTAG OCD support
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valid_instr => valid_instr,
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insert_nop => insert_nop,
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block_irq => block_irq,
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change_flow => change_flow,
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-- Program memory
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pc => pc,
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inst => inst,
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-- I/O control
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adr => adr_int,
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iore => iore_int,
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iowe => iowe_int,
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-- Data memory control
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ramadr => ramadr,
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ramre => ramre,
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ramwe => ramwe,
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cpuwait => cpuwait,
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-- Data paths
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dbusin => dbusin_int,
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dbusout => dbusout_int,
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-- Interrupt
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irqlines => irqlines,
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irqack => irqack,
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irqackad => irqackad,
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--Sleep
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sleepi => sleepi,
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irqok => irqok,
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--Watchdog
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wdri => wdri,
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-- ALU interface(Data inputs)
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alu_data_r_in => alu_data_r_in,
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-- ALU interface(Instruction inputs)
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idc_add_out => idc_add,
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idc_adc_out => idc_adc,
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idc_adiw_out => idc_adiw,
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idc_sub_out => idc_sub,
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idc_subi_out => idc_subi,
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idc_sbc_out => idc_sbc,
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idc_sbci_out => idc_sbci,
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idc_sbiw_out => idc_sbiw,
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adiw_st_out => adiw_st,
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sbiw_st_out => sbiw_st,
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idc_and_out => idc_and,
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idc_andi_out => idc_andi,
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idc_or_out => idc_or,
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idc_ori_out => idc_ori,
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idc_eor_out => idc_eor,
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idc_com_out => idc_com,
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idc_neg_out => idc_neg,
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idc_inc_out => idc_inc,
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idc_dec_out => idc_dec,
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idc_cp_out => idc_cp,
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idc_cpc_out => idc_cpc,
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idc_cpi_out => idc_cpi,
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idc_cpse_out => idc_cpse,
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idc_lsr_out => idc_lsr,
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idc_ror_out => idc_ror,
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idc_asr_out => idc_asr,
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idc_swap_out => idc_swap,
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-- ALU interface(Data output)
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alu_data_out => alu_data_out,
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-- ALU interface(Flag outputs)
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alu_c_flag_out => alu_c_flag_out,
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alu_z_flag_out => alu_z_flag_out,
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alu_n_flag_out => alu_n_flag_out,
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alu_v_flag_out => alu_v_flag_out,
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alu_s_flag_out => alu_s_flag_out,
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alu_h_flag_out => alu_h_flag_out,
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-- General purpose register file interface
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reg_rd_in => reg_rd_in,
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reg_rd_out => reg_rd_out,
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reg_rd_adr => reg_rd_adr,
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reg_rr_out => reg_rr_out,
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reg_rr_adr => reg_rr_adr,
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reg_rd_wr => reg_rd_wr,
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post_inc => post_inc,
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pre_dec => pre_dec,
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reg_h_wr => reg_h_wr,
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reg_h_out => reg_h_out,
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reg_h_adr => reg_h_adr,
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reg_z_out => reg_z_out,
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-- I/O register file interface
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sreg_fl_in => sreg_fl_in, --??
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globint => sreg_out(7), -- SREG I flag
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sreg_fl_wr_en => sreg_fl_wr_en,
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spl_out => spl_out,
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sph_out => sph_out,
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sp_ndown_up => sp_ndown_up,
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sp_en => sp_en,
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rampz_out => rampz_out,
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-- Bit processor interface
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bit_num_r_io => bit_num_r_io,
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bitpr_io_out => bitpr_io_out,
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branch => branch,
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bit_pr_sreg_out => bit_pr_sreg_out,
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bld_op_out => bld_op_out,
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bit_test_op_out => bit_test_op_out,
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sbi_st_out => sbi_st,
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cbi_st_out => cbi_st,
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idc_bst_out => idc_bst,
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idc_bset_out => idc_bset,
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idc_bclr_out => idc_bclr,
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idc_sbic_out => idc_sbic,
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idc_sbis_out => idc_sbis,
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idc_sbrs_out => idc_sbrs,
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idc_sbrc_out => idc_sbrc,
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idc_brbs_out => idc_brbs,
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idc_brbc_out => idc_brbc,
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idc_reti_out => idc_reti);
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GPRF_Inst:component reg_file port map (
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--Clock and reset
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cp2 => cp2,
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cp2en => cp2en,
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ireset => ireset,
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reg_rd_in => reg_rd_in,
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reg_rd_out => reg_rd_out,
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reg_rd_adr => reg_rd_adr,
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reg_rr_out => reg_rr_out,
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reg_rr_adr => reg_rr_adr,
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reg_rd_wr => reg_rd_wr,
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post_inc => post_inc,
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pre_dec => pre_dec,
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reg_h_wr => reg_h_wr,
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reg_h_out => reg_h_out,
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reg_h_adr => reg_h_adr,
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reg_z_out => reg_z_out);
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BP_Inst:component bit_processor port map(
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--Clock and reset
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cp2 => cp2,
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cp2en => cp2en,
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ireset => ireset,
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bit_num_r_io => bit_num_r_io,
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dbusin => dbusin_int,
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bitpr_io_out => bitpr_io_out,
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sreg_out => sreg_out,
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branch => branch,
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bit_pr_sreg_out => bit_pr_sreg_out,
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bld_op_out => bld_op_out,
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reg_rd_out => reg_rd_out,
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bit_test_op_out => bit_test_op_out,
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-- Instructions and states
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sbi_st => sbi_st,
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cbi_st => cbi_st,
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idc_bst => idc_bst,
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idc_bset => idc_bset,
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idc_bclr => idc_bclr,
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idc_sbic => idc_sbic,
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idc_sbis => idc_sbis,
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idc_sbrs => idc_sbrs,
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idc_sbrc => idc_sbrc,
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idc_brbs => idc_brbs,
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idc_brbc => idc_brbc,
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idc_reti => idc_reti);
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io_dec_Inst:component io_adr_dec port map (
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adr => adr_int,
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iore => iore_int,
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dbusin_int => dbusin_int, -- LOCAL DATA BUS OUTPUT
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dbusin_ext => dbusin, -- EXTERNAL DATA BUS INPUT
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spl_out => spl_out,
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sph_out => sph_out,
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sreg_out => sreg_out,
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rampz_out => rampz_out
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);
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IORegs_Inst: component io_reg_file port map(
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--Clock and reset
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cp2 => cp2,
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cp2en => cp2en,
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ireset => ireset,
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adr => adr_int,
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iowe => iowe_int,
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dbusout => dbusout_int,
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sreg_fl_in => sreg_fl_in,
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sreg_out => sreg_out,
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sreg_fl_wr_en => sreg_fl_wr_en,
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spl_out => spl_out,
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sph_out => sph_out,
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sp_ndown_up => sp_ndown_up,
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sp_en => sp_en,
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rampz_out => rampz_out);
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ALU_Inst:component alu_avr port map(
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-- Data inputs
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alu_data_r_in => alu_data_r_in,
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alu_data_d_in => reg_rd_out,
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alu_c_flag_in => sreg_out(0),
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alu_z_flag_in => sreg_out(1),
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-- Instructions and states
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idc_add => idc_add,
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idc_adc => idc_adc,
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idc_adiw => idc_adiw,
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idc_sub => idc_sub,
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idc_subi => idc_subi,
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idc_sbc => idc_sbc,
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idc_sbci => idc_sbci,
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idc_sbiw => idc_sbiw,
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adiw_st => adiw_st,
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sbiw_st => sbiw_st,
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idc_and => idc_and,
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idc_andi => idc_andi,
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idc_or => idc_or,
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idc_ori => idc_ori,
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idc_eor => idc_eor,
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idc_com => idc_com,
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idc_neg => idc_neg,
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idc_inc => idc_inc,
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idc_dec => idc_dec,
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idc_cp => idc_cp,
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idc_cpc => idc_cpc,
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idc_cpi => idc_cpi,
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idc_cpse => idc_cpse,
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idc_lsr => idc_lsr,
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idc_ror => idc_ror,
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idc_asr => idc_asr,
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idc_swap => idc_swap,
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-- Data outputs
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alu_data_out => alu_data_out,
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-- Flag outputs
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alu_c_flag_out => alu_c_flag_out,
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alu_z_flag_out => alu_z_flag_out,
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alu_n_flag_out => alu_n_flag_out,
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alu_v_flag_out => alu_v_flag_out,
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alu_s_flag_out => alu_s_flag_out,
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alu_h_flag_out => alu_h_flag_out);
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-- Outputs
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adr <= adr_int;
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iowe <= iowe_int;
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iore <= iore_int;
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dbusout <= dbusout_int;
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-- Sleep support
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globint <= sreg_out(7); -- I flag
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end Struct;
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